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Distribution-Compensable Jitter Generator for

Communication Test

Presenter ： Pin-Chong Chen

Advisor ： Tsung-Che Huang

2009/09/21

Y.-H. Chou, T.-H. Wu, P.-C. Chan, and T.-C. Huang, “Distribution-Compensable Jitter Generator for Communication Test ,” 20th VLSI Design/ CAD, Aug. 2009.

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Outline Introduction Programmable Delay Line (PDL) Random Number Generator (RNG)

Normal Distribution RNG Uniform Distribution RNG

Distribution-Compensable Methodology Experiment Results Conclusions

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Introduction In high-speed computer and communication

systems, timing jitter is one of the most critical parameters.

Jitter testing is becoming indispensable. Conventional Jitter Generator is executed by

expensive external testers or instruments. Communication test :(1)Waveform Analyses,

(2)JG/JM and (3)bit error rat test .

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Basic Methodology

Based on the noise/jitter generation structure . The non-linearity and self-jitter of the converter h

ave skew .

Fig. 1. A programmable noise/jitter generator.

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Benchmark DTC’s (1)

Fig. 2. A programmable jitter generator.

Fig. 3. Adopted DCDL.

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Benchmark DTC’s (2)

Fig. 4. Adopted VCDL as a fine-tuned delayline.

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Monte Carlo simulation results

Fig. 5. Transfer function of a 5-bit DTC

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Box-Muller &table-lookup methods

Box-Muller

table-lookup methods

Fig. 6. Typical table lookup methods.

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Ziggurat algorithm

Fig. 7. (a) Ziggurat algorithm and (b) 7-layer Ziggurat diagram.

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Efficient RNG (1) (a) shows the uniform distribution u1,u2 . (b) show the sum of u1 and u2 . (c) show the minimum (min) of u1 and u2 (d) show the maximum (max) of u1 and u2

Fig. 8. Uniform and composed distributions.

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Efficient RNG (2)

),min(:)1(? 321111 uuxxxxuru iiiii

Fig. 9. The ith H- and V-trapezoid pdf’s.

(1)

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Simulations of RNGs

Fig.11. Examples of the V-trapezoid RNGs with the simulation results.

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Jitter Distribution Compensation(1)

Distribution-compensable methodology

RNG (f1(x)) DTC f2(x) chi-square test

Compensation

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Jitter Distribution Compensation(2)

Fig. 12 Compensating example

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Examples

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CONCLUSION In this paper a programmable, fast and area-effic

ient trapezoidal PWL RNG is developed. The speedup and area reduction make it possible to build into SoCs/NoCs.

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Thanks for your attention.