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COMP541COMP541

More on More on State Machines;State Machines;and Video Scanoutand Video Scanout

Montek SinghMontek Singh

Feb 16, 2010Feb 16, 2010

OutlineOutline Last Friday’s labLast Friday’s lab

Tips/discussionTips/discussion

Look at Verilog coding practicesLook at Verilog coding practices Avoid generating latchesAvoid generating latches Parameterized ModulesParameterized Modules

How to generate video signalHow to generate video signal

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What did you have trouble What did you have trouble with in lab?with in lab?

TestingTesting How do you simulate/test a module that How do you simulate/test a module that

outputs a signal every millionth time?outputs a signal every millionth time?

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Off By One?Off By One? Did you have problems if you designed a Did you have problems if you designed a

counter out of one-digit modules?counter out of one-digit modules?

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Good Verilog PracticesGood Verilog Practices Best to use single clock for all FFsBest to use single clock for all FFs

Make all signals synchronous to one clkMake all signals synchronous to one clkno posedge button or posedge pulseno posedge button or posedge pulseno @(signal)no @(signal)

– not supported by current boardnot supported by current board

Avoids “weird” and frustrating problemsAvoids “weird” and frustrating problems

Multiple modulesMultiple modules Tested individuallyTested individually Top level has input and outputsTop level has input and outputs

One module per fileOne module per file Just to make it easier to follow and testJust to make it easier to follow and test

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Button DebounceButton Debounce Mechanical switches can “bounce”Mechanical switches can “bounce” May get a fast series of Hs and LsMay get a fast series of Hs and Ls

10s of milliseconds10s of milliseconds

How do we avoid problems?How do we avoid problems?

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Button Debounce and Button Debounce and SynchronizeSynchronize Let’s try to make it Let’s try to make it simplersimpler this time! this time!

Use it as input to test in an always statement that’s Use it as input to test in an always statement that’s clocked by the master clockclocked by the master clock

State machine to detect down/up?State machine to detect down/up?Wait for Wait for NN clock cycles and then use it! clock cycles and then use it!

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What else did you have What else did you have trouble with in lab?trouble with in lab?

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Assignment (of signals)Assignment (of signals) ContinuousContinuous ProceduralProcedural

Note there are two uses for Note there are two uses for alwaysalwaysTo generate FFs and latches (plus gates)To generate FFs and latches (plus gates)To generate combinational logic onlyTo generate combinational logic only

– Latter does not introduce unnecessary FFs …Latter does not introduce unnecessary FFs …– … … if synthesizer detects all possibilities covered (i.e. no state if synthesizer detects all possibilities covered (i.e. no state

needed)needed)

Look at the synthesizer logLook at the synthesizer log

Procedural Assignment 1Procedural Assignment 1module C2(output reg C = 0, input A, input B);module C2(output reg C = 0, input A, input B);

always @ (A or B)always @ (A or B)

case ({A, B})case ({A, B})

2'b11: C <= 1;2'b11: C <= 1;

default: C <= 0;default: C <= 0;

endcaseendcase

endmoduleendmodule

Schematic next pageSchematic next page

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SchematicSchematic

LUT is a look-up tableLUT is a look-up table Double clicking it showsDouble clicking it shows

Procedural Assignment 2Procedural Assignment 2module C1(output reg C = 0, input A, input B);module C1(output reg C = 0, input A, input B);

always @ (A or B)always @ (A or B)beginbegin

if(A == 1 && B == 1)if(A == 1 && B == 1)C <= 1;C <= 1;

endendendmoduleendmodule

Synthesizer now saysSynthesizer now saysWARNING:Xst:737 - Found 1-bit latch for signal <C>.WARNING:Xst:737 - Found 1-bit latch for signal <C>.WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant WARNING:Xst:1426 - The value init of the FF/Latch C hinder the constant cleaning in the block C1.cleaning in the block C1.

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SchematicSchematic LDE is latchLDE is latch Small box is clock driverSmall box is clock driver

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In fact…In fact… If I change the INIT of C like it saysIf I change the INIT of C like it says

output reg C = 1output reg C = 1 Synthesizer saysSynthesizer says

INFO:Xst:1304 - Contents of register <C> in INFO:Xst:1304 - Contents of register <C> in unit <C1> never changes during circuit unit <C1> never changes during circuit operation. The register is replaced by logic.operation. The register is replaced by logic.

SchematicSchematicmodule C1(output reg C = 1, input A, input B);module C1(output reg C = 1, input A, input B);

always @ (A or B)always @ (A or B)beginbegin

if(A == 1 && B == 1)if(A == 1 && B == 1)C <= 1;C <= 1;

endendendmoduleendmodule

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Parameterized ModulesParameterized Modules2:1 mux:2:1 mux:module mux2module mux2

#(parameter width = 8) // name and default value#(parameter width = 8) // name and default value

(input [width-1:0] d0, d1, (input [width-1:0] d0, d1,

input s,input s,

output [width-1:0] y);output [width-1:0] y);

assign y = s ? d1 : d0; assign y = s ? d1 : d0;

endmodule endmodule

Instance with 8-bit bus width (uses default):Instance with 8-bit bus width (uses default): mux2 mux1(d0, d1, s, out);mux2 mux1(d0, d1, s, out);

Instance with 12-bit bus width:Instance with 12-bit bus width:mux2 #(12) lowmux(d0, d1, s, out); mux2 #(12) lowmux(d0, d1, s, out);

VGA MonitorsVGA Monitors

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How Do Monitors Work?How Do Monitors Work? Origin is TV, so let’s look at thatOrigin is TV, so let’s look at that

LCDs work on different principle, but all signaling still LCDs work on different principle, but all signaling still derived from TV of 1940sderived from TV of 1940s

Relies on your brain to do two thingsRelies on your brain to do two things Integrate over spaceIntegrate over space Integrate over timeIntegrate over time

Many Still ImagesMany Still Images Video (and movies) are a series of stillsVideo (and movies) are a series of stills

If stills go fast enough your brain interprets as moving If stills go fast enough your brain interprets as moving imageryimagery50-60 Hz or more to not see flicker50-60 Hz or more to not see flicker

In fact, even single “still” image displayed repeatedly In fact, even single “still” image displayed repeatedly over timeover time

Phosphor persistence variesPhosphor persistence varies

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Cathode Ray TubeCathode Ray Tube

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From wikipedia: http://en.wikipedia.org/wiki/Cathode_ray_tube

Deflection CoilsDeflection Coils

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Simple Scanning TVSimple Scanning TV Electron beam scans acrossElectron beam scans across Turned off whenTurned off when

Scanning back to the left (horizontal retrace)Scanning back to the left (horizontal retrace) Scanning to the top (vertical retrace)Scanning to the top (vertical retrace)

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ScanningScanning TVs use TVs use interlacinginterlacing

Every other scan line is swept per fieldEvery other scan line is swept per field Two fields per frame (30Hz)Two fields per frame (30Hz) Way to make movement less disturbingWay to make movement less disturbing

Computers use Computers use progressive scanprogressive scan Whole frame refreshed at onceWhole frame refreshed at once 60Hz or more, 72Hz looks better60Hz or more, 72Hz looks better

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ColorColor Three colors of phosphorThree colors of phosphor Beams hit eachBeams hit each Black – beam offBlack – beam off White – all onWhite – all on

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Picture is a bit misleading. Mask (or aperture grill) ensures beams hit only correct color phosphor.

AsideAside Frustrated with VerilogFrustrated with Verilog See what to do to relieve stressSee what to do to relieve stress

http://science.howstuffworks.com/what-if-shoot-tv.htmhttp://science.howstuffworks.com/what-if-shoot-tv.htm

Educational tooEducational too

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What about LCD?What about LCD? We’ll talk about how they work laterWe’ll talk about how they work later They don’t scanThey don’t scan However, signaling is the same!However, signaling is the same!

For compatibilityFor compatibility

Same goes for micro-mirror projectorsSame goes for micro-mirror projectors

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VGA SignalingVGA Signaling RGB and two synchronization pulses, RGB and two synchronization pulses,

horizontal and verticalhorizontal and vertical

VGA TimingVGA Timing You supply two pulses, hsync and vsync, that You supply two pulses, hsync and vsync, that

let the monitor lock onto timinglet the monitor lock onto timing One hsync per scan lineOne hsync per scan line One vsync per frameOne vsync per frame

ContinuousContinuous Don’t stop hsyncDon’t stop hsync

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Image from dell.com

Horizontal Timing TermsHorizontal Timing Terms hsync pulsehsync pulse Back porch (left side of display)Back porch (left side of display) Active VideoActive Video

Video should be Video should be blankedblanked (not sent) at other times (not sent) at other times Front porch (right side)Front porch (right side)

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Picture not accurate for our case; just for illustration.

Video and HSYNC not on same wire

Horizontal TimingHorizontal Timing

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640 Horizontal Dots 640 Horizontal Dots Horiz. Sync Polarity NEG Horiz. Sync Polarity NEG Scanline time (A) 31.77 usScanline time (A) 31.77 usSync pulse length (B) 3.77 usSync pulse length (B) 3.77 usBack porch (C) 1.89 usBack porch (C) 1.89 usActive video (D) 25.17 us Active video (D) 25.17 us Front porch (E) 0.94 usFront porch (E) 0.94 us

Image from http://www.epanorama.net/documents/pc/vga_timing.html

This diagram shows video as a digital signal. It’s not – video is an analog level.

Vertical Timing (note ms, not us)Vertical Timing (note ms, not us)

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Vert. Sync Polarity NEGVert. Sync Polarity NEGVertical Frequency 60HzVertical Frequency 60HzTotal frame time (O) 16.68 ms Total frame time (O) 16.68 ms Sync length (P) 0.06 msSync length (P) 0.06 msBack porch (Q) 1.02 msBack porch (Q) 1.02 msActive video (R) 15.25 msActive video (R) 15.25 msFront porch (S) 0.35 msFront porch (S) 0.35 ms

Timing as PixelsTiming as Pixels Easiest to derive all timing from single-pixel Easiest to derive all timing from single-pixel

timingtiming

How “long” is a pixel?How “long” is a pixel? Active video / number of pixelsActive video / number of pixels 25.17 us / 640 = 39.32ns25.17 us / 640 = 39.32ns Conveniently close to 25 MHz – just use thatConveniently close to 25 MHz – just use that Actual VESA spec is 25.175 MHzActual VESA spec is 25.175 MHz

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StandardsStandards 640 x 480 (sometimes x 60Hz) is “VGA”640 x 480 (sometimes x 60Hz) is “VGA”

I will give you spec sheets in labI will give you spec sheets in lab

You can try for 800x600 at 60 Hz (40 MHz You can try for 800x600 at 60 Hz (40 MHz exactly) exactly) or 800x600 at 72 Hz (50 MHz exactly)or 800x600 at 72 Hz (50 MHz exactly)

Note that some standards have vsync and Note that some standards have vsync and hsync positive true, some negative true – hsync positive true, some negative true – choose correct onechoose correct one

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Color DepthColor Depth Voltage of each of RGB determines colorVoltage of each of RGB determines color 3-bit, 2-bit color here3-bit, 2-bit color here All on for whiteAll on for white

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What To Do FridayWhat To Do Friday1.1. First finish previous labFirst finish previous lab

2.2. Make Verilog module to generate Make Verilog module to generate hsync, vsync, horizontal count, vertical count, and hsync, vsync, horizontal count, vertical count, and

signal to indicate active videosignal to indicate active video

3.3. Use higher-level module to drive RGB using Use higher-level module to drive RGB using counts gated by activecounts gated by active Just do something simple; need to meet 25MHz Just do something simple; need to meet 25MHz

constraintconstraint

4.4. Later will use memory addressed by counts to Later will use memory addressed by counts to make terminalmake terminal

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What do you Need for VGA?What do you Need for VGA? Think firstThink first

Need counter(s)?Need counter(s)? Will you need a state machine?Will you need a state machine?

Sketch out a designSketch out a design Block diagramBlock diagram

Test individually in labTest individually in lab Keep in MindKeep in Mind

Verilog has all these operators (and more; see Verilog Verilog has all these operators (and more; see Verilog ref.)ref.)

==, <, >, <=, >===, <, >, <=, >=

Next week’s lab: Character Next week’s lab: Character Terminal?Terminal? No frame bufferNo frame buffer Character terminalCharacter terminal

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Screen Character Memory

BitmapMemory

VGA Driver

Timing Generator

RGB

HSync

VSync

From/ToCPU

Valid, VSync, HSync

bitmaps by rows

Future Labs PreviewFuture Labs Preview VGA timing generatorVGA timing generator Character terminal (learn memories)Character terminal (learn memories) MIPS datapathMIPS datapath Add load/storeAdd load/store Add branchingAdd branching PeripheralsPeripherals Final projectFinal project

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VGA LinksVGA Links VGA TimingVGA Timing

http://www.epanorama.net/documents/pc/vga_timing.htmlhttp://www.epanorama.net/documents/pc/vga_timing.html http://appsrv.cse.cuhk.edu.hk/~ceg3480/Tutorial7/tut7.dochttp://appsrv.cse.cuhk.edu.hk/~ceg3480/Tutorial7/tut7.doc

Code (more complex than you want)Code (more complex than you want) http://www.stanford.edu/class/ee183/index.shtmlhttp://www.stanford.edu/class/ee183/index.shtml

InterestingInteresting http://www.howstuffworks.com/tv.htmhttp://www.howstuffworks.com/tv.htm http://computer.howstuffworks.com/monitor.htmhttp://computer.howstuffworks.com/monitor.htm http://www.howstuffworks.com/lcd.htmhttp://www.howstuffworks.com/lcd.htm http://plc.cwru.edu/http://plc.cwru.edu/ Liquid Crystals by S. Chandrasekhar, Cambridge Univ. PressLiquid Crystals by S. Chandrasekhar, Cambridge Univ. Press

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Next TimeNext Time Sequential TimingSequential Timing MetastabilityMetastability Homework dueHomework due

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