1 comp541 arithmetic circuits montek singh oct 21, 2015
TRANSCRIPT
![Page 1: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/1.jpg)
1
COMP541
Arithmetic Circuits
Montek Singh
Oct 21, 2015
![Page 2: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/2.jpg)
Today’s Topics Adder circuits
ripple-carry adder (revisited)more advanced: carry-lookahead adder
Subtractionby adding the negative
Overflow
2
![Page 3: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/3.jpg)
Iterative Circuit Like a hierarchy, except functional blocks per
bit
3
![Page 4: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/4.jpg)
Adders Great example of this type of design Design 1-bit circuit, then expand Let’s look at
Half adder – 2-bit adder, no carry in Inputs are bits to be addedOutputs: result and possible carry
Full adder – includes carry in, really a 3-bit adder
We have already studied adder in Lab 3/Comp411here we look at it from a different anglemodify it to be faster
4
![Page 5: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/5.jpg)
Half Adder Produces carry out
does not handle carry in
5
![Page 6: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/6.jpg)
Full Adder Three inputs
third is carry in Two outputs
sum and carry out
6
![Page 7: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/7.jpg)
Two Half Adders (and an OR)
7
![Page 8: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/8.jpg)
Ripple-Carry Adder
Straightforward – connect full adders Carry-out to carry-in chain
Cin in case this is part of larger chain, or just ‘0’
8
32-bit ripple-carry adder
![Page 9: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/9.jpg)
Lab 3: Hierarchical 4-Bit Adder We used hierarchy in Lab 3
Design full adderUsed 4 of them to make a 4-bit adderUsed two 4-bit adders to make an 8-bit adder…
9
![Page 10: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/10.jpg)
Specifying Addition in Behavioral Verilog// 4-bit Adder: Behavioral Verilog
module adder_4_behav(A, B, C0, S, C4);input wire[3:0] A, B;input wire C0;output logic[3:0] S;output logic C4;
assign {C4, S} = A + B + C0;endmodule
10
Addition (unsigned)
Concatenation operation
![Page 11: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/11.jpg)
What’s the problem with this design?
DelayApprox how much?
Imagine a 64-bit adderLook at carry chain
11
![Page 12: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/12.jpg)
Delays (after assigning delays to gates)
Delays are generally higher for more significant bits
12
![Page 13: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/13.jpg)
Multibit Adders Several types of carry propagate adders (CPAs)
are:Ripple-carry adders (slow)Carry-lookahead adders (fast)Prefix adders (faster)
Carry-lookahead and prefix adders are faster for large adders but require more hardware.
Adder symbol (right)
A B
S
Cout Cin+N
NN
![Page 14: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/14.jpg)
Carry Lookahead Adder Note that add itself just 2 level
sum is produced with a delay of only two XOR gatescarry takes three gates, though
Idea is to separate carry from adder function then make carry fasteractually, we will make carry have a 2-gate delay total,
for all the bits of the adder!these two gates might be huge though
14
![Page 15: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/15.jpg)
Four-bit Ripple Carry
15
Adder functionseparated fromcarry
Notice adder has A, B, C inand S out, as well as G,P out.
Reference
![Page 16: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/16.jpg)
Propagate The P signal is called propagate
P = A B Means to propagate incoming carry
16
![Page 17: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/17.jpg)
Generate The G is generate
G = AB, so new carry created So it’s ORed with incoming carry
17
![Page 18: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/18.jpg)
Said Differently If A B and there’s incoming carry, carry will
be propagatedAnd S will be 0, of course
If AB, then will create carry Incoming will determine whether S is 0 or 1
18
![Page 19: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/19.jpg)
Ripple Carry Delay: 8 Gates Key observation:
G and P are produced by each adder stagewithout needing carry from the right!
need only 2 gate delays for all G’s and P’s to be generated!critical path is the carry logic at the bottom
the G’s and P’s are “off the critical path”
19
![Page 20: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/20.jpg)
20
Turn Into Two Gate Delays Refactor the logic
changed from deep (in delay) to widefor each stage, gather and squish together all the logic to
the right
![Page 21: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/21.jpg)
C1 Just Like Ripple Carry
21
![Page 22: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/22.jpg)
C2 Circuit Two Levels
22
G from before and P to pass on This checks two propagates and a carry in
![Page 23: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/23.jpg)
C3 Circuit Two Levels
23
G from before and P to pass onThis checks three propagates and a carry in
Generate from level 0 and two propagates
![Page 24: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/24.jpg)
What happens as scaled up? Can I realistically make 64-bit adder like this? Have to AND 63 propagates and Cin! Compromise
Hierarchical designMore levels of gates
use a tree of AND’sdelay grows only logarithmically
24
![Page 25: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/25.jpg)
Making 4-Bit Adder Module
Create propagate and generate signals for whole module
25
![Page 26: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/26.jpg)
Group Propagate
Make propagate of whole 4-bit block P0-3 = P3P2P1P0
26
![Page 27: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/27.jpg)
Group Generate
Indicates carry generated within this block
27
![Page 28: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/28.jpg)
Hierarchical Carry
28
4-bit adder
A B
S G P Cin
4-bit adder
A B
S G P Cin
C0Look Ahead
C8 C4
Left lookahead block is exercise for you
![Page 29: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/29.jpg)
Practical Matters FPGAs like ours have limited inputs per gate
Instead they have special circuits to make addersSo don’t expect to see same results as theory would
suggest
29
![Page 30: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/30.jpg)
Other Adder Circuits What if hierarchical lookahead too slow Other styles exist
Prefix adder (explained in text) had a tree to computer generate and propagate
Pipelined arithmetic units – multicycle but enable faster clock speed
These are for self-study
30
![Page 31: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/31.jpg)
Adder-Subtractor Need only adder and complementer for input
to subtract
Need selective complementer to make negative output back from 2’s complement
31
![Page 32: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/32.jpg)
Design of Adder/Subtractor
32
Output is 2’s complement if B > A
Inverts each bit of B if S is 1
Adds 1 to make 2’s complement
S low for add,high for subtract
![Page 33: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/33.jpg)
Overflow Two cases of overflow for addition of signed
numbersTwo large positive numbers overflow into sign bit
Not enough room for resultTwo large negative numbers added
Same – not enough bits
Carry out by itself doesn’t indicate overflow
33
![Page 34: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/34.jpg)
Overflow Examples4-bit signed numbers:
Sometimes a leftmost carry is generated without overflow: -7 + 75 + (-3)
Sometimes a leftmost carry is not generated, but overflow occurs:4 + 4
34
![Page 35: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/35.jpg)
Overflow Detection Basic condition:
if two +ve numbers are added and sum is –ve if two -ve numbers are added and sum is +ve
Can be simplified to the following check:either Cn-1 or Cn is high, but not both
35
![Page 36: 1 COMP541 Arithmetic Circuits Montek Singh Oct 21, 2015](https://reader031.vdocuments.us/reader031/viewer/2022012916/56649f495503460f94c6aadb/html5/thumbnails/36.jpg)
Summary Today
adders and subtractorsoverflow
Next class: full processor datapath
36