CMOS TIME RESPONSE

Nano107

Chapter 8

CMOS TIME RESPONSE DC analysis tells us Vout if Vin is constant

Transient analysis tells us Vout(t) if Vin(t) changes

Requires solving differential equations

Input is usually considered to be a step or ramp

From 0 to VDD or vice versa

Vin(t)

Vout

(t)C

load

Idsn

(t)

DELAY DEFINITIONS

tpdr: rising propagation delay

From input to rising output crossing VDD/2

tpdf: falling propagation delay

From input to falling output crossing VDD/2

tpd: average propagation delay

tpd = (tpdr + tpdf)/2

tr: rise time

From output crossing 0.2 VDD to 0.8 VDD

tf: fall time

From output crossing 0.8 VDD to 0.2 VDD

INVERTER DELAY CALCULATION

Solving differential equations by hand is too hard

SPICE simulator solves the equations numerically

Uses more accurate I-V models too!

But simulations take time to write, may hide insight

We will use simple equations that are inaccurate but provide insight

(V)

0.0

0.5

1.0

1.5

2.0

t(s)0.0 200p 400p 600p 800p 1n

tpdf

= 66ps tpdr

= 83psVin

Vout

Simple Case Example: Resistive Pull-Up Inverter

Transient Response

INVERTER CAPACITANCES

Vss=Vs=0VG

Field Oxide

VDDPoly Load

Output

Ci

CGB

n

CGSp CDS

n

Example: Resistive load inverter

List of Parasistic MOS Inverter Capacitances 1. Drain Junction Capacitance of driver 2. Interconnect Capacitance 3. Capacitance Associated with load 4. Load Inverter Capacitance F=Fan Out

CDS CodCi

Col

FCin

The inverter must therefore drive a capacitance CL Cod Col Ci FCin

INPUT CAPACITANCE Vss=Vs=0

VG

Field Oxide

VDDPoly Load

Output

Ci

CGB

n

CGSp CDS

n

Cin CGS CGB CGD WLoxtox

C in C L

V DD

The input capacitance Cin of the MOS inverter is the gate capacitance of the driver

Capacitance at the output of a Resistive load MOS inverter

CL Cod Col Ci FCin

RISE AND FALL TIMES

VOL to VOH

VOH to VOL

Rise (toff or tr) and Fall Time (ton or tf)

Rise time (Turn-off Time ) is approximately the time

that the output voltage of the inverter

takes to increase from

The Fall time (Turn-on -time ) is approximately the

time that the output voltage

takes to settle down from

These transient times are governed by the capacitances and resistances in the circuit and

by the currents charging and discharging them to the desired voltage levels.

Dt = C(DV)/

where < I > denotes average current

RISE TIME OF RESISTIVE PULL-UP INVERTER

I coff 1

VDD

vout

R0

VDD

dvout

1

VDD

vout2

2R

0

vDD

vDD

2R

Then,

tr CLVDDVDD /2R

2RCL t r 2RCL

In general the rise time is given by

tr = 2.3 RC

tr is essentially governed by the pull-up conductance and by the load capacitance CL

MOSFET OFF

FALL TIME OF A RESISTIVE LOAD INVERTER

Icon k VDD VT 2 2

6

VT

6VDD

VDD

2R

t f 6CLVDD

kD2

VT

VDD

VDD VT

2

3VDD

B

1

Fall Time

Fall time is affected by all 3 devices including the pull-down

The non linear behavior of the MOSFET requires piecewise linear calculation of the solution by solving the relevant differential equation with appropriate boundary conditions. Instead Shockley model uses average current and plugs it into

Dt = C(DV)/

CMOS Capacitances and delays

CMOS INVERTER INPUT AND OUTPUT CAPACITANCES

. .3 3L DS NMOS i in NMOSC C C FC

.

.

oxin n GSn GBn GDn n

ox

oxin p GSp GBp GDp p

ox

C C C C W Lt

C C C C W Lt

Input and output capacitance of a CMOS inverter

VDDGND

n

+np

Vout

Vin

+p+n +p +n

CGSn CGSp

CGBn CGBp

CDSn CDSp

But Wp~2Wn

. . . 3ox

in CMOS in p in n n

ox

C C C W Lt

Fall time

VDD

VinL=0

VDD

Rise time

CMOS FALL TIME

In CMOS the turn-off time is totally governed by the load, whereas the turn-on time is totally governed by the driver. Using Shockleys approach

DD TD

TD DD TD

02

DD oDD TD O DD TD O

2D DD0c(on)

DD TD TD

DDO

V Vk 2 dV

2V V V

3

V

kV V dV V V V

2VkI V V VVdV

resulting in

VVVVkCV

tTDDDTDDDD

DD

on

2

32

2

VDD Dt = C(DV)/Icon

CMOS RISE TIME

DD

2L

LDD TL O DD TL DD OO0

Vc(r)

O

0

2L DD

DD TL TL

DD

- k - - ) 2

- +3

k (VV V dV V V V dVI

dV

2VkV V V

V

DD T L DD

DD T L

V V V

V V

2

DD

2

L DD TL DD TL- -

3CVt

V V 2V Vkr

VinL=0

VDD

One obtains an identical equation form for toff by replacing kD by kL and VTD by VTL

Note that when VDD>>VT than ton = toff= C/kVDD If kL = kD (symmetric inverter) then ton = toff and the time response of CMOS inverter will be symmetric as well The inverter propagation delay is than

tp= (ton+toff)/2= C/kVDD

IMPORTANT SIMPLIFICATIONS

CMOS FANOUT and CMOS LOGIC GATE RESPONSE

CMOS FANOUT limited by maximum propagation delay tpmax that is allowed

tpmax= Cmax/kVDD Cmax= tpmax kVDD

If input capacitance of load inverter is Cin than

Fmax=Cmax/Cin = tpmax kVDD / Cin

2

DD

2f

D DD TD DD TD

=- -

3 Vt

V V 2Vk

C

n V

CMOS LOGIC GATE DYNAMIC RESPONSE

2

DD

2

L DD TL DD TL- -

3 Vt

V V 2V Vk

C

mr

Where nkD and mkL are the effective transconductance parameters of the NMOS path and PMOS paths. The capacitance C must include the effective Drain capacitances of NMOS and PMOS transistors

CMOS POWER DISSIPATION

Ptotal = Pdynamic + Pstatic

Dynamic power: Pdynamic = Pswitching + Pshort circuit Switching load capacitances Short-circuit current

Static power: Pstatic = (Isub + Igate + Ijunct )VDD Subthreshold leakage Gate leakage Junction leakage [Contention current (two terminal pull-ups)]

POWER IN CIRCUIT ELEMENTS

VDD DD DDP t I t V

2

2R

R R

V tP t I t R

R

0 0

212

0

C

C

V

C

dVE I t V t dt C V t dt

dt

C V t dV CV

2

C cP CV f

Energy stored at a capacitor

Power removed from a capacitor when driven by frequency f

CHARGING A CAPACITOR

When the gate output rises

Energy stored in capacitor is

But energy drawn from the supply is

Half the energy from VDD is dissipated in the pMOS transistor as heat, other half stored in capacitor

When the inverter output falls

Energy in capacitor is dumped to GND

Dissipated as heat in the nMOS transistor

212C L DD

E C V

0 0

2

0

DD

VDD DD L DD

V

L DD L DD

dVE I t V dt C V dt

dt

C V dV C V

2

switching DDP CV f

SHORT CIRCUIT CURRENT

When transistors switch, both nMOS and pMOS networks may be momentarily ON at once

Leads to a blip of short circuit current.

< 10% of dynamic power if rise/fall times are comparable for input and output

Edp=VDD (Ipeak.ton)/2+ VDD (Ipeak.toff)/2=>

Pdp= VDD Ipeak f tp

CMOS POWER DISSIPATION

STATIC POWER :

Due to Leakage: Ps VDD.ILeakage

DYNAMIC POWER DISSIPATION: Due to load capacitance Each half cycle the energy stored on the C is with f = frequency

2

c P DDCV f

Due to Direct path transition currents

Pdp= VDD Ipeak f tp

SWITCHING POWER & ACTIVITY FACTOR

C

fswi

DD(t)

VDD

Suppose the system clock frequency = f

Let fsw = af, where a = activity factor

If the signal is a clock, a = 1

If the signal switches once per cycle, a =

Dynamic power:

2

CMOS ( )DD DD peak p le kDD aIP CV V Vt f Ia