ALTO: A Personal Computer System Hardware Manual

May, 19'19

Abstract

This manual is a rcvision of the original description of the Alto: "Alto. A Personal Computer Systcm." I t includcs a complete description of the Alto 1 and Alto I1 hardwarc and of tllc standard micrococlc (I:24, I1:3).

XEROX PAL0 ALTO RESEARCH CENTER 3333 Coyotc liifl Road / Palo ~ \ l to / California 94304

Xcrox Corporation 01978, 1979 All righ ts rcscrved.

Alto Hardware Manual

Table of Contents

J~ltroduction Microprocessor Arithmetic section Constat~t Mcmory Main Mcmory M icroprocessor control Emulator Standard Itistnlction Set Intcnupts Rootstrapping klarclwarc 1)ispl;ly Controller Programming Characteristics I-lardware llisplay Controller Microcode Cursor Miscell;~ncous Pcriphcrals Kcyboard Mousc Kcysct lliablo l'rinter Parity llrror Detection Disk and Controller Disk Controller Implementation Klllcrnct l'rogramming Characteristics Htlicrnct )lardware litl~crnct M icrocodc C:ontrol RAM, ROM, and s Hcgistcrs lir\~-liclatcd 'I'asks l~roccssor 13us and A I ~ U Interface Microinstruction Bus Interface Microinstructio~~ Mcmory Banks Standard 1Lnulator Access J~~tcrprctiltion of Emulator Traps M and S Registers Itcstrictions and Caveats Nuts a~rtl llolts for the Microcoder Standasd Microcodc Convcntions Microcodc 'l'cchniqucs Which Nccd Not Be Rediscovered Rflirroinstructio~~ Sutnlnary Stir rltlilrd liescrvcd Mcniory 1,ocations St;intl;lrd Rcscrvcd SIO (S'I'AK~P) Bits St:~nil:lrtl 'I'asks S-Group Instritction Summary Allo I/Alto 11 1)iffcrcnccs Snolmary of I(now11 S~caturcs/Bugs in liclcascd Microcodc Vcrsions

1.0 INTRODUCTION

l'liis documcnt is a dcscription of thc Alto, a small pcrsonal computing system originally dcsigncd at PARC:. Ily "pcrsonal computcr" we mean a non-sharcd system containing sufficient processing power, storagc, and input-output capability to satisfy thc computational needs of a single user.

A basic Alto systcm is: * An 875-linc tclcvision monitor, with a viewing area of about 8%" x l l " , oricntcd with the long

tubc dimension vertical. l'hc controller providcs a 606 by 808 point display which is rcfrcshed from main mcrnory at 60 fields (30 frames) per second. It has prograrnmablc polarity, a low resolution modc which conserves memory space, and a 16 by 16 cursor whose position and contcnt arc undcr program control.

* An unencodcd 64-key keyboard.

* A mousc (pointing device) and five-finger keyset.

* Up to two Iliablo Modcl 31 disk drives or a Modcl 44 disk drive. * An intcrfacc to the Ethernet, a 3 Mbps local nctwork that can connect up to 256 Altos and other

computers scparatcd by as much as a mile. Most Ethcrncts are interconncctcd by gatcways and lcascd lincs to form a nationwide internet.

* A microprogrammed processor which controls the disk, display and Bthcrnct, and emulates an instruction sct. 'The standard instruction sct for which emulation microcodc is supplied in the niicroinstruclion ROM is dcscribcd in section 3.0.

* 64K 16 bit words of 850ns error corrected semiconductor memory, expandable to 256K. * 1K microinstruction RAM that can be read and written with spccial microcodc to cxtcnd the

standard instsuction set or to emulate a diffcrent instruction set or to drivc spccial 1 1 0 devices. * 'I'lic processor, disk, and their power supplics arc packagcd in a small cabinet. l h c othcr 110

dcviccs may be a few fcct away, and arc pleasingly packagcd for dcsk top use.

Sotnc options:

* An cxpandcd ~nicroinstmction memory consisting of either 2K of 171<OM or 3K of RAM.

* A Diablo Hy'l'ype printer.

* A Vcrsalcc I'rintcr/Plottcr.

* A controllcr for CalComp Trident disk drives.

* A controllcr for MDS and Kennedy tape drives.

* An Orbit, thc controller for a vast array of laser-scanncd printcrs.

* Communications controllcrs for BBN-1822, SIILC, Bisync and Async.

'I'hc rctnaioing scctions of this documcnt will discuss the hardware and microcode of thc standard configuration Alto. At prcscnt, two slightly diffcrent vcrsions of thc Alto cxist: thc Alto I and the Alto 11. Most passagcs of this documcnt pertain to both machines; thosc that apply to one only are clearly markcd.

'I'his d o c ~ ~ n ~ c ~ i t docs not dcal with thc numerous non-standard pcriphcral dcvices that have becn intcrfaccd to thc Alto. Non-standard interfaces and their dcsigners arc tabulated in an appendix.

Alto ~J:irtlwnrc M;lnual Section 1: Introduction

1. I Guide to lliis Docutnent

This documcnt is a comprclicnsive description of thc Alto. Information about hardwarc, microcode, and CPU programming is spriuklcd throughout. Programmers interested primarily in the CPU cmulator should conccntratc on the scctions labclcd with an astcrisk in the table of contents.

1.2 People

'Ihe Alto was originally dcsigncd by Charlcs P. Thacker and Edward M. McCreight and was based on rcquircmcnts and ideas contributcd by Alan Kay, Butler Idampson and other members of PARC'S C o ~ n p i ~ t ~ r Scicnccs Idaboratory and Systcms Sciences 12aboratory. 13ob Mctcalfc and David Boggs dcsigned tlie Ethcmct; Scvcro Ornstein and Bob Sproull dcsigncd thc Orbit; Rogcr Ihtcs designed the 'I'ridcnt controllcr; David 13oggs dcsigncd the tape controllcr; Tat Lam, nick Lyon, Rd McCreight arid 1)an Swincliart dcsigncd the Audio Board; Larry Stcwart designed the BBN-1822 interface.

7'hc niacliinc was re-enginccrcd as the Alto I1 for ITG/SDD to a specification developed by John Ellcnby. 'l'hc cnginccring and production wcre carricd out by E?OD Spccial Programs Group, managed by Doug Stcwart and coordinated on bchalf of PAKC and snu by John Ellenby. 'Ihc members of l i O ~ / s p a who workcd on tlic projcct arc Doug Stewart, Ron Cude, Ron Freeman, Jim Leung, 'l'om Logan, Bob Nishi~nura, Abbcy Silvcrstone, Nathan 'l'obol, and Ed Wakida.

l'his hardware manual lias had a long history of modification and cxtcnsion and lias bcncfited from cndlcss toil by numerous individuals. The original manual was writtcn by Chuck 'I'hacker and Ed McCrcight. 'I'lic last major rcvision was edited by Bob Sproull and Diana Merry. l'hc prcscnt documcnt is tlie rcsponsibility of Ed McCrcight, David Boggs, and Ed 'I'aft.

1.3 Cott verttions attd Notation

Numbcrs in this documcnt are dccimal unless followed by "13"; thus 10 = 1213.

13its in rcgistcrs arc numbcrcd from thc most significant bit (0) toward the least significant bit. Ficlds within rcgistcrs arc givcn by following tlic registcr name with a pair of nutnbcrs in brackets: II<[~-b] dcscribcs tlic b-a+ 1 bit ficld of tlie II< rcgistcr beginning with bit a and ending with bit 1) inclusive. l ~ [ a l is short 1i)r II<[~-a].

'I'lic symbol "+" is uscd to mcan "is rcplaccd by." l'hus 1a[4-51 6 2 rncans that thc 2-bit ficld of I I ~ including bits 4 and 5 is rcplaccd by thc bit values 1 and 0 rcspcctivcly. 'l'hc symbol " =" is used as an cqi~ality tcst.

Mcmory is by convention divided into 256-word "pagcs." Page n thus contains addrcsses 256*n to 256*n+255 inclusive. Thc notation "rv(adr)" is uscd, as in 13CPId, to denote "the contcnts of the memory location with atldrcss adr."

Alto )J;lrdw;~re Manual

2.0 MICROPROCESSOR

Sectio~i 2: Microprocessor

'I'l~is scction dcscribcs the Alto microprocessor structure. If your programming nccds on thc Alto do not cxtcnd to writing ncw microcodc, this section is bcst left untacklcd. If you d o nccd to decipher what follows, it may bc lielpful to havc a listing of the "standard" Alto microcode at your side.

'l'lic rnicroproccssor is shown schcniatically in Figures 1 and 2. A principal dcsign goal in this systcm was to achicvc thc simplest structiirc adcquatc for thc requircd tasks. As a rcsult, thc central portion of thc proccssor contains vcry littlc application-spccific logic, and no spccializcd dab paths. 'I'hc entire systcm is synchronous, with a clock interval of approximately 170 ascc. All microinstructions rcquire one cyclc for thcir cxccution.

A sccond design goal was to minimize the amount of hardware in the 110 controllers. l'llis is achicved by doing most of tlic processing associated with 110 transfers with microprograms. To allow dcviccs to procccd in parallcl with each othcr and with CPU activity, a control structure was devised which allows t11c tnicroprocessor to be sharcd among up to 16 fixed priority tasks. Switching among tasks rcquires vcry littlc ovcrlicad, and occurs typically cvery few microseconds.

2.1 Ai-ithrne tic Section

l'hc arithmetic scction of thc proccssor consists of two 32-word by 16-bit rcgister files 11 and S, and five rcgistcrs, 'r, L. M, MAR, and 111. Thc registers arc connected to thc mcmory and to an AI,U with a 16-bit parallcl bi~s. For historical rcasons, thc S and M registers arc viewcd as part of tllc microinstruction RAM and arc dcscribcd in scction 8.

'I'hc AI,U is a ~ ~ 7 4 1 8 1 typc, restrictcd so that it can do only 16 arithmetic and logical functions. Thc ALU oi~lpilt feeds thc L., M, and MAR rcgistcrs. 'I' may also be loaded fsom thc AI,U output undcr certain contlitions. 1, is conncctcd to a shiftcr capable of left and right shifts by one placc, and cyclcs of 8. It has a ~iiodc in which it docs tlic peculiar 17-bit shifts of the standard instruction sct, and a tnodc which allows doublc-lcngth shifts to bc done.

'I'hc rlt rcgistcr is uscd by tlic cmulator to hold the currcnt cmulatcd instruction -- scc scction 3.5.

Attaclicd to thc bus is a 256-word read only mcmory (ROM) which holds arbitrary 16-bit constants.

'l'hc ficlds of thc 32-bit microinstruction are:

I:lI~Idt> NAME MEANING

lt Rcgistcr Sclcct AL,U Function nits Data Source P'unction 1 1:unction 2 1,oad 'r 1,oad I, & M Next microinstruction addrcss (subject to modifien)

Whcn microprogramining the Alto, it is important to understand whcrc t l ~ c macliinc's statc residcs and how it changcs. At t11c beginning of a microinstruction cyclc, thc various rcgistcrs (principally 'r, L,, M, and I I ~ , bi~ t also various bits of statc such as ~ i . u c o ) contain valucs that remain unchanged tliroughout cxcciltiorl of tlic microinstruction. lluring this timc, thc various non-statc-~'ctnini~ig data pi~tlls and clcmcnts, such as the bus, ALU, and shiftcr, co111pi1tc results bascd cntircly on thc initial valucs of thcsc

Figure 1 - - Processor Data Paths

3 SBANK

5 RSEL Monitor Transceivc

I Drive I

& I I I

HSEL ~ : : ~ ~ : : ~ : : : ~ : : : ~ ~ ~ ~ ~ ALUF BS F1 F2 T L - N E X T J

Ethernet Control

R

Display Control

RSEL[O-21 > A I I

- RSEL[3-41 -* 5

I M

IR[l-21 P

. 32x 16 32x 16 RsEL -& Constant Disk

* I x

IR[3-41 - 3 ROM

BS -4 256 x 16 Control

?

A

v Y Processor \I V \I V ,

$/ Bus I \ 16

M P X

- LOAD T

J/

L v J/

T I I I I

32 ,'

v ALU Bus

ALUT[O-31 -+ SKIP +

'7 . > ;

M - I

v LOAD L > L MAR

Memory ,, 16 Address

Shifter BUS > - v

Decode

A B

ALU

F

Main Memory

4x64Kx16 + 7

Error Corrected Dynamic MOS

& Control 1'

Alto I-lardwarc Manual Section 2: Microprocessor

rcgistcrs. I-Iowcvcr, the rcgistcrs thctnsclves do not change.

At thc cnd of thc cyclc, if the microinstnlction spccifics that onc or morc rcgistcrs bc loadcd, thcy are loadcd instantancously and simultancously with thc newly-computed valucs. 'I'hcsc thcn scrvc as thc initial rcgistcr valucs for thc ncxt microinstniction. As a rcsult, it is possible (and in fact vcry common) to both rcnd and load a registcr during thc samc microinstruction. 'l'hc R rcgistcrs bchavc similarly cxccpt that it is not possiblc to both rcad and load an R rcgistcr during thc samc microinstruction.

l'hc n sclcct ficld spccifics one of the 32 R cells to bc loadcd or rcad undcr control of the bus source ficld, or, in conjunction with the bus sourcc field, onc of the 256 locations to bc rcad from the constant ROM. l 'hc I< ficld is also uscd to address rcgistcrs in s -- scc scction 8.

The low ordcr two bits of thc R addrcss (but not thc constant KOM addrcss) may be taken from ficlds in IR undcr control of thc functions. This allows the emulator to address its ccntral rcgistcrs casily.

'I'hc AI,UI: ficld controls the s~74181 ALU. This dcvice can do a total of 48 arithmetic and logical opcrations, lr~ost of which arc rclativcly usclcss. The 4-bit ficld is mapped by a I>I<OM into the 16 most uscful f~inctions.

A1 .UI: T T:UNCTION S3 S2 S1 SO M C OPERATION

0 * BUS 1 1 1 1 1 0 1 'I- 1 0 1 0 1 0 2 * I3US OR T 1 1 1 0 1 0 3 nus AND T 1 0 1 1 1 0 4 I3US X01< T 0 1 1 0 1 0 5 * I3US + 1 0 0 0 0 0 0 6 * 1iUS - 1 1 1 1 1 0 1 7 BUS + T 1 0 0 1 0 1 101% l3US - 'I- 0 1 1 0 0 0 1 I R I3US - 1' - 1 0 1 1 0 0 1 J 2R * RUS + '1' + 1 1 0 0 1 0 0 13R * INS + SKIP 0 0 0 0 0 SKIP 141) * nus . .r. (AND) 1 0 1 1 1 0 1 SR 13US AND N W 1 ' 0 1 1 1 1 0 1613- 1713 UNIII<f~INF<D

A n A + B AD A XOR R A PI,US 1 A MINUS 1 A PI,US B A MINUS n A M ~ N U S n MINUS 1 A PI,US 13 PI.US 1 A PI'US 1 AB A & NOT n

If 1' is londcd in an instl-uction containing an ALUF with a * in thc column, it will bc loadcd from the A1,U output rathcr tllnn from BUS.

~ 3 3 0 sclccts thc function; M selects logical or arithmctic mode by controlling carry propagation; c is thc carry into thc l s n . 'I'hc carry output is forccd to zero during logical opcrations (M=O). HUS is the A i11pl11 lo ~ I I C AI,U; '1' is llic R input.

I3US SOURCIB

The bus data sourcc (1s) ficld spccifics onc of 8 data sourccs for thc bus:

RS NAMI3 SOURCE

0 + ~ N a r n c Read R 1 ~ N a i n c t 1.oad it from shiftcr output (scc bclow) 2 (Nonc) Rnablcs no sourcc to thc BUS, lcaving i t all olics 3 'I'ask-spcci fic l'crfonns diffcrcnt filnctions in diffcrcnt tasks.

Alto Hartlwarc Mi~nual Scction 2: Microproccssor

4 ?'ask-specific Pcrfonns different functions in diffcrcnt tasks. 5 +MI) Mcmory data 6 +MOUSE ~ ~ ~ [ 1 2 - 1 5 ] + MOUSl4; ~ ~ ~ [ 0 - 1 3 ] + -1 7 +IIISP IK[~-151, possibly sign extcndcd (scc scction 3.5)

1iNamc6 is not logically a sourcc, but bccausc it is gated to thc bus during both rcading and writing, it is includcd in thc sourcc specifiers. 1,oading K forces the nus to 0 so that an Arm fiinction of 0 and T may bc exccutcd simultaneously.

'l'hc bus has thc propcrty that if more than one sourcc is gatcd to it during a singlc microinstruction, it computcs tllc AND of thc sourcc values. ?'his is true regardless of thc mcans by which thc sources are cnablcd (ns, 1:1, or r42).

This bus sourcc decoding is not pcrfomcd if F1=7 or F2=7. 'lbcsc functions usc thc ns ficld to provide part of thc addrcss to thc constant ROM.

'I'hc two function fields spccify the address modifiers, register load signals (othcr than thosc for R, s. L, M and 'I.), and other spccial conditions rcquired in the proccssor. The first cight conditions spccificd by cach ficld (cxccpt BI,OCK) arc interprctcd idcntically by all tasks, but thc intcrprctation of the sccond eight dcpcnds on thc activc task. Thc task-independent functions arc givcn bclow; thc task-spccific functions arc includcd with the task dcscriptions.

I:] NAME MEANING 0 --- No Activity

1,oad MAR from AI,U output; start main lncmory refcrencc (scc section 2.3).

2 TASK Switch tasks if highcr priority wakeup is pcnding (scc section 2.4). 3 11r.o~~ Ilisable thc current task until re-cnablcd by a hardware-gcncratcd

condition. Notc: this f~~nction is rcscrvcd by convention only; it is rlol donc by the rnicroproccssor.

4 +I, L,SI1 1 SlI1I~l'ER ou'rlw'r will bc I, shiftcd lcft onc placc* 5 +I, RSlI 1 SIIII~I'EK OUI'PUl' will bc I, shifted right onc place* 6 +I , ICY 8 SIIII;~ER OUIPUI' will be I, rotatcd left 8 places* 7 +CONSTANT Put on thc bus thc constant froin the constant 1t0M location addrcsscd by

I<sl~I,I~C'I'.l3s

*Modified by 1 1 ~ s (DO Novcl shifts) function, and MAGIC function. I, I S t l 1 and L KSII 1 ordinarily shift a zero into thc vacated bit position.

1 2 NAMI:. MI~ANI'NG 0 --- No Activity 1 nus=o N R X T ~ N E X ~ OR (if (nus-o) then 1 elsc 0). 2 SlI<O NI:Xr+NEXT Oli (if ( S I I I ~ T I ~ R OU?'PUI'<~) t h ~ n 1 C ~ S C O).* 3 SII=O NEXT+NI'X'I' OK (if (SI I I I~I ' I~ I< O U ~ ' P U ~ = ~ ) thcn 1 clsc O).* 4 IIUS NliXl'+NI:XT OR ~ ~ ~ [ 6 - 1 5 ]

Alto I lartlwarc Manual

5 ALUCY

Section 2: Microprocessor 6

Nlixl'+-NEXT OR ALuCO. ALUCO is the carry produccd by the Al,U during the most recent microinstruction that loaded L. It is not the carry produced during exccution of the nlicroinstruction that contains the ALUCY function.

6 MD+ Deliver HUS data to memory (see section 2.3) 7 CONST TAN^' Same as F1=7

*Note that the value of the SIIIFI'ER OUI'PUT is determined by the valuc of I, as thc microinstruction begiris execution and the shifter fi~nction (I, LSlI I , I, RSI-I 1, or I, I,CY 8) specified during the currerzl microinstruction (if no shifter filnction is specified, the shiftcr output is equal to L,).

The constant mcmory is a 256 x 16 PROM that holds arbitrary constants. The constant memory is gated to the bus by F I = ~ , 1:2=7, or 1)S>4. The constant memory is addressed by the (8 bit) concatenation of lisrtri:cr and 13s. 'I'lic intent in enabling constants with 1 8 2 4 is to provide a masking facility, particularly for the +MOUSE and +I)ISP bus sources. This works because the processor bus ~ ~ 1 1 s if more than one source is gated to it. Up to 32 such mask constants can be provided for each of the four bus sources 2 4 .

Alro I: Note that it is not possible to use a constant other than -1 with the +MI) bits source, because mctnory parity is calculated on the bus, and a parity error will result if bits arc masked off in a word fetched from manory.

2.3 Mairt Mentoiy

Main mcmory references arc handled differently on Alto I and Alto TI. It is, however, possiblc to write most microcode so that it will operate correctly on both machines.

Mclnory is addressed by a 16-bit number that rcfcrs to a 16-bit word in the mcmory. Addresses 0 tl~rougli 17677711 arc truc memory storage locations; addresses 177000n through 177777~ are used to contl'ol 110 dcviccs that arc attaclicd to the Alto memory bus. Some operations on memory are pcrforl~~cd on "double-words." 'I'he double-wol-d beginning at location adr (adr is even) is a 32-bit quantity equivalent to the 16-bit contcnts of location adr, togctlicr with the 16-hit contents of location adr-kl. (Iloublc-word references operate corrcctly only on truc mcmory locations, not on 110 device locations.)

h41:hlOl<Y IiEI:13KI~NC13S

Alro 1 (111d Alto I I : A mcmory rcfcrcncc is initiated by executing l:l=I, MAli+-. 'I'hc res~~lts of a lacad opcsation a1.c dclivcrctl sonlcw1i;rt Iatcr onto the bus with 11S=5, ~ M I I . A storc into the addsesscd memory location is achicved with 1;2.=6, MD+. 'I'lic microprogram partially controls memory timing, and must obscrvc certain rules to insure correct operation.

a) A minimum of one microinstruction must intervene between the initiation of a memory r c f ~ r ~ n c ~ and an MI)+ or +MI,.

b) On both Alto I and Alto IT, memory cyclcs last a total of 5 micro-cycles, although double- wort1 opesations may cxtcncl the mcmory cycle to take a total of 6 micro-cycles. Although the exact clctails of mcmory timing differ o n Alto 1 and Alto IT, both macllincs s1lnr.c the property that the processor will suspend exccution ol' nlicroinsl~'i~ctio~ls if the mcnlory

Section 2: Microprocessor

interface cannot process the function (MAR+, MD+ or +MD) specified; processing will resumc as soon as the intcrface is free. It is permissible to "abandon" a memory reference that has already bee11 startcd simply by not rcfercncing MD within the first 5 cycles, or by starting a new memory rcference with MAR+.

c) l'he memory chccks parity on all fetches, unless the cyclc is a rcfresh cycle or the address is bctwecn 17700013 and 177777s inclusive, in which case an 110 device is being rcferenccd. Parity crrors rcsillt in activation of a high-priority task (task number 1 5 ~ ) whosc purpose is to deal with the error (see section 5.5). The Alto I1 chccks mcmory parity on store as well as fetch cycles.

d) If Irsrn.Ecr = 3713 during the instruction which starts the memory, a refresh cycle is assumed and all mcmory cards are activated. This is uscd by the rcfresh task.

c) MAR+ cannot bc invoked in the same instruction as +MD of a previous access.

In the discussion that follows, we assume that a mcmory reference has been started with MAR+, and wc designate this instruction (tnicro)cycle 1. Examples of proper sequences are given bclow.

f ) 1)uring cycle 5, if ~;2=6, MD+, a store of bus data into the word addrcsscd by MAR will occur. l'he MI,+ may not be issued later than cycle 5. (Note: So~nc Alto 1's have bcen modificd to allow a "double-word store." On these machines, it is permissiblc to issue two MD+ instructions in a row, thc first coming in cycle 5, and the sccond in cyclc 6. If M ~ l l is loadcd with an even address adr, the two words will be stored at adr and a d r + l rcspcctivcly.)

g) Tluring cycle 5 of a reference, if 1w=5, +MD, the reference is a fetch of the word addressed by MAR. During cycle 6, if ns=5, +MD, the odd word of the doublcword addrcsscd by M A I ~ is dclivcrcd. If Mn is rcfcrcnced during cyclc 6, it also must have bcen rcfercnccd (by either +-MI) or MD+) during cycle 5.

f) 1)uring cyclc 4, if 1:2=6, MD+, a store of bus data into the word addresscd by MAR will occur. 'I'hc MI)+- may not bc issued later than cycle 4. Alto 11's allow a "double-word store:" it is pcrmissiblc to issue two MD+ instructions in a row, the first coming in cyclc 3, and the sccond in cyclc 4. If M A R is loaded with an addrcss ads, the two words will be stored at ads and (ads xoli 1) respectively.

g) Iluring cyclc 5, if ns=5, +MD, the reference is a fetch of the word addrcsscd by MAR. Tluring cyclc 6, if ns=5, +MI,, the othcr word of thc doublcword addrcsscd by MAR is dclivcrcd. Again, if MAR is loadcd with address adr, the two words fctcl~cd will be from location adr and (adr XOR 1) respectively.

h) 13ccausc the Alto I1 latches mcmory contents, it is possible to execute + M D anytime after cyclc 5 of a rcfcrcncc and obtain the results of the read opcration.

13ccausc thc description above is a bit terse, we shall givc scvcral cxamplcs for Alto I opcration, for Alto 11 opcration, and for coding schemes that will work properly on both kinds of Altos. In the coding cxamplcs, l i l iQu~l i l ; I~ stands for somc microinstruction (you supply it) that must appear in the sequence; SUSPI:NI) stancls for a microinstn~ction which if omittcd will cause cxccution to suspend for one cyclc bccausc tlic lnclnory intcrface is not ready; O P ' ~ I ~ N A I . stands for a micsoinstruction which ]nay be oniittcd wilhout pcnalty. 'I'hc notation A N Y will be uscd to stand for an arbitrary 16-bit addrcss; EVEN will stand for nn cvcn 16-bit addrcss. A11 of thcse cxamplcs apply to cxtcndcd mcmory rcfcrcnccs also (dcscrihcd in the next section); simply substitute XMAR for MAR.

Scctiot~ 2: Microprocessor

Sirnplc fctch:

Alto I Alto I1

MAR+ ANY; MAR+ ANY; IiI~QUIliED; REQUl REI); SIJSPITNI); SUSPEND; SUSPIINI); SUSPEND; W ~ C S C C V ~ S + M D ; wherccvcr+MD;

Simplc storc:

Alto I Alto I1 MARcANY; MARcANY; IiIlQUIRF<D; REQUIKI:D; SUSI'1:NL); OPTIONAI,; SUSP13NI); MD+ whatever; MI,+ whatever;

Simple s torc , fol lowed immedia te ly b y another m c m o r y cycle:

Alto I Alto I1 Alto I1

MAR+ ANY; MAReANY; MARcANY; I<IIQUIRI'D; REQUIRED; REQUlIilD; SUSPllNI); KEQUII<ED; MD+ whatcvcr; SuSl'IrNI>; MI)+ whatever; SUSPEND; MI>+ whatever; SUSPEND; SUSPEND; MAKtANY; MAR+ ANY; MARcANY;

I>oublc-word fctch:

Alto I Alto I1

MAIi+EVI:N; MAR+ ANY; I~l<QUIIiL~I~; REQUIRED; SLJSl'1:NI); SUSPEND; SUSI'ICND; SUSPl {NI); w h c r c c v c r ~ ~ ~ ~ ; W ~ C ~ C C V C ~ ~ M D ; W ~ I C ~ C C V C ~ + M I ~ ; W ~ C ~ C C V C ~ + M I ) ;

Alto I Alto I1

MAli+-13VI~N; MAR+ ANY; I~I~QUl1~1~1>; REQUIRED; SIJSI'I:NI>; SUSI'l<NI>; SlJSI'IINl>; M U + whatcvcr ; MI,+ whntcver; W~CSCCVCS+MD; W ~ ~ C ~ C C V C ~ + M D ;

l>oublc-word storc (only on modified Alto Is):

Alto I Alto I1

MAR+ ANY; RI:QUIRBI); MI,+ whatcvcr ;

Alto Hardw;lrc Manual

SUSPEND; Mll+whatcver; M I ~ + W ~ ~ ~ C V C ~ ;

Section 2: Microprocessor

MDcwhatcvcr;

l'lic Alto I1 mcmory buffering pcrmits a doublc-word "cxchange":

M A R + ANY; l<I?QUIREI~; ~ l ) + n ~ ~ C O l i t ~ n t ~ l ; address = adr M l N - n ~ ~ C o l i t ~ n t ~ 2 ; address = adr XOR 1 L+MD; address = adr T ~ M L ) ; address = adr XOR 1 oIdcontcntsl+~, LcT; oldcontcnts2+1,;

Microcode which uses thc lncmory timings below will work on citlier vintage of Alto:

Si~nplc fctch: (as Alto I).

Simplc storc: (as Alto 11). <<<<< Nola Belle

1)oublc-word fctch: (as Alto I).

Iloublc-word storc/fctch: (as Alto 11).

Otlicrs arc not possible.

Main tncmory on Alto 11s can bc optionally cxpandcd to up to 2 5 6 ~ words in 6 4 ~ banks. Each task has associatccl with it four extra bank Oils which are presented to tlic mcmory along with tlic 16 bit addresses gcncratcd by tlic task's microcode. Norrr~crl rnenzory references arc rnicrocodcd in tlic usual way and use two of tllc bank bits to specify thc task's norttzal bank. I!'x~ended tncnzory refiret~ces arc microcodcd slightly diffcrcutly and use thc two othcr bank bits to specify tlic task's allertin~e barlk. 'I'hus a task can rcfcrcncc 6 4 ~ vcry casily, anotlicr 6 4 ~ with a little difficulty, and thc othcr two 6 4 ~ banks only aftcr loading its bank rcgistcrs appropriately.

1'0 signal that a mcmory rcfcrcncc should go to tlic altcrnatc bank, thc ~nicroinstruction which loads M A R must also contain 1:2=6 (MI)+). The micronsscmblcr will gcncratc tliis conbination of filnctions for a clausc wliosc left hand sidc is XMAR (LC., X M A R + address will gcncralc an instnrction with 1:l-1 and 1<2=6).

'I'lic bank rcgistcrs appcar as 16 words in thc 110 arca which can bc rcad and written. 1,ocation (177740~ + N) is tlic bank rcgistcr location for task N. 13ooting tlic Alto clcars tlic rcgistcrs to zcros making all rcfcrcnccs for all tasks go to batik zcro, thus making tlic macliinc opcrntc as a standard Alto without the cxtcndcd mcmory option. Within a bank register, tlic layout is as follows:

HI<[O- 1 I] undcfincd 1,1<[12-131 normal rcfcrcncc bank numbcr 1~[14-151 cxtcndcd rcfcrc~~cc bank numbcr

'I'lic higlicst 512 locations in cach bank arc not mappcd by thc bank rcgistcrs and always rcfcr to tlic 110 arca. 'I'hat tiicans that location 1777401% is thc emulator's bank rcgistcr ~cgardlcss of what thc rcfcrcncing task's bank rcgistcr contains and rcgardlcss of whctllcr it is rcfcrcnccd with a tior~iial or an cxtcndcd mcmory rcfcrcncc.

No changes arc ncccssary in ordcr to rill1 tlic display, disk, or F.Lhcrnct in diffcrcnt banks. l'hc casicst and lcast confirsing way to tlo this is to load thc bank rcgislcrs for all conccrncd tasks (c.g. r)vr, 1 ~ 1 1 ' and D W ' ~ for Lhc display, or KSI:c and KWII for thc disk) with solric ollicr b a ~ ~ k I I L I I I I ~ C I . . 'l'llc~i tlic dcvicc is

Alto Ilardwi~rc M i ~ n l ~ i ~ l Section 2: Microproccssor

controlled by tlic rclevant words of page 1 in its bank.

Programs which usc the extcndcd memory must first initialize it to have corrcct parity. This involves disabling parity intcrrupts, storing something in cvcry word, flushing any parity intcrrupts tliat rcsult, and tlicn rccnabling parity interrupts. ?'he standard bootstrap loaders initialize bank zero only.

All Alto 11s manufdcti~rcd starting with tlic 7th build have tlic cxtcndcd merndry option but arc normally sliippcd with nicmory chips for bank zero only. Somc earlier Alto 11s havc bccn modificd in thc ficld. Machincs with tlic cxtendcd mcmory option liavc enginccring nunlbcr 3 -- sec the description of the Vl;l<S instruction.

2.4 Microprocessor Control

Control of thc Alto microprocessor is shared among 16 "tasks" arranged in a priority order. 'Hie tasks arc nulnbcrcd 0 to 15: 0 is thc lowcst priority task and 15 is the highest. The lowcst priority task is the cmulator task which fctclics instnlctions and cxecutes them.

'I'lic only statc savcd for cacli task is a "micro program counter," MPC. 'I'he ciirrcnt task number, saved in thc currcnt task rcgistcr, addrcsscs a 16 by 12 Ml'C RAM. l 'hc rcsult is an Ml'C for the currcnt Lask; it is usccl to addrcss a 1~ by 32-bit scad-only n~icroinstruction rncmory (MI ROMO) or a 1K by 32-bit writcablc microinstruction memory (MI RAMO), dcscribcd in section 8. An optional feature of Alto 11s cxtcnds the MI ROM to 2K or the liAM to 3K -- see section 8.

I3RANC:I IING

'I'hc micropsoccssor offers a liniitcd branching capability which, although somcwhat cumbcrsome, lias psovcn adcquatc for cliorcs undertaken by Alto microcode. 'Ibe basic idea is tliat special microprocessor ful~ctions may modify the ~ 1 : x . r field, and conscqucntly altcr tlic flow of control. Modification is :~ccomplislicd by olcing various bits into thc NEXT ficld.

Addrcss modification is complicated slightly because tlic Alto prc-fetches one ~nicroinstruction ahead. Conscclucntly, n bt.cz11ch coridi[ion rnod~j?es the NEXT field of the rr~icroiris~ruclioi~ fi)llowi/rg fire one irt ~vllicli the conciirion rest is placed This propcrty is bcst illustrated wit11 an cxamplc:

MI location MI

100n r;2 = 2 (SII<O), NEXT= 1 0 1 ~ lOln ..., NI:.x'~ = 10213 10211 ... 10313 ...

Whcn tlic inqtruction at location lOOn is being cxecutcd, the iustnlction at location lOln lias alrcady bcen fctclicd. 'I'l~crcforc, thc srl<O tcst rnodifics thc N r X l ficld of thc on-dcck instruction, tlic onc at 10111. 'I'hus tlic two possiblc cxccution scqucnccs arc: (1) if 1 ~ 2 0 on cntcring Llic codc abovc: 1001$ 10111, 102n; (2) if 1.<O on cntcring tlic codc: 10013, 101n, 10313.

0 1 1 l y onc of tlic 16 tasks is executing microinst~z~ctions at any onc time. Oncc a task bcgit~s cxccution, it co~itillucs to cxccutc until it invokcs a task switcli function tliat cnablcs switcliit!g to anotlicr task. A task is considcrcd cligiblc for cxccution if its hardware-gcncratcd "wakcup signal" is '~sscrtcd (tlicsc signals are not acccssiblc to tlic microprogram). 'l'hc wi~kcltp signals cntcr a priority cncodcr that calculates tlic numbcr of thc liiglicst-priority cligiblc task. Whcn a runnil~g task invokes a task switcl~, co~:lrol will

Instruction

P ZER I E o =R El T

Figure 2 - - Processor Control

L

E N c 0 D E

y R

4

C U R R A

'E N K T

* A

Address Modification

Logic

CHAM Address I L

-

I

1 '

4

I

4

Next Microinstruction Address Bus

MPX

. \I/ I

MPC RAM 16x12

2 /

v D E C 0 D

>

10

I I . 10

+

Address

Control

RAM

1K x 32

or 3K x 32

Data Out

'

Address

Control

ROM

1Kx32

or 2K x 32

Data Out

22

" v MIR

Alto I-Iardw;lrc Manual Section 2: Microprocessor 11

switch to another task only if a highcr priority task has a wakcup signal held true, or if the currcnt task no longer has a wakcup signal true. In the latter case, control goes to a lower priority tiisk. 'Ihc lowest priority task is the CPU emulator, which is always requesting wakeup.

If the processor executes the TASK function (1;1=2) during an instruction, the current task register is loaded (at tlic cnd of the instruction) with the number of the highest priority task currently requesting a wakcup. Ih i s causes the next instruction to be fetched from the ROM location specified by thc saved task's MPC. One additional instsuction is cxccuted by thc currcnt task before the switch bcco~nes effective. 'l'llis instruction may execute task-specific functions, but it musl do r l o NI;X'T' address ~~iodificniion, since any such modification would affect the new task. Thc situation for two streams of instructions A-1: and J-M in two diffcrcnt tasks is shown bclow:

Instruction Instruction Address stored in being executed being fetched MPC at end of cycle

A B C n c D c1 D E I> J K J~ K L K~ L M I, E F I:, F G

l~nstruction C allows task switching. New task's MPC = J. 2~nstri~ction J docs a11 operation which removes its task's wakcup request. 31nstruction K allows task switching, and the original task is now higlicst priority.

'I'hc III,OCK fiinction (1:1=3) is used, by convention, to signal a hardware device associated with the currently running task to remove its wakcup signal. ' r l~is fiinction is 1101 accomplished by the Alto n~icroproccssor, but rather by the individual device interfiiccs.

Task switches must occur only at times when the current task has no statc in any register (except R registers dcdicatcd to the task) and has no lnain memory operation in progress, since there is no provision in the hardware for saving this infornmation. 'I'hat is, all statc importnnt to the task ~rlust havc been stored in safe places by the end of the microinstruction after the one containing the TASK function. It is not legal to place TASK functions in two consecutive microinstrilctions.

'I'hc only way in which the microprogram can affcct the task structurc is to request a task switch. In l)articular, it cannot affect the MI'CS of tasks other than itself. 'l'his presents an initialization problem which is solvccl by having each task start at the location which is its task numbcr (thus the crnulator task finds its first instruction to cxcctltc at MI'C--0). 'I'ask nu~nbcrs arc written into the MI'C R A M during a reset cycle, whicli 111;ly be initiated masiunlly or by a CI'U instruction (see SIO instruction in scction 3.3). 'I'asks ordinarily begin cxccution in KOMO. In order to start tasks in tllc RAM, thcrc is a mccll;~aism for modifying the iuilial MPC'S of tasks so that they will begin execution in RAMO (scc section 8.4)

S'1'ANI)ARD 'I'ASKS

'I'hc standard Alto and its associated device controllers use many of the available tasks. Ilctailcd descriptions of the operalion of most tasks are found in the scctions of this manual rclcvant to the hardware devices. Appendix 1) is a list of the standard tasks.

Alto I l;irdm;lrc Manual

3.0 RMULATOK

Scction 3: 1Smul;ltor

'I'hc lowcst-priority Alto task is called the Emulator task. This task is always requesting wakeup, but can be intcrruptcd by a wakcup rcqucst fiam any other task. In effect, the cmulator task is the "background job." '1'11~ standard Alto microcode ROM includes standard cmulator task microcodc for fctching from Alto mctnory, decoding, and intcrprcting instructions fsom the Standard Instruction Set. In the rcst of this chapter we shall frcqucntly usc the term "emulator" to mean "standard ctnulator task microcodc." 'I'his standard microcodc can be cxtcndcd or replaced, usually by executing special cmulator task microcodc in thc microinstruction ]<AM.

This scction dcscribcs microcodc versions installed after June 1976. T o determine the vintage of a macl~iuc's microcodc, scc descriptioils of SIO and VERS (section 3.2).

3.1 Statrrlard Iristr~lctiorr Set

'I'hc cmulator state is carried from instruction to instruction in several rcgisters:

IT: 'l'hc "program counter," which contains the 16-bit address of the next instruction to be fetched and cxecuted. It is actually implcmcntcd as Il-register 6 .

ACO, A C ~ , A C ~ , A C ~ : l 'he accumulators, each of which contains 16 bits. Instructions arc available for transferring contcnts of accumulators to and from memory registers and for pcrfornling arithmctic and logical operations among accumulators. 7'hc notation AC(n) is often uscd to rcfcr to ~11c contcnts of accumulator n (n=0,1,2,3). l'hcse accumulators arc implcmcntcd as R-registers 3-0 rcspcctivcly.

c: 'l'hc "carry" bit which is modified by most arithmetic operations. It is iniplcmcntcd as special hardware (see section 3.5).

MI:MORY: 'l'hc Alto has "64K" 16-bit memory words, addrcsscd by valucs ranging from 0 to 17677711. Addrcsscs 177000~ to 17777713 arc rcscrvcd for various 110 device i~ses (see Appendix 13). Memory on Alto 11s can bc cxtcndcd to 256K in 64K ballks (sce Scction 2.3).

Additional 11- and S-registers may be uscd temporarily during emulation of a single instruction.

INSI'RUCI'ION 1:OIIMA'I'

'I'hc standard instruction set is bcst described by breaking it into four groups according to the way the instructions arc formaltcd (sec Figurc 3).

Scvcrnl of tlic instructions compute an "cffcctivc addrcss" bascd on the valucs of the I (indirect), x (indcx) and l ~ l s l ~ (disl~laccinenl) ficlds of thc M-group, J-group and some s-group inslructions. 'I'hc cffcctivc addrcss calculation is bcst dcscribcd by a brief "program." First wc dcfinc thc function Signl~xtcnd(x) to rcpscs~nt the sign-cxtcnsion of the $-bit n ~ ~ t n b c r x:

'I'hcn llffAddr(), the fiinction to compute the cffcctivc address is:

M-Group LDA (MFunc = 1) X = 0: Page 0 addressing STA (MFunc = 2) X = 1 : PC-relative addressing

X = 2: Base-register (AC2)

X = 3: Base-register (AC3)

0

J-Group JMP (JFunc = 0) JSR (JFunc = 1) ISZ (JFunc = 2)

DSZ (JFunc = 3)

MFunc

0 0 0

A-Group COM (AFU nc = 0) L (SH = 1) z (CY = I ) # (NL = 1) SKP (SK = 1) NEG (AFunc = 1) R (SH = 2) 0 (CY = 2) SZC (SK = 2) MOV (AFunc = 2) S(SH=3) C(CY=3) SNC (SK = 3) INC (AFunc = 3) SZR (SK = 4) ADC (AFunc = 4) SNR (SK = 5) SUB (AFunc = 5) SEZ (SK = 6) ADD (AFunc = 6) SBN (SK = 7) AND (AFunc = 7)

DestAC

w . JFunc I

1

Figure 3 - - Instruction Formats

I

X

SrcAC

0 1 1

DlSP

X

DestAC

AugmentedFunc

DlSP

1

DlSP

AFunc SH CY NL SK

Alto I-Iardware Manual Section 3: IZmulator

EffAddr() = [ //The sylnbol "E" denotes cffcctivc address ~t ( //Values of I,X, and DISP arc from the instruction

if x = 0 then 11rs1) //"page 0 addrcssing" clscif x = 1 thcn SignExtcnd(~1s~) +PC //"rclativc addressing" clscif x = 2 tlicn SignExtcnd(~)~s~) + A C ( ~ ) //"base register addrcssing" clseif x = 3 thcn SignExtcnd(~1~~) + hc(3) //"bast register addressing" 1

if r ;t 0 'thcu l i+rv(~) //Now do single-lcvcl indirection I.

7'hc notation for thcsc addressing modcs is demonstrated below. '1'11c LIISI) valuc is always spccificd first; thc x vnluc is not givcn cxplicitly, but is determined either by thc address of thc labcl or by a modifier ",2" or ",3" which spccifics base register indcxing:

JMP LABEL2 ; I f LABEL2 i s i n page 0 , X=O; o t h e r w i s e X -1 . JMP 1 5 , 3 ; D I S P = l 5 ; 3 means use AC3 as base r e g i s t e r . JMP 93 ; The c h a r a c t e r 8 causes I t o be 1.

Notc that instructions which compute an effcctivc address always do so bcforc any other opcrations. 'I'hus JSII 1,3 cornputcs thc cffcctivc address of l + ~ c ( 3 ) before saving PcS1 in AC3.

MllMORY GIIOUP 0PI:IIATIONS

'I'hc n c s t ~ c ficld spccifics onc of thc four accumulators (DCSMC=O for ACO, ~ ) c s t ~ c = l for A C ~ , ctc.). 'I'lic MI:LIIIC ficld spccifics one of two operations:

Mnetnonic MI.'unC Action

I I I A 1 This operation loads an accumulator from mcmory. ~ c ( ~ e s t ~ c ) + r v ( ~ ) . SI' A 2 This operation storcs an accumulator into memory. ~v(E)+Ac(~)cs~Ac).

'I'hcsc instructions arc writtcn by giving the mnemonic, followcd by thc accumulator nulnbcr (IICS~AC). followcd by an cffcctivc addrcss notation:

STA 3 .+4 ; S t o r e AC3 i n t h e f o u r t h l o c a t i o n f o l l o w i n g h e r e LDA 0 4 , 2 ; Load ACO f rom address=4+AC(2) LDA 0 @ . + 2 ; Load ACO f rom address c o n t a i n e d i n second l o c a t i o n f o l l o w i n g h e r e

JIJMP AN11 MO1)ll:Y GKOUI' OP1:RM'IONS

'l'hc J1:ilnC ficld spccifics onc of four operations:

Mncmonic Jlllnc Action

JMP 0 'I'llis operation causes a "jump" by changing thc valuc of thc PC. IC+I:. JSR 1 'l'his opcration is uscfi~l when calling suhroutincs bccausc it saves a rcturn

addrcss in A C ~ . AC(~)+I>C+ 1; PC+I%.

IS% 2 'l'his operation incrcmcnts thc contents of a memory ccll and skips if the ncw contcnts arc zcro. rv(19+-rv(1:)+ l ; if rv(li)=O thcn I)c+PC+ 1. l'his instruction docs not altcr thc c bit.

I)SZ 3 'I'his instruction dccrcmcnls tllc contents of a tnclnory ccll and skips if the ncw contc~lts arc zcro. rv(~i)+l.v(~i)-l; if I'v(I:)-- 0 llicn I ) c ~ . I ) C - ~ 1. This instruction docs not altcr thc c bit.

Alto 1-Iardwarc Manual Section 3: 1:mulator 14

'Thcse instri~ctions are writtcn by giving the mnemonic and thc cffcctive address notation:

JSn SUBR ; AC3 i s l e f t p o i n t i n g t o t h e l o c a t i o n a f t e r t h i s one JMP 1 , 3 ; Jump t o A C ( 3 ) + 1

ARII'IIMBI'IC GROUP OPI~llAl'IONS

All 8 of thcsc instructions opcratc on thc contcnts of the accumulators and thc carry bit. 'I'ypically, a binary opcration involvcs thc contcnts of the "source accumulator" ( s r c ~ c ) and thc "dcstiaation accumulator" (IXS~AC) and lcavcs thc result in thc dcstination accumulator. 'l'hc carry bit (C bit) and the PC can also bc rnodificd in the proccss.

'I'hc opcration of thc instri~ctions is best explained by following the flow in Figure 4. 7'hc 16-bit contents of thc sourcc and dcstinatiotl accumulators arc fctchcd and passcd to thc function gcncrator.

l'hc carry gcncrator produccs an output that dcpcnds on thc value of the C bit and thc CY field of the iustruction:

M~iemonic CY Output

nonc 0 C z 1 0 0 2 1 C 3 1-c (is., the complcmcnt of C).

'I'hc firnction gcncrator is controllcd by thc Al~ilnC field; various values will bc dcscribcd below. It takes two 16-bit numbcrs and a carry input and generatcs a 16-bit Rcsult and a carryKcsult.

'I'hc shiftcr is controllcd by thc S I I field in thc iustruction:

Mncmonic SII Action

nonc 0 No shifting; the 17 output bits arc thc samc as thc 17 input bits. I, 1 Iiotatc thc 17 input bits lcft by onc bit. l'his has t l ~ c cffcct of rotating bit

0 lcft into thc carry position and tllc carry bit into bit 15. I< 2 Iiotatc thc 17 bits right by one bit. Uit 15 is rotatcd into thc carry

position and LIIC carry bit into bit 0. S 3 Swap thc 8-bit halvcs of the 16-bit rcsult. l'hc cassy is not affected.

'I'hc skip scnsor tests various of thc 17 bits presented to it and may cause a skip (PC+I'C+~) if an appropsiatc condition is dctcctcd:

Mnc~nonic SK Action

nonc SKP S%C SNC S%K SNIl S1'Z SI3N

0 Ncvcr skip 1 Always skip 2 Skip if the carryResult is x r o 3 Skip if the carsyRcsult is non-zero 4 Skip if the 16-bit Result is zcro 5 Skip if thc 16-bit Kcsult is non-zcro 6 Skip if cithcr carryRcsult or Rcsult is zero 7 Skip if both carryResult and Rcsillt arc non.i:ero

To/From Memory Dest AC

w

Carry

Accumulators

Dest AC

16

I Carry Generator

1

Src AC

16

Function Generator

1 16

Shifter

1 16

Skip Sensor A

1 16

V v Governed by NL

Figure 4 - - Instruction Execution

Alto I-Ii~rtlwnrc M:~nual Scctiorl 3: Emu1;ltor 15

Thc alcrt rcadcr will dctcct that the s K ficld is microcoded. 'I'l~e skip condition can bc dcscribcd as:

skip = (SK[2]*0) xolr ((sK[O]+O AND result =0) OR ( s ~ [ l ] f 0 AND carryllcsult = 0))

whcre SK[O] is thc first bit of thc ficld, S K [ ~ ] thc second and s~[2]thc third.

'Thc NI, bit in thc instruction controls the opcration of Uic switch in thc illustration. If NI,= 1, ncithcr thc dcstination accumulator nor thc carry bit is loaded; othcrwisc the destination accutnulator is loaded from Rcsult and thc carry bit from carryRcsult. l'hc "no-load" feature is uscfi~l for instructions wliosc only usc is tcsting somc valuc. 'I'hc character # is appcndcd to the mncmonic for opcratiotis if the N1, bit is to bc set.

Thc ~r:unc opcrations arc described bclow. Note that "Result" will bc storcd into the dcstination accumulator ( l ~ s t n ~ ) unlcss NL= 1.

Mnctnonic AIXlnC Operation Description

COM

N EG

MOV

INC

AI>C

SUB

0 COMPLEMENI' Thc function generator produccs thc logical complctncnt of ~ c ( s r c ~ c ) . It passcs thc carry bit unaffccted.

1 NIZGATE Thc function gcncrator produces thc two's complcmcnt of ~ ~ ( s r c ~ c ) . If AC(S~CAC) contains zcro, complcmcnt thc valuc of tlic carry supplicd to thc function gcncrator, othcrwisc supply thc spccificd valuc.

2 MOVE l'hc function gcncrator passcs AC(SSCAC) and thc carry bit unaffected.

3 INCREMBNI' The Result produccd is AC(S~CAC)+~; thc carry is complc~ncntcd if AC(S~CAC) = 17777711.

4 ADD COMPI~IIMENT I'hc Rcsult produccd is thc sum of ~ ~ ( u c s t ~ c ) and thc logical complcmcnt of ~ c ( s r c ~ C ) . 'I'hc carry bit is con~plcmcntcd if thc addition gcncnttcs a carry.

5 SUBI'RACr Subtracts by adding thc two's cornplc~ncnt of AC(S~'CAC) to AC(DCS~AC). 'I'hc carry bit is complc~ncntcd if thc addition gcncrates a carry.

6 ADD Adds ~ c ( s r c ~ c ) to ~ c ( l > c s t ~ c ) . The carry bit is complcmcntcd if thc addition gcncratcs a carry.

7 AND The Rcsult is thc logical and of Ac(srcAc) and nc@cst~C). The carry is passcd unaffected.

'Ihc aritlitnctic instri~ctions arc writtcn by citing the AIxlnc mnemonic, followcd optionally by thc CY mncmo~lic, followcd optionally by thc SII mnemonic, followcd optionally by thc NI, tnncmonic. 'I'hcn aftcs a spncc, thc sourcc accumulator numbcr is givcn, thc destination accutnulator number, and optionally an SK mncmonic. For cxamplc:

SUB 0 0 MOVZ 2 1 SUBZL 1 1 ADC 0 0 SUB# 2 3 SNR

COMH 1 1 SZR SUBZH I 0 SZC ADCZH 1 0 SZC

; Z e r o ACO b y s u b t r a c t i n g i t f r o m i t s e l f ; Move AC2 t o AC1, and z e r o C ; S e t AC1 t o 1 ; S e t ACO t o 1 7 7 7 7 7 8 ; S k i p s i f AC2 and AC3 a r e u n e q u a l b u t ; a f f e c t s n e i t h e r ; S k i p s i f AC1 i s 1777778 b u t l e a v e s i t unchanged ; S k i p s i f ACO<ACl u n s i g n e d ; S k i p s i f ACO(AC1 u n s i g n e d

'1'0 subtract tlic constant 1 from ACI:

Alto I-lardware Manual Section 3: Emulator 16

NEG 1 1 COM 1 1

'1'0 OR together the contents of ACO and ~ c l ; rcsult in ACO: COM 1 1 AND 1 0 ADC 1 0

'1'0 XOR togcthcr thc contents of ~ c 0 and ~ c l ; result in ACO: MOV 0 2 ANDZL 1 2 ADD 1 0 SUB 2 0

7'0 negate a doublc-length ilunlbcr in ACO and ~ c l : NEG 1 1 SNR NEG 0 0 SKP COM 0 0

'1'0 add the double-length number in A C ~ , A C ~ to one in ~ c O , ~ c l :

ADD2 3 1 S Z C I N C 2 2 ADD 2 0

7'0 subtract the doublc-length number in AC2,AC3 from one in ACO,ACL:

SUEZ 3 1 SZC SUB 2 0 SKP ADC 2 0

'I'hc 13cpl construct "if a gr b then ..." uses code which docs a subtract and checks thc sign. Uuforlunalcly, this is not a truc signed compare because thc subtract may overflow. With this codc, 2 gr 0 is true, but 077777s gr 10000011 is false (077777~ is the largcsl positive nutnbcr and 10000013 thc largest negative). 7'hc codc generated by I3cpl looks likc:

LDA 0 4 , 2 ; P i c k up a LDA 1 5 , 2 ; P i c k up b AOCLU 1 0 SZC ; S u b t r a c t and check s i g n JMP f a l s e p a r t ; N o t t r u e JMP t r u e P a r t ; T r u e

'l'hc "true signed compare" for a>b is:

LDA 0 4 , 2 ; P i c k up a LDA 1 5 , 2 ; P i c k up b SUBZR 2 2 ; P l a c e lOOOOOB i n AC2 AND 1 2 ; A C 2 = ( i f b < O t h e n lOOOOOB e l s e 0 ) ADDL 0 2 ; C A R R Y = ( i f a and b s igns d i f f e r then 1 e l s e 0 ) ADC#/ 1 0 SNC JMP f a l s e p a r t JMP t r u e p a r t

0l)codcs in the range 60000~-7777713, arc assigned to the S-group, which colnpriscs a variety of miscell;illcous instructions and unimplcmcntcd operations. nits 3 through 7 of the instruction dctcrlninc 32 opcodcs, each of which may usc the displacclncnt field (bits 8-15 of the instruction). Onc of thesc opcodcs (blxxx, O<xxx<37713) uses the displaccmcnt ficld to rcprcscnt up to 250 inslructions wllich do not require a disl>lncc~ncnt or a parameter as part of the opcotlc.

Alto I Jiudware Manual Section 3: E~tll~liltor 17

Currently, only a small number of thc available S-group instructions havc bccn implcmcntcd. Thc remaining unin~plcmentcd instructions all trap in one of two ways:

llOM trap PC is savcd in location TRAPPC, and then a J M P d TRAPVBC+OP instruction is simulated. 01' is bits 3-7 of the trapping instruction.

TRAPPC 5 2 7 ~ When an unimplclncnted opcodc is cxccutcd by thc ctnulator, the PC is savcd hcrc. It points to tllc localion aRcr thc trapping instruction.

I.nArwl;c 53011-567n Contains pointcrs to the trap routincs for thc 32 opcodcs (bits 3-7 of the trapping instruction). 'I'hc first word corrcsponds to opcode 60xxx, 0<xxx<377u.

RAM trap If no microinstruction RAM is present, the trap is handlcd as a ROM trap. If a RAM is prcscnt, thc microcode transfers to location 'I'RAPI in tllc RAM with the trapping instruction in L., thc instruction cycled by 8 bits in the I<-register XRU.~;, and PC pointing to the location after the trapping instruction.

'This arrangement makes it convenient to extend the Alto's standard instruction sct by implcmcnting additional functions in softwarc which is dispatched to via ,I'I<AI'VI:~, or in microcodc which is dispatchcd to via a RAM trap. An appendix tabulates the S-group instruction set opcodcs and what cach docs or how it traps.

MUI, 61 02013 Unsigned multiply:

Multiply the unsigned integers in ~ c l and Ac2 to gcncratc a 32-bit product; add thc product to the integer in ACO. J,eavc the high-order part of thc rcsult in ACO and thc low-order part in A C ~ . ~ c 2 is unaffectcd.

LII v 6102113 Unsigned dividc:

'I'hc double-length unsigned integer in ACO and ~ c l is dividcd by the ilnsigncd intcgcr in ~ c 2 . 'I'hc quoticnt is left in A C ~ ; the remainder in ACO. Ac2 is unaffected. T'hc instruction normally skips the next instruction; if overflow occurs (ACO 2 AC2 unsigned), Dlv docs not skip.

CYC:I,E 6OOOOe Txft C Y C ~ C ACO:

1,cft cyclc (rotate) the contents of ACO by the amount specified in instruction bits 12-15, unless this value is zero, in which case cycle ACO left by the amount spccificd in bits 12-15 of ~ c l .

S S K I ~ 64400~ Jump to subro~~tinc double indirect, PC relative:

JSRIS 65000~ Jump to subroutine double indirect, AC2 rclativc:

Alto I-Iartlwarc Manual Section 3: Xmulator

CONVL:,R'I' 6700011 Scan convcrt a font character:

'I'he C O N V I ~ I ~ ~ insttuction does scan convcrsion of characters, LC., it transfcrs data bctwecn an arca of main lnclnory containing a font and an area of memory containing a bit map to be displaycd on thc 'rv monitor.

CONVBIIT takes a number of arguments:

ACO contains the addrcss of the destination word into which the uppcr lcft corner of the character is to be placcd, offsct by NWKIIS, thc numbcr of words to bc displaycd on each scan linc (ACO = IIWA-NWRDS).

AC3 points to a character pointer in the font for the character to bc displaycd (he3 = I:ONTI3AST:.+ CIIARACTEII CODE).

~c2+SignRxtctid(l)1~~) is thc address of a two-word tablc:

word 0: NWlIDS (numbcr of words per to scan linc); Nwlins < 128.

word 1: IIRA, the destination bit address corrcsponding to thc lcft hand edgc of the cl~aractcr. CONVERT interprets this bit addrcss rcverscd From the normal convcntion, i.c., 0 is the lcast significant bit, 15 thc most significant bit.

CONVEKI' scquires that a 16 word mask table be set up starting at MASK'I'A11 (46013) in page 1. SV(MASKTAII+ n)= (2r(n+ 1))-1 (OLnclS).

'l'hc format of an Alto font designed for use with CONVEIU' is givcn bclow; names of font filcs in this format conventionally have an extension ".AL". 'l'hc CONVERT instruction docs not cxamine thc words at I:ON~'I~ASI~-~ and I:ONTBASI:-1; thcsc are provided solcly for convc~~icncc of software.

'l'hc height of a line of text in scan lines. This numbcr incorporates the cffccts of the highcst and lowcst character in the font, j.c. it is I~~X(IIII~-XII)-~~II(IID) whcrc thc max and min arc taken independently and 111, and XII are dcfincd bclow.

I3it 0: 0 = Fixed width font. 1 = Proportional width font.

13its 1-7: Dascline -- numbcr of scan-lincs from top of highcst charactcr in font to thc baseline.

Ilits 8-15: ?hc width of the widcst charactcr in rastcr points.

Sclf-rclativc poirltcrs to word xw of thc charactcr dcscriptor block for the character codcs 0-377n.

'l'hcse locations contain self-rclativc poinlers to word xw of thc cllaracter dcscriptor blocks for extensions, LC., portions of characters which are wider than 16 bits. ~ : x r c ~ ' r is thc total number of character cxtcnsions.

Alto I-lardware Manual Section 3: Emulator 19

FONTIIASI; + 40013 + FXTCNT to end:

Contains a number of character descriptor blocks of the form:

word 0 to word xw-1: 'I'he bit map for the character and surrounding spaces. 'I'hc bit map docs not includc 0's at the top and bottom of the charnctcr, as the character will bc vertically positioned by C~NVIIRI'. The upper left-hand bit of the character is in the MSB of word 0.

word xw: If the character is 5 16 bits widc, this word contains (2*width)+l. If the character is > 16 bits widc, this word contains 2* a pseudo-character which is uscd as a charactcr codc to index an cxtension chnractcr in the font. If this is the last extension block of a character, this word contains (2* the width of the final cxtcnsion), rathcr than the total width. l'he pointer indexed by the character codc points to this word.

word xw+l: In the left byte, IID. In the right byte, XII . IID is the numbcr of scan lincs to skip before displaying the charactcr, xrr is the height of the bit map for this character.

'I'hc C O N V L ~ I V ~ instruction ORS the character bitmap into the display area. If the character docs not rcquirc an cxtcnsion, CONVI:R?' skips, with thc following inforlnation in the AC's:

ACO: unchanged ACl: 1>13A AN11 17B A C ~ : unchanged AC3: the width of the charactcr in bits

If the charactcr rcquircs an extension, CONVERT returns does not skip. nC3 contains the pseudo- charactcr code for the extension, and AC'S 0-2 are as above.

1 1 ~ 1 ,K 6100313 Iicad Clock:

'I'hc microcode maintains a 26 bit rcal time clock which is incrcmcntcd by the mcmory rcfrcsh task at 38.08 microsecond interv:ils (more prcciscly, oncc cvcry 224 ticks of thc systcm clock, whosc nominal frcqucncy is 5.880000 MHz). l'hc high-order 16 bits of this clock arc maintained in loci~tion 11'rC (43013) in page 1 'I'hc low-ordcr 10 bits arc kept in 1137. 'I'hc remaining 6 bits of 1137 contain statc infornlation unrclatcd to thc tilnc. KCI,K loads A C O with the contents of location IY~C, and loads ~ c l with the contents of 1137. 'I'hc pcriod of the full 26-bit clock is about 40 minutcs.

'l'hc contcnts of R37 arc slightly diffcscnt on Alto I and Alto IT: o n Alto I, ~3710-91 conbin the low order clock bits; on Alto 11, ~3714-131 are uscd. Consequently, on thc Alto I , the contents of ACO nuci ~ c l rcturncd by KCI.K may bc viewed as a 32-bit clock in units of .595 microseconds, proviclcd ~c1[10- 151 is first ~erocd.

SIO 6100411 Start I/O:

Start 110 is includcd to facilitate 110 control. It placcs thc contents of ACO on thc processor bus atid cxccutcs the s r ~ 1 1 n : filnction (11 = 1713). Ijy convention, bits of ACO must bc "1" in order to signal dcviccs. Scc Appcndix C for a summary of assigned bits.

Alto Ilnrdwarc Manual Scction 3: Emttlator 20

If bit 0 of ACO is 1, and if an Hthcrnet board is plugged into the Alto, tlie machinc will boot, just as if the "boot button" were pressed (see sections 3.4, 8.4, and 9.2.2 for discussions of bootstrapping).

SIO also rcturns a result in ACO. If the Ethcrnct liardwarc is installed, the scrial numbcr and/or Ethernet host address of the machinc (0-37711) is loaded into ~c0[8-151. (On Alto I, the serial number and I~thcrnct host address are equivalent; on Alto 11, the value loadcd into ACO is the Rthcrnct host address only.) If Ethernet hardware is missing, AcO[~-151 = 37713. Microcode installed aftcr Junc 1976, which this manual describes, returns ACO[O]=O. Microcodc installed prior to Junc 1976 returns AcO[O]= 1; this is a quick way to acquirc thc approximate vintage of a machine's microcode.

ILT 610058 Block transfer:

IU,KS 610068 Block store:

These instructions usc tight microcode loops to move a block of mcmory from onc placc to another (131:l') or to storc a constant value into a block of memory ( s l . ~ ~ ) . Block transfer and block store take the following arguments:

ACO: Address of the first source word-1 (nr.~), or data to bc storcd (131,~~). ACI: Address of the last word of the dcstination arca. A C ~ : Negative word count.

nccausc tlicsc instructions arc potentially time consuming, and kecp their state in the ~ c ' s , they arc interruptable. If an intcrrupt occurs, the PC is decrclncrltcd by one, and thc ~ c ' s contain thc intcr~ncdiatc state. On return, the instruction continues. 'On completion, the AC'S are:

ACO: Address of last source word+] (IKT), or unchanged (I~LKS). A C ~ : Unchanged. ~ c 2 : Unchanged. AC3: 0.

I'hc first word of thc dcstination arca ( ~ c l + nc3 4- 1) is the first to bc stored into.

6 100713 Star1 interval timer:

'I'hc microcode implements an interval timer which has a resolution of 38.08 microseconds, and a maximum pcriod of 10 bits. 13ccausc the principal application for this timcr is to do bit sampling for a serial 1;1~-1cs232 conipatiblc communications line, the timcr is spccializcd for this purpose. It uses three dedicated locations in page 1:

I 52513 Contains the time at which the next timer intcrri~pt sliould be caused. On Alto I, thc 10-bit time is stored in rl-r1n!ii[0-9], and the remaining bits must be zero. On Alto 11, the time is stored in l'l'll~1:[4-13], and the remaining bits must be zero.

n'lnrrs 42313 'I'liis word contains one or more bits specifying the channel or channels on which thc timcr intcrrupt is to occur.

II'QUAN 42211 When the interval timer intcrrupt is caused, thc n~icrocodc stores a quantity in this location which depends on the mode.

'I'he sn' instruction o ~ s the contents of ACO into K37. 'Ihc high 14 bits sliould be 0; the low- order 2 bits dcterminc thc interval tilncr mode:

Alto Ilard\v;~~.c Miin~tal

~37[14-15]

0 Off.

1 Normal modc. Every 38.08 rnicroscconds, tcst to scc if ( ~ 3 7 AND 'TIMEMASK)= 1l"TlMl:. (on Alto I, TIMEMASK = 177700~; on hito 11, the propcr valuc for TIMI~MASK is 77748, but vcrsion 23 of Alto 11 microcodc uses a value of 770013). If they arc cqual, cause an 'interrupt on the chantlcl spccificd by ~~~~~~~~~s. Store thc current statc of thc HA interface in ITQUAN, and sct ~37[14-15] to zcro. The statc of thc I ~ I A interface is bit 15 of location I:~AI,OC (177701~) in page 3778. This bit is 0 if thc line is spacing, 1 if it is marking.

2 Same as 0.

3 Every 38.08 microseconds, chcck the statc of the I;IA linc by reading EIAI,OC. If the line is marking (EIAI,OC is lion zcro), do nothing. If the linc is spacing, causc an interrupt on thc channel spccificd by I.nn17rs. Storc the current valuc of R37 in ITQUAN, and sct 1137[14-151 to zcro.

The intention is that a program which does EIA input call use lnodc 3 to monitor the linc for the arrival of a character, and can thcn usc mode 1 to time the ccntcr of each bit. Ily storing the shtc of the linc, thc interrupt latency can bc as much as 1 bit time without crrors.

JMI'KAM 61010k1 Jump to RAM: (see section 8.5 for details)

Switchcs the cmulator task micro 1'C to another microinstruction bank in ROM or RAM Tllc next ctnulator microinstruction will bc dctcrmincd from the valuc in ~ c l (mod 1024) -- scc the discussion of bank switching in section 8.4.

I<LII~AM 6lOlln ltcad IUM: (SCC section 8.5 for details)

Itcads thc control RAM halfword addressed by A C ~ into ACO.

Notc: In Alto 11s running microcodc version 2, this instruction does not work rcliably if the Hthcrnct intcrfacc is running.

WR'I'RAM 6101213 Wsitc RAM: (SCC section 8.5 for dctails)

Wrilcs ACO into thc high-ordcr half and AC3 into thc low-ordcr half of thc control RAM word addrcsscd by A C ~ .

VL:.RS 61014~ Version:

ACO is loaded with a numbcr which is coded as follows:

bits 0-3 Alto cnginccring number

0 or 1 Alto I 2 Alto I1 3 Alto T I with cxtcndcd incmory

bits 4-7 Alto build nutnbcr.

bits 8-15 Vcrsion nut~lbcr of thc microcodc.

'I'his instruction pcrlnits programs to know thc diffcrcnccs alllong various kinds of Altos. Usc of thc Alto build number (bits 4-7) has bccn abandoned; its contcnts ilrc undcfinctl. 'Ihc two flavors of Alto maintain scparalc enumcratio~~s of microcodc vcrsions (scc scclion 9 for soinc

Alto IIi~rdwarc Manual

convcntions).

DRIIAI) 6101 SU Doublc-word read (Alto I1 only):

IIWRI'~I: 61016~ Doublc-word writc (Alto I1 only):

DI~XCII 6101711 Double-word cxchangc (Alto I1 only):

I ~ I A G N O S I ~ ~ 61022~ Diagnostic instruction (Alto I1 only):

'I'his inslruction starts a spccial doublc-word writc cycle that also writcs thc Ilamming codc check bits.

~~(177026~1) + AC2 (set 1 Jamming code) TV(AC~)+ ACO; SV(AC~ XOR I)+ A C ~

DlAGNOSI:2 6102313 Iliagliostic instruction (Alto I1 only):

'I'his instructiol~ writcs the same mcmory location with two diffcrcnt valucs in quick succession:

rv(~c3)+ ACO r v ( ~ c 3 ) t ACO xor A C ~ ACO+ ACO xor ~ c l

111~1'111:r 6 102411 nit-boundary block transfer:

An instruction for moving bits around in mcmory. It is particularly hclpli~l for dealing with thc display bit Inap. nrw:r rcquircs thc RAM to bc present in ordcr to use somc S rcgistcrs (418 through 5111). If the IiAM is not prcscnt, RITBLT will trap as if it wcrc an unimplcmcnted operation.

'I'hc nrrnl:i' function is invokcd with:

A : 0 AC2: pointer to nln'ablc, which must bc cvcn.

Only A C : ~ i s prcscrvcd by nn'1u:r.

'I'hc most common errors whcn using this instruction arc failing to align thc n~n'ablc on an evcn word boundary, failing to zero A C ~ , and failing to zcro I ~ u N c I ' I ~ N [ ~ - ~ ] .

'I'hc fornint of the ~ ~ s r a b l c is:

Alto Hardware Manual Section 3: Elnulator 23

Word Name Remarks

1:UNCTION unused I1BCA I ~ I I M R * I)IX* IITY * I)W * 111-1 * SI3CA SBMR SLX* S?Y * Gray0 Gray1 Gray2 Gray3

Operation, Sourcerrype, Bank, ctc

Ilcstination BCA Ilcstination BMR Ilcstination LX Dcstination TY Dcstination w Ilcstination H Source DCA SOUSC~ RMR Source LX Source TY Four words to specify gray block ...

*These should all be positive values, although if L ~ I I < O or nw<O then III'I'RLT is a NOP.

Trick: since nrrnl,?' uses all of the accumulators, I3CP1, programmers must savc AC2, the stack pointer, somcwhcrc. Put it in word 1 of the RRl'ablc, since AC2 still points at the tablc after the instruction finishes, making it easy to recover.

'I'hc instruction is interruptable as it begins consideration of each scan line. If an interrupt happcns, the statc of its progress is saved in ~ c l and the PC is backed up so that o n return from tlic interrupt, ~ ~ ' r r u , ~ will finish its job. This is the reason why ~ c l must bc zcro whcn starting the instruction.

A bit t~trl) is a rcgion of memory dcfincd by nCA and BMR, whcrc DCA is the base core address (st;\~-Ling location) and DMR is the bit map rtrsler widlh in words; the number of scan lincs is il-sclcvant for our purposes. (If both RMR and I3cA are even, thcn the bit map [nay be displnycd o n the scrccn itsing standard Alto facilitics.)

A block is a rectangle within a bit map. It has four corners which need not fall on word boundaries. A block is described by 6 numbers:

13CA nit map's basc core address BMR llit map's width in words I x 13lock's left x ("x offset" from first bit of scan-line) IY 13lock's top Y ("y offset" from first scan-line) W I3lock's width in bits I I 13lock's height in scan-lines

I:jcr/tt~ple: A block is i~scd to dcsignatc a scqucncc of bits in memory, such as a I6 widc 14 high rcgion containing the bit pattern of a font character. In this casc, I3CA points to the font cllari~cter, R M I ~ is 1, I X and TY arc 0, w is 16, and 11 is 14. If source and destination blocks overlap, they had better have thc same BCA.

Alto I l;~rdwiire Mitnual Section 3: Emnlator 24

The basic block operations operate by storing some bits into a "destination block." 'i'hc source of thcsc bits varies; often it is another block, the "sourcc block." 'I'hcrc arc various fu~ictio~ls that 13n.lw:r can perform.

'The I:UNCI'ION word of the able contains a number of fields:

I~uNC'IION[O-~] Must be zero UNCTION[^^] Source block is in the alternate bank t ; u ~ c n o ~ [ l l ] Destination block is in the alternate bank 1 : u ~ ~ o ~ [ 1 2 - 1 3 ] Sou rce'l'ype ~ u ~ c r r o ~ [ 1 4 - 1 5 ] Operation

The operation field specifics the operation to be performed on the sourcc and dcstination blocks:

Opcration Name Action

0 Replace Destination Block + Source 1 Paint Ilcstination Block + ,I'ource OR l jeslinnlion 2 Invert Destination Block + Source xOl< I~estirrulion 3 1 'rase 13cstitiation Block + (NOT Source) AN11 1,eslinalion

The SourceTyl~e specifies how the Source as uscd in the above 4 opcrations is to bc computed. 'I'hc cncodings are:

So~lrceType Meaning

0 Source is a block of a bit map 1 Source is the complelncnt of a block of a bit map 2 Source is the logical "and" of a soi~rcc block and the "gray block" (see

below). 3 Source is the "gray block."

'J'lic "gray block" is conceptually a block of infinite cxtcnt in which a pattern of dots is repeated. 'I'hc paltcrn is specified by foul. words (Gray0 tllrough Gray3). 'I'l~csc give the pattcrns to write into the destination block where called for, one gray word per scan line. 'I'hc words will align with dcstination block word boundaries, but BI,~BI,T will use Gray0 through Gray3 in tllc order it1 wllicll 111'1'131:1' P~OCCSSCS scanlincs (either top to bottom (LYI'Y<SI'Y) or bottom to top (L)I'Y>s~Y)).

'l'hc most comn~on usc of these gray values is to generate a uniform pattcrn. While the I3I'I'BL'r instruction takes carc of going through these values appsopriatcly, the table must be phased propcrly to eliminate seanis. Specifically, if A I3 c D are the desired 16-bit word-aligned values of gray for scan-lincs 0 1 2 3 (mod 4), tlicn two adjustments must be made:

I,ct Q =r IYl'Y + 1. If I Y ~ Y < S ~ Y , then exchange n and D and let Q = -(ary+1)11+2). IXotntc the pattcsn left ( i .~. , A + I ~ , B+C, etc) a total of (Q AND 3) times. Sct GrayO+~, Grayleu, G r a y 2 + ~ , Gray3+1>

When the sourcc is a block of bit map, the width and height parameters of the block are not needed: thc width and height of thc dcstiantion block arc also uscd as the width and hcight of tlic sourcc block. It is pcr~nissible for the so:irce and destination blocks to overlap, such as when slidilig an cxisling block around within a bit map; 131'rrlr:r will move words in the order required for the corrcct rcsults. Ilowcvcr, if t11c source and dcstinalion blocks do overlap, they nus st belong to the same bit nlap ( if . , I,l3cA=Sl3CA and 11~~11-SI~MR).

Alto I I:~rtlwnrc Manual

'I'lle microcode has roughly thc following speed charactcristics:

Horizontally, along one raster line (so to speak):

store constant 13 cycles/word move block 23 cyclcs/word if skew not zero add 6 if source not zcro add 7 1st or last word add 13 function not store add 6

Vcrtical loop ovcrhead (time to change raster lincs):

14-21 cycles/scanlinc, depending on source/dcst alignment add 6 if function uses gray

Initial setup overhead (time to start or resume from interrupt):

approximatcly 240 cycles

I'otal for a typical character, 8 wide by 14 high:

approximately 1500 cycles

Ihese timings all in units of Alto microinstriiction cycles and do includc all memory wait time and do rlol include any degradation due to competing tasks, suc11 as the display or disk. For typical characlcrs on the Alto screen, om131rr is about 2/3 the speed of CONVI:R'I'.

XMI .I)A 610250 Extended Mcmory Load Accumulator (Alto I1 only)

1,oads ACO from the location addressed by ~ c l in thc alternate bank.

XMSI'A 61026~ Extcnded Memory Store Accumulator (Alto 11 only)

Stores ACO into the location addrcssed by A C ' ~ in thc alternate bank. If the the addressed bank of memory has not been installed, the instruclion yields undefined results and will probably causc a parity crror. See scction 2.3.

Alto f1artl~varc Ma~iunl Section 3: Eniulator

3.2 Interrupts

'I'hc cmulator microcode provides 15 cllannels of vectorcd intcrrupts. l'hc microcodc implements only a singlc lcvcl of intcrrupts; however, a multi-level priority intcrrt~pt systcm may easily bc implcmcntcd in software (scc below).

Interrupts may bc caused in two ways:

microcode 'I'his method is used by 110 device microcode. A device usually has a dedicated location in which the CPU program places a word containing oncs in the bit positions corresponding to the channels on which to cause intcrrupt(s) upon completion of 110 activity. 'I'hc cmulator is guaranteed to notice an intcrrupt caused in this way within one instruction.

software This method is used by a c ~ u program. A program causcs intcrnrpts by acing into location ww one bits corresponding to the channels on which interrupts should occur. l'hc emulator is rlot guarantccd to notice an interrupt caused in this way until an E I I ~ instruction is executed.

Whcn an interrupt occurs, further intcrrupts arc disabled and thc state of the interrupted CIW program is contained in ACO-3, CARRY, and PC, which must be savcd and rcstorcd by thc interri~pt routine. Intcrri~pts can occur between instructions or during long instructions, in which case the instruction's intcrnicdiatc state is savcd in the accumulators and PC is backed up so that the interrupted instruction is re-executed when the interlupt is dismissed.

If two intcrr.upts arc requested simultaneously, the onc with thc higlicst-numbcrcd channcl will bc serviced first.

'1'11~ interrupt system uses a number of fixed locations in page 1:

ACHVI; 45313 This word contains ones for the channels on which interrupts arc permitted to occur. Rit N is set to one to enable channel N. Ilil 0 is rcscrvcd and should not be set by any program.

ww 45213 This word contains bits for channels on which interrupts are pcnding. This infonnation is only valid whilc the intcrlupt systcm is enabled. ])it conventions arc the same as for ACI'IVI;. ww is r ~ o t updated when interrupts are disabled -- wakcups caused from microcodc accumulate in NWW until intersupts arc enabled.

PCI ,OC 50013 When an interrupt is initiated, the PC is savcd here. If the a )u program allows ncstcd intcrrupts, this location must be savcd bcforc re-enabling interrupts.

INTVI:C 501 13-5 171% Contains pointers to the service routines for thc 15 in tcrrupt channels. The first word corresponds to channcl 15 (bit 15) and the last corresponds to cliirnl~el 1 (bit 1). Channel 15 is permanently assigned to handling main memory parity errors.

'lhc interrupt system uses four inst~uctions:

Alto Il;~l.tlwarc Mi~nual

111 1t 6100011 Disablc interrupts:

1)isablcs thc intcrrupt system. If more than one intcrrupt is initiatcd on a channcl while intcrrupts arc disablcd, only onc will occur whcn interrupts are rc-cnablcd.

DIKS 61013~ Disablc intcri-upts and skip if on:

1)isablcs thc intcrrupt system and skips the ncxt instruction if intcrrupk wcrc cnablcd at thc start of this instruction.

EIK 61001~ Enablc interrupts:

Enablcs tllc intcrrupt systctn. Intcrizlpts initiatcd whilc intcrrupts werc disablcd occur aflcr this instruction.

RRI 61 002s Branch and return from interrupt:

Simulates a JMP @PCI.,OC instruction, and then enables the intcrrupt system. Interrupts initiated whilc intcrrupts were disablcd occur aftcr this instruction.

'Thc codc bclow is a samplc intcrrupt handlcr for onc channel, say channcl 10. It pcrmits ncstcd intcrrupls from highcr priority channels, whcre thc priority is dctcnnincd by software. l'his is accomplished by turning off all lower-priority channels and re-cnabling intcrrupts (which wcrc disablcd by thc microcode at thc onsct of this intcrrupt). Bcforc dismissing thc intcrrupt, it is ncccssary to disable the inlcrrupt system and turn thc lower-priority channels back on.

I n t e r r u p t : STA 0 SavedACO ; save t h e i n t e r r u p t e d p r o g r a m s t a t e STA 1 SavedACl STA 2 SavedAC2 STA 3 SavedAC3 MOVR 0 0 STA 0 SavedCarry LDA 0 CIPCLOC STA 0 SavedPC

LDA 0 @ACTIVE ; d i s a b l e l o w e r p r i o r i t y c h a n n e l s STA 0 S a v e d A c t i v e LDA 1 ChanMask AND 1 0 STA 0 @ACTIVE

EIR

DIR

; r e - e n a b l e i n t e r r u p t s ; s e r v i c e t h e i n t o r r u p t ; d i s a b l e i n t e r r u p t s

LDA 0 S a v e d A c t i v e STA 0 @ACTIVE ; r e - e n a b l e l o w e r p r i o r i t y c h a n n e l s

LDA 0 SavedPC ; r e s t o r e t h e i n t e r r u p t e d p rog ram s t a t e Sl-A 0 @I'CLOC ILLIA 0 SavedCarry MOVL 0 0 LDA 3 SavedAC3 LDA 2 SavedAC2 LDA 1 SavedACl L[)A 0 SavedACO BRI ; d i s m i s s t h e i n t e r r u p t

SavedACO: 0 SavedACl: 0 SavedAC2: 0 SavedAC3: 0

; t h e s e l o c a t i o n s ~ i j u s t be p r i v a t e t o t h i s channe l

Allo Hardware Manual Section 3: Kmulator 28

SavedCarry : 0 SavedPC: 0 SavedAc t i ve : 0

PCLOC : 500 ACTIVE: 453 ChanMask: 37 ; c o n t a i n s ones f o r h i g h e r p r i o r i t y c h a n n e l s

It is customary (though not essential) to assign interrupt channel priorities such that channel 15 has the highest priority and channel 1 the lowest. In \his casc, the ChanMask for channcl i s intcrrupt routine will consist of 15-i one bits right-justified. In any casc, ChanMask trzusl contain zero in the bit corrcsl>onding to the intcrrupt channel bcing serviced.

'I'hc codc bclow initiates interrupts on the channels corrcsponding to one bits in ACO. It must disable interrupts to prevent ww from bcing changed by microcode-initiated interrupts.

C a u s e I n t : COM 0 0 DIR LDA 1 OWW AND 0 1 ADC 0 1 ; AC1 + ACO OR AC1 STA 1 @WW E IR ; t h e i n t e r r u p t happens a f t e r t h i s

WW: 452

If a channel's A c r l v r ; bit is 0 when viewed from non-interriipt level, thcn the channel is not in use. I'hc codc below scarches ~ c r r v l : for the highcst priority free channel. It is careful not to assign the parity intcrrupt ch;int~cl. It then initializes an interrupt handler on that channel and returns a word with a otlc in the bit position of thc assigned channel. It must not be called from intcrrupt Icvcl.

; e n t e r wit11 ACO = t h e a d d r e s s o f t h e i n t e r r u p t h a n d l e r I n i t c h a n : Sl-A 0 INTHANDLER

SUB 1 1 ; AC1 + 0 SUIIZL 0 0 ; ACO + 1 LDA 2 @ACTIVE

FFC: MOVZL 0 0 SZC JMP f a i l ; no i n t e r r u p t c h a n n e l s f r e e .

INC 1 1 AN[)# 0 2 SZR ; f r e e ?

JMP FFC ; no. T r y t h e n e x t one

LOA 2 INTVEC ; i n s t a l l h a n d l e r i n INTVEC ADD 1 2 L.DA 3 INTHANDLER STA 3 0 2

L.OA 2 @ACTIVE ; t u r n on t h e channe l ADD 0 2 ; c a n t c a r r y : e q u i v a l e n t t o OR STA 2 @ACTIVE

; ACO = o n e - b i t 111ask d e s i g n a t i n g t h e a s s i g n e d channe l

I N I VEC : 501 INTIIANDLER: 0 ; temp

'I'hc codc below destroys thc intcrrupt channcls corresponding to one bits in ACO. It must not be called from interrupt lcvcl.

D e s t r o y I n t : COM 0 0 I.I)A 1 @ACTIVE ANI) 0 1

Alto 1l;lrtlwarc Miulual Section 3: ICmalator 29

STA 1 @ACTIVE

In addition to thc main memory locations, the interrupt system uses one R-r~gis t~r : NWW, new interrupts waiting. Rit 0 of N W W is 0 if the intcrri~pt system is enabled and one if it is disablcd. 'I'his is why there are only 15 channels of interrupts and why WW[O] should never be set. 110 device microcode 0 1 ~ s bits into this register to causc intcrri~pts. (NWW OR WW) expresses all pcnding intcrrupts.

'I'hc main loop of thc cmulator checks NWW during the fetch of cach emulated instruction. If NWW is grcatcr than zero (LC., NWW[O] is ,101 sct incaning thc interrupt systcln is on, and at least one bit is set in NWW[l-15] meaning an intcrrupt is pcnding on some channel) thcn the microcodc computes (NWW OR ww) A N D ACTIVE. I f this quantity is nonzero ( i .~. , an interrupt is pcnding and its channel is active) then an intcrri~pt is causcd. If not, NWW OR ww is stored in ww, Nww is zcrocd, and the instruction is rcstartcd.

If an interrupt is causcd, the microcodc stores the program counter in PCLOC, scts Nww[O] to disable further interl-upts, clcars the bit in NWW and in ww corresponding to the channel on which thc interrupt is occurring, and loads PC with ~V(INTVEC+~~-CIIANNEL, ) .

Whcn thc intcrnlpt system is disabled (by cxccuting DIR or I,II<S or initiation of an intcrrupt), the microcode sets NWW[O]. When the interrupt systcm is enabled (by cxccuting lirli or 13li1), the microcode clcars NWW[O] and OIis ww into NWW.

'I'his organization is optimized to minimize the cost (in additional microinstructions in the emulator main loop) of tlic most common casc where the interrupt system is cnablcd and no intcrrupts arc pcnding. Wlicn a bit appears in NWW whilc the intcrrupt system is activc, it is either cleared by causing an inten'upt or flushcd into ww whcsc it is checked less often, since thc cost of deciding that an interrupt is pending but that tlic channel is inactive is too high to tolcrate on each pass through the main loop. The assn~nption in flushing inactive bits into ww is that t l ~ c CPU progranl will enable interrupts sllortly after changing ACTIVI:, and doing so will cause the pcnding bits in ww to bc reconsidered.

'I'hc cmulator contains ~nicrocodc for initializing the Alto in certain ways, and thcrcby "bootstrapping" a runnablc program into the machinc. A "boot," which is invoked cithcr by prcssing the small button at thc scar of thc kcyboard or by cxccuting an appropriate SIO instruction (see section 3.3), simply rcscts all micro-l>c's to fixcd initial valucs dctcrmincd by tllcir task numbcrs. Unless tlic Reset Modc Register specifics othcrwisc (scc section 8.4), the cmulator task is started in the PROM and performs a nutnbcr of operations:

1. 'l'he current valilc of PC is storcd in rncmory location 0. '['he cmulator accumulators are not altcrctl during booting.

2. 'I'hc display is turncd off; i.e. rv(42013)+0.

3. Intcrrul~ts arc disabled.

4. 'I'hc first keyboard word (KRIIAD, 17703413) is read to dcterminc what sort of boot is to be done:

Disk Ijoot: If the < I S > kc)! is not dcpresscd, thc microcodc interprets any dcprcsscd keys rcportcd in this kcyboard word as a real disk address. I f no keys arc dcprcsscd, this results in a rcal disk addrcss of 0.

Alto Hardwi~rc Manual Section 3: Enlulator 30

The single disk sector at the givcn address is rcad: the 256 data words arc rcad into locations 1 to 4 0 0 ~ inclusivc; the label is rcad into locations 402n to 41111 inclusivc. When thc transfer is complete, r c t l , and thc cmulator is started. 'I'lic disk status is stored in location 2, so thc bootstrapping code must skip this location.

Etlicr Iloot: If the <ns> key is dcprcssed, thc microcodc anticipates brcatliing lifc into thc Alto via the Ethernet. The L?tlicrnct hardware is set up to read any packet with destination Alto number 37713 into locations 1 to 40011 inclusivc. If a packct arrives with good status and wit11 memory location 2 (i.c., thc second word of the packct) equal to 6 0 2 ~ (a "Brcath-of-Life" packct), IVY-3, and thc emulator is started.

More information regarding boot loaders and boot file formats is found with lluildboot documentation in the Alto Subsystcrns Manual.

'I'hcrc is a stnall amount of special hardware which is uscd cxclusivcly by thc ctnulator. This hardware is controlled by the task specific F2's, and by the + l l lS l~ bus sourcc.

'l'hc IR register is uscd to hold thc current instruction. It is loaded with I R + ( ~ 2 = 1411). l l i+ also mcrgcs bus bits 0,5,6 and 7 into NEXI'[~-91, which does a first level instruction dispatch.

'rhc high ordcr bits of IR cannot be rcad directly, but the displaccmcnt ficld of Ilr (8 low ordcr bits), may bc rcad will1 thc +DISP bus sourcc. If thc x field of thc instruction is zero (LC., it spccifics page 0 addressing) ~ h c n thc IIISP ficld of the instruction is put on ~us[8-15] and 13us[0-7] is zcrocd. If the x ficld of the instruction is nonzcro (i.e. it specifics PC-rclativc or base-rcgistcr addressing) tlicn thc DISP ficld is sign-extended and put on thc bus.

1%~~[8-15]+ IR[~-151 1%us[0-7]+ if 11<[6-7]=0 then 0 clscif 1~[8]=0 then 0 else -1

'l'hcrc arc two adclitional 12's which assist in instsuction decoding, rl,rsl' and +~csoulzCl<. 7'hc II>ISI' fi~nction (1:2= 1513) does a 16 way dispatch under control of a PROM and a multiplcxc~~. 'Ibc values arc tabulated below:

Conditions oRcd onto NEXT Comment

if clscif clsci f clscif clsci f clsci f clscif clsci f clsc

then 3-11<[8-91 complcmcnt of SII field of IR then IR[~-41 JMP, JSR, IS%, DSZ then 4 LDA then 5 STA t l l~ll 1 then 0 thcn 1611 CONVERT thcn 6 11t[4-71

+ACSOURCL:. (1:2= 1613) has two roles. First, it rcplaccs the two-low ordcr bits of tllc K sclcct field with the coniplcrncnt of the SKAC ficld of I I ~ , (11z[1-21 xolc 3), allowing tlic emulator to address its acci~nii~lators (which arc assigned to 1t0-1~3). Sccond, a dispatch is pcrfotmcd:

Alto ll:~rOware M:~nual Scction 3: ISn~ulntor 31

Conditions

if I R [ ~ ] = 1 clseif IR[~-21 Z 3 clseif 111[3-71 = 0 elscif 11t[3-71 = 1 clseif 1 ~ [ 3 - 7 ] = 2 clscif 111[3-71 = 3 clseif 111[3-71 = 4 elscif 11t[3-71 = 1113 clscif 1~[3-71 = 1 2 ~ clseif 1~[3-7] = 1 6 ~ elseif 11<[3-71 = 373 clse

thcn 3-I@-91 then I R [ ~ ] then 2 then 5 then 3 then 6 thcn 7 then 4 then 4 thcn 1 then 1 7 ~ 1 6 ~

tlic co~n~lcment of the SII field of IR the Indircct bit of I R CYCLE RAMTRAP NOPAR -- parametcrlcss opcodc group RAMTli AP RAMTRAP JSRII JSKIS CONVERT ROM'TRAP -- used by Swat, the debugger RAM'I'RAP

Acnl :sr , 1:2= 130, causes (IR[~-41 XOR 3) to be used as the low-order two bits of thc RsEi ,Eer ficld. This addresses the accumulators from the dcstination ficld of the instruction. 'The sclcctcd rcgistcr may be loaded or scad.

'I'hc c~nulator has two additional bits of state, the SKIP and C A I ~ R Y flip flops. CAai ty is distinct from the microprocessor's Al.ucO bit, tcstcd by the AI.UCY fi~nctio~i. CARRY is sct or clearcd as a function of 1R and many othcr things (scc scction 3.1) when thc DNS* (do novel shifts, r:2=1213) furiction is cxccutcd. In particular, if 1R[12] is tnle, CARRY will not changc. I>NS also addrcsscs R from (3-IR[~-4]), causcs a store into I< unlcss 11<[12] is set, and scts the SKIP flip flop if appropriate (see scction 3.1). l'lle elnulator microcodc increments by 1 at the beginning of the next emulated instruction if SKIP is set, using INS -1 SKIP (AI>UI:= 1313). IR+ clears SKIP.

Note that thc functions which replace the low bits of RSEI,EC?' with 1R affect only thc sclcction of R; they do not affect the address supplied to the constant ROM.

'I'wo additional cmulator specific f~~nctions, 1 3 u S o n I ~ (172=101i) and MAGIC ( ~ 2 = l l n ) , arc not ~>cculiar to emulation, but arc included for thcir gencral uscfulncss. BUSOl~D merges nuS[l5] into N I ~ x ' I [ ~ ] . MAGIC is a modifier applicd to I , I,SII 1 and I , RSH 1 to allow doublc lenglh shifts. I , I.SII 1 and I, ]is11 1 normally shift zcro into tlic vacatcd bit position in the shiftcr output. MAGIC placcs thc high ordcr bit of 1' into tlic low ordcr bit of tlic shiftcr output on lcft shifts, and placcs the low ordcr bit of 'r into thc high order bit position of thc shiftcr output on right shifts. ('l'hc microasscmblcr acccpts I, M I ~ I 1 to spccify the combination of L l S l l 1 and MACiIC, and similarly for I, MRslI 1.)

'Ihc srAl<i'1: function (I:I =17n) is generated by the sro instruction, and is used to dcfinc commands for 110 hardware, including the Ethernet.

'l'hc ICSNI: function (!:I= 1 6 ~ ) is dccodcd by the Rthcrnct interfacc, which gates thc host address wired on the backplane onto 1lrrs[8-151. uus[O-71 is not drivcn and will thcrcfore be -1. If 110 Etlicrnct interface is prcscnt, I ~ U S will be -1.

Alto I-liirtlw:~re Manual Section 4: Disp1:ry Controller 32

4.1 Programtru'ng Characteristics

'I'hc display controllcr handlcs transfcrs bctwccn the main mcmory and thc CRT. The cn'r is a standard 875 linc rastcr-scanned I 'V monitor, refreshed at 60 fields per second from a bit map in main memory. 'The cri'r contains 606 points horizontally, and 808 points vertically, or 489,648 points total.

'I'hc basic way in which information is prcscnted on the display is by fctching a series of words from Alto main mcmory, and scrially cxtracting bits to bccomc the video signal. 'I'hcreforc, 38 16-bit words are requircd to reprcscnt cach scan linc; 30704 words arc required to fill thc scrccn.

The display is dcfincd by one or more display control blocks in main mcmory. Control blocks (DCB's) arc linkcd togcther starting at location 1111sl'~w(420n) in page 1:

IIAS'rAR'r: Pointer to word 0 of the first (top on the screen) n c ~ , or 0 if display is off.

IIASI'ART+~: Vcrtical ficld intcrrupt bit mask. Every 1/60 sccond, this word is 01t'cd into NWW to causc interrupts, even if the display is off (i.e., ~V(DASTART)=~).

Ilisplay control blocks must begin at evcn addresscs in mcmory, and have the following format:

IICB: 130iiitcr to ncxt DCB, or 0 if this is the last.

I>CII+ 1: I3it 0: 0 = high resolution mode 1 = low resolution mode

Bit 1: 0 = black on white background presentation 1 = white on black background

Bits 2-7 ( A ) : On each scan line of this block, wait 16*11'1'AD bits bcforc displaying information from mcmory.

I3its 8-15 (NWI<IX): Each scan line in this block is defined by NWKDS 16 bit words. (NWRDS must be evcn). 111 order to skip space on the scrccn without rcquiriiig bit-map, set NWRlIS Lo 0.

11cn+2 (sA): I3it map starting addrcss, which must be evcn.

r , c ~ - t 3 (s I ,~) : 'I'his block dcfitics 2*S1,c scan lincs, SIX: in cach ficld.

At thc start of cach ficld, the display controllcr inspccts DASTAK~ and D A S ~ ' A R T + ~ . An interrupt is initiated on thc cliannel(s) spccificd by the bit(s) in r I ~ s l ' ~ I c r + 1. l'hc controller thcn cxccutcs each 11c1, scqucntially until thc display list or tlic ficld ends. At normal resolution, tlic first scan linc of the first (evcn) ficltl of a block is taken from location SA to SA~NWIIDS-1, the first scan linc of thc odd field is takcn from locations S A S NWI1DS to SA+~*NWRDS-1. Iluring cach display ficld, the bit map addrcss is incrcmcntctl by an cxtra NWI<IIS bctwccn cnch pair of scan lincs. In low rcsoliition mode, thc video is gcncn~tccl :I[ half spccd, anti cach scan Iitic is displayed twicc (oncc in cnch ficld). lli~ritig cach ficld, the bit map acldrcss is not incrcmcntcd by an cxtra NWRI)S bctwccn thc display of adjaccnt scan lines. ~I'his makes tlic format of tlic bit map in mcmory identical for both modcs--only the size of the prcscntation is affcctcd by thc modc.

'I'hc display controllcr consists of a sync gcncrator, a data buffer and serializing shift rcgistcr, and thrcc niicrocodc tasks which control data handling and communicate with tlic Alto program. 'I'hc hardware is shown in block form in l;ig~11.c 5. 7'11~ 16 WOI'CI bilfrcr is loaded from thc Alto bus with tllc i)1)1<+

Section 4: 1)isplay COII troller 33

fittiction (I?= 1011, specific to the display word task DWT, illegal in an instruction which stops the clocks). 'I'lic purposc of the intermediate buffer is to synchronize data transfers between the main buSScr, which is synchronous wit11 the 170ns. maslcr clock, and the shift rcgistcr, which is clocked with an asynclironous bit clock. 'lhc sync generator provides this clock and thc vcrtical and horizontal synclironization signals required by the monitor.

'I'hc bit clock is disabled by vcrtical and horizontal blanking, and its rate can bc set by tlic microcode to either 50 or 100 ns. by the filnction SE~MODI; (I?= l l n , specific to thc display horizontal task I)IIT). This function examines the two high order bits of the processor bus. If bit 0= 1, tlic bit clock rate is set to 10011s period (at the start of the ncxt scan line), and a 1 is mcrgcd into NEX'r[9]. SITMODE also It~tclies bit 1 of the processor bus and uses the value to control the polarity of the video output. A third filnction, I:.VI~N~:II:I,II (1:2= 1013, specific to nIn' and to the display vertical task l,vl'), nlcrges a 1 hito NL:.X'r[9] if the display is in the even ficld.

'I'hc display control hardware also gcncrates wakeup requests to the microproccssor tasking hardware. 'I'hc vcrtical task I ) ~ T is awakened oncc per ficld, at the beginning of vcrlical retrace. The display horizontal task is awakcned oncc at the beginning of each ficld, and thereafter whenever thc display word task blocks. ~~~~~r can block itself, in which case neither it nor the word task can bc awakened until the start of the ncxt ficld. l 'he wakcup request for the display word task (I)wI') is controlled by thc state of the 16 word buffer. If DW'r has not executed a u r . o c ~ , if D I ~ is not blockcd, and if thc buffer is not full, 11wr wakcups arc generated. 'I'he hardwarc scts the buffer empty and clears the uwr block flip-flop at the beginning of horizontal retrace for every scan line.

4.3 Display Controller Microcode

'I'lic display controller microcode is divided into three tasks. 'I'hc highcst priority task is DVT, thc display vcrtical task, the ncxt is I)IIT, the horizontal task, and the third is Ilwr, the display word task. 'I'he display controller ilscs 6 registers in R:

CRA: llolds the address of thc currently activc I I C B + ~ . AIXI ,: IIolds the address of the end of the currently active scan linc's bit map in main

memory. S1.C: Ilolds the numbcr of scan lines rcliiaining in tlic currently activc IICII. I 1 . r ~ ~ : Ilolds the nit~nber of tab words remaining on the currcnt scan line. IIWA llolds tile address of the bit map doubleword tun-ently being fetchcd for

transmission to the hardware buffer. M'U:MI': Is a temporary cell.

'I'lic vcrtical task initializes tlic controller by setting SLC to 0 and ~ B A to DAS'~AICI '+~. It also merges the contcnts of I , A S ~ A I U ' + ~ into NWW, which will cause an intcrrilpt if the specified channel is activc. Dvr also scts up info1.1nation rcqi~ircd for the cursor (see below), TASKS and becomes inactive until the next ficld.

I I IH starts by initiating a fetch to the word addrcsscd by CIIA. It checks SIG, and if it is zero, tlic conll~ollcr is linislicd with tlic currcnt IlCl3, and tlic link word of the DC'l3 is fetched. If Lliis word is non- zero, it rcplaccs CXA and processing of a new 1)co is begun. If the link word is zcro, uln' blocks until the start of the ncxt ficld.

If the check of sr,c indicates that more scan lines remain in the current Dcr,, SI,C is decrcnlcntcd by one and the fctcli of ( ~ 1 3 ~ ) is used to obtain the second word of tlic Ixn, ratlicr than the link word. 'The contents of this word arc used to set thc display modc and polarity, and the tab count is extracted and piit into I I ~ I ' A I ~ . N W R I ~ S is extracted, and used to increment DWA and Ar:cI, by the appropriatc amount, depending on tlic modc and ficld. All the rcgistcrs required by 1)w.r have now bccn set up, and 111n' 'I'ASKs and becomes inactive illitil DWI' blocks.

Alto 1-iartlwnrc Manual Scction 4: 1)isplay Controllcr 34

If a ncw IICII is rcquircd, IIIIT fctchcs all four words of the ncw DCII, and iliitializcs all tllc rcgistcrs. Iluring all scan lincs of a IICB cxccpt thc first, u ~ i r only accesses tlic first doublcword of thc block.

rlwr has tlic sole task of transferring words from memory to the hardwarc. Whcn it first awakens during horizontal rctracc, it chccks IITAB. If it is non-zero, it enters a loop which outputs I i l 'AIl 0's to tllc display. Whcn In'A13 is zcro, a second loop is entcrcd which fctchcs a doublcword from the localion spccificd by nwA. I,WA is compared with AECL, and if they arc cqual, DWl' blocks until the next scan linc. 1)WA is incrcmcntcd by 2, in prcparation for thc fctch of thc llcxt doublcword. If DWAf AECL, DWI' continues to supply words to the buffer whcncvcr it bccomcs non-full.

4.4 Cursor

13ecausc of thc difficulty of inscrting a cursor at the appropriatc place in tlic display bit map at rcasonablc spccd, a hardwarc cursor is included in thc Alto. 'I'hc cursor consists of an arbitrary 16x16 bit patch, which is mcrgcd with the video at the appropriatc tirnc. l'hc bit map for the cursor is containcd in 16 words starting at locatiotl C~li~h1'(43113) in pagc onc, and the x,y coordinatcs of the cursor arc spccificd by location C~JI<I ,OC (42611) and c'ul<r,oc+ 1 (42713) in pagc 1. 'I'lic coordinatc origin for thc cursor is thc uppcr lcft 11:tnd corncr of thc screen. 'Ihc cursor presentation is unaffcctcd by changes in display rcsolution. Its polarity is that of thc currcnt 1>c13, or thc last L)CB proccsscd if it is locatcd 011 an arca of thc scrccn not dcfined by a IICI~. 'I'he cursor may bc rcmovcd Gom vicw in a numbcr of ways. 'I'he most cfficicnt in tcrins of processing timc is to set the x coordinate to -1.

'I'hc cursor Iiardwarc consists of a 16-bit shift registcr which holds the information to bc displayed on the currcnt scan linc, and a countcr which is incrcmented by the bit clock, and dctcnnincs thc x coordinatc at which ~11e shift rcgister bcgins shifting.

'Ihc hardwarc is loaded during horizontal rctracc by the cursor task microcodc, whicli simply copics thc x coordinntc and bit map scgmcnt from the R niclnory into the hardware.

'Ihc valucs of x and tlic bit map arc sct up in R by a scction of thc mclnory rcfrcsli task, wliosc wakcup and priorily arc arranged so that it runs during cvcry scan line aftcr 1)wr has done all ncccssary output and 1)11'r has sct up thc information rcquircd by D W ~ for tlic next scan linc. MI^ cliccks tl-le cun'cnt y posilion of thc display, and if it is in tlic rangc in which thc cursor sliould be displaycd, fctchcs tlic appropriatc bit map scgmcnt fsom CUI<MAI>. Whcn thc cursor y position is cxcccdcd by the display, a flag is sct in M1i.l' to disi~blc further proccssing. l'hc x and y coordinatcs of the cursor arc fctclicd from cu111,oc and cuai,oc+l at thc beginning of each display ficld by a scction of tlic display vcrlical task microcode.

Cursor proccssing is distributed as it is to minimize thc amount of proccssing whicli must bc donc during lhc monitor's horizontal rctracc timc. 'I'his timc is approximately 6 microseconds, and it must includc the worst cast latcncy imposcd by tasks at lowcr priosity than the display, plus thc worst casc disk word proccssi~lg limc (thc disk word task is at highcr priority than tllc display), plus thc time ncccssary for I)WT to ~xirlinlly fi l l lhc display buffcr, plus cursor processing timc.

Alto Processor Bus

Figure 5 - - Display Control

I 6

-

Bit map address I I I I I C I I I I I I I

I I I

I I

16-word

Buffer

Pointer to next DCB

Scan Lines I I I I I I I I I I I I -_I--

Resol

Cursor , Shift Register

-

DkGnd

1 -word Buffer

I

Horizontal Tab

+ ! I I I

-

I I

I I

Words per Scan Line I I I I I I I I -

Display Shift Register

Digital Video \ , Mixer >

-

Bit Clock

Control - / x

Buffer

r

Sync Generator

Sync >