vme

VMEbus is a computer architecture. The term VME stands for Vgsj MtodulejEmocaffd andwas first coined in 1981 by the group of manufacturers who defined itTTFhis group wascomposed of people from Motorola, Mostek and Signetics corporations who werecooperating to define the standard. The term "bus" is a generic term describing a computerdata path, hence the name VMEbus.

VMEbus grew out of ae older standard called VERS Abus which was defined by MotorolaCorporation in 1979 for its 68000 microprocessor. While it is still used today? it has notachieved the wide acceptance that VMEbus has* VERS Abus initially competed with otherblisses including Multibus™, IBM-PC™, SIB bus, S-100, Q-bus and many others.

The microcomputer bus industry began with the advent of the microprocessor, and in 1981many busses were showing their age. Most worked well with only one or two types ofmicroprocessors, had a small addressing range and were rather slow. The VMEbusarchitects were charged with defining a new bus that would be microprocessorindependent^ easily upgraded from 16 to 32-bit microprocessors, implement a reliablemechanical standard^ and allow independent vendors to build compatible products* Noproprietary rights were assigned to the new bus which helped stimulate third party productdevelopment. Anyone can make VMEbus products without royalty fees or licensing*

Since much work was already done on VERSAbus it was used as a framework for the newbus. In addition^ §LI2££32^ chosen*Eurocard is a term which loosely describes a family of products based around the DIN41612 and EC 603-2 connector standards, and the DIN 41494 and IEC 297-3 rackstandards. When VMEbus was first developed, the Eurocard format had been wellestablished in Europe for several years. A large body of mechanical hardware such as cardcages? connectors and sub-racks were readily available. The pin and socket connector

Chapter 1 - Introduction to VMEbus 1 The VMEbus Handbook

scheme is more resilient to mechanical wear than older printed circuit board edgeconnectors. The marriage of the VERSAbus electrical specification and the Eurocardformat resulted in VMEbus Revision A.

The VMEbus specification has since been refined through revisions B9 C, C.1, DEC 821and IEEE 1014-1987. The DEC and IEEE standards are important because it makes it apublicly defined specification. Since no proprietary rights are assigned to it, vendors andusers need not worry that their products will become obsolete at the whim of any singlemanufacturer.

Since its introduction VMEbus has generated thousands of products and attracted hundredsof manufacturers of boards, mechanical hardware, software, and bus interface chips. Itcontinues to grow and support diverse applications such as industrial controls,telecommunications, office automation and instrumentation systems.

1.1 Why Use A Microcomputer Bes?

When developing a system there are three solutions an integrator can choose from: beild itfrom scratchy convert a standard computer or use microcomputer boards. The choice isaffected by time to market^ cost, volume, technology s compatibility and sometimes the "wedon't do hardware" mentality. Figure 1-1 shows these trade-offs.

The full custom system is the costliest in terms of development time and money. Its mainadvantage is that it can be exactly tailored to an application and can be cheaply produced inhigh volumes. It also might be the only choice if no other solution exists. Full custommight be a poor choice if a simple machine control had to be built in six weeks, but itwould probably be the right choice if thousands of units needed to be built, and a year ortwo were available for product development.

Figure 1-1. System integration trade-offs*

Adapting a standard mini or microcomputer is the most cost effective in modest volumes9Valuable product development resources would be wasted if a standard system could be

Chapter 1 - Introduction to VMEbus The VMEbus Handbook

adapted to the application* The major drawbacks of this approach are inflexibility and highunit cost. If special functions^ I/O or mechanical packaging are needed, the standardsystem might be too inflexible. For example, a personal computer can be adapted toperform bench top data acquisitioe, but might not be able to handle a sophisticated controlapplication.

Integration with microcomputer boards is a compromise between custom and standardsystems. They can be pieced together with available parts and minimum tooling costs*Generally they are used for small and moderate volume applications where 1-1000 units arebuilt. In many cases it can be done by people with little or no background in electronics.

Another advantage to microcomputer boards is flexibility. At the onset of productdevelopment the requirements of the computer system are only generally known. As aproject progresses more of the application becomes obvious, and the computer architecturemust adjust accordingly. This is especially true of first generation products. As theproduct becomes more refined so can the computer architecture* In many cases themicrocomputer bus is the most flexible because standard boards can be substituted in thesystem.

1.2 Why ¥MEbus?

Once it is decided to use a microcomputer bus, the choice of which one to use must bemade. There are a wide variety of buses available, with new ones introduced regularly 9Table 1-1 shows a comparison between VMEbus and some other popular buses. Thechoice depends on application, and is affected (again) by time to market, cost, volume,technology f compatibility and the "we donft do hardware11 mentality.

1.2.1 Features

A few VMEbus features are listed in Table 1-2. VMEbus has a 32-bit address bus (up to 4gigabytes of memory), a 32-bit data bus? performs multiprocessing and it can smoothlyhandle seven interrupt levels. Both the address and data busses can be dynamicallyconfigured (they change size automatically). This allows system expansion asmicrocomputer technology grows. It also handles data transfers at speeds in excess of 40Mbytes/second.

VMEbus uses a master-slave, architecture. Functional modules called masters transfer datato and from modules called slaves.- Since many masters can reside on the bus it is called amultiprocessing bus* Before a master cae transfer data it must first acquire the bus using acentral arbiter. This arbiter is part of a module called the system controller. Itfs function isto determine which master gets the next access to the bus. Seven levels of interrupts arealso supported.

All bus activity is perfomed by the four sub-busses shown in Figure 1-2. Data transferstake place over the Data Transfer Bus, and arbitotion by the Data Transfer Arbitration Bus.If interrupts are used these are handled by the Priority Interrupt Bus. A fourth, called theUtility Busf carries generic signals like a 16 Mhz dock and power-up reset.

1 - Introduction to VMEbus 3 . The VMEbus Handbook

1.2.1.1 Backplanes

VMEbes modules are connected together by backplanes which can have between 2 and 21slots. One or two backplanes may be used depending upon the system configuration* APl/Jl backplane handles 24 address bits, 16 data bits, some power/ground and all controlsignals. A second backplane called the P2/J2 can be used to expand capability to 32address and 32 data bits. It also adds more power/ground and includes some user definedpins. The two backplanes may be mounted separately or as a single unit depending uponthe style selected. Figure 1-3 shows a 12 slot combination (monolithic) Pl/Jl and P2/J2backplane mounted in a sub-rack (the Pl/Jl portion of the backplane is at the top).

VMEbus modules are located on 0.8" centers in the backplane*

1.2.1.2 Styles of Bus Modules

Two styles of VMEbus boards called single and double height modules can be used* Thesmallest is the single height module^ and connects to the Pl/Jl backplane. These cangenerate or accept 16/24 bit addresses and 8/16 bit data transfers. They are commonly usedif space is limited or if only a small amount of circuitry is used. In addition they are moreresilient to vibration than the double height board. Figure 1-4 shows a single heightmodule.

The larger and more popular size board is the double height module. These are electricallycompatible with single height modules since they use the same set of Pl/Jl address, dataand control signals. Unlike the single height module they can be expanded (optionally) touse up to 32 bits of address and data. Modules that do 32 bit address or data ttansfers mustbe double height modules. Figure 1-5 shows a double height module.

Single and double height boards are sometimes referred to as 3U and 6U modules. Somemanufacturers also offer triple height (9U) modules which use three DIN 41612connectors. While these are not VMEbus compatible they are supported by most Eurocardpackaging systems. Proprietary busses which require a third DIN 41612 connector willoften use the VMEbus definition on the PI and P2 connectors, and define their own bus onP3. This was done in the VXIbus specification* Standard VMEbus modules can then beadapted to the proprietary bus with 3U/6U/9U card cages or adapter modules like thatshown in Figure 1-6.

The use of two backplanes has proven to be one of the biggest features of VMEbus becauseit allows two card sizes. Many users require a smaller card because of size or vibrationconstraints* This allows VMEbus to compete against smaller boards such as STD bus.For example the size and vibration resilience of single height modules make them popularin the aerospace industry. Double height modules allow it to compete effectively againstbusses with larger form factors such as Multibus II™.

VMEbus is asynchronous and non-multiplexed Because it is asynchronous no clocks areused to coordinate data transfers. Data is passed between modules using interlockedhandshaking signals where cycle speed is set by the slowest module participating in thecycle.


Figure 1-2= Functional block diagram of VMEbus.

Chapter 1 - Introduction tc VMEbas 6 : YMEbus Handbook

Table 1-2. VMEbus Features

Item

Architecture

Transfer mechanism

Addressing range

Bate path width

Unalgneddatotransfer support

Error detection

Data transfer rate

Interrupt levels

Multiprocessingcapability

System diagnosticcapability

Mechanical standard

International standards

Specification

Master/slave

Asynchronous,non-multiplexed

16-Wt (short I/O)24-bit (standard)32-bit (extended)

8§ 16, 24 or 32-Wt

Yes

Yes

0-40 Mbytes/second

7

1-21 processors

Yes

Single heightDouble height

Yes

Notes

No central clock used

Address range selecteddynamically

Data path width selecteddynamically

Compatible with mostpopular microprocessors

Using BERR* (optional)

Priority interrupt systemwith vector return

Flexible bus arbitration

Using SYSFAIL* (optional)

160 X 100 mm eurocard160 X 233 mm eurocardDIN 603-2 connected

IEC 821, IEEE 1014


Figure 1-3. Sub-rack with 12 slot combination Pl/Jl and P2/J2 backplane. Photocourtesy Motorola Microcomputer Division.

Chapter 1 - Introduction to VMEbits The VMEbus Handbook

Figure 1-4. Single height (3U) module. Photo courtesy National Instraments.


Figure 1-5. Double height (6U) module. Photo courtesy Motorola MicrocomputerDivision.


Figure 1-6. 9U adapter with 6U bus module. This unit allows standard VMEbus modulesto be used with Sue 3 workstations. Photo courtesy of National Instalments.

The maximum speed of asynchronous busses is limited by the propagation delay of signalsacross backplanes and through buffer ICs, as Figure 1-7 shows. A VMEbus backplanecan be up to 500 mm (19.68") in length and can have relatively high inductive andcapacitive loads on the signal Graces. If this bus were synchronous it would probably havea system clock speed of around 10 Mhz. This would allow 100 nanoseconds for a signalto propagate from a module at one end of a bus, through an interface IC, across thebackplane, and through another interface IC to its destination. This is about as fast as asynchronous system could operate using 74LSXX IC technology* Asynchronous buseshave the same delays but they can take advantage of higher logic speeds as they becomeavailable. This allows bus bandwidth to increase as faster IC technology becomesavailable.

Chapter 1 - Introductionn to VM l i

Backplane

Figure 1-7. Signal propagation path in a microcomputer system.

1.2.1.3 Non-multiplexed Architecture

VMEbus is non-multiplexed. Figure 1-8 shows how multiplexed buses share the same setof pins for address and data lines* A two part bus cycle is required to transfer data. Duringthe first portion of the cycle an address is passed over the pins. Data is then moved duringthe second half of the cycle* This slows down bus cycles because extra time is required tomultiplex these two functions. Non-multiplexed busses have separate pins for bothaddress and data lines* Unfortunately this also means that more bus interface circuitry andsignal pins are required

Address Data

IAddress Data

JBes

Tranceiver

ii

BusTranceiver

BusTranceiver

i\

BusTraeceiver

i

i )

Common address & date Acicfresg Data

(a) Multiplexed bus Non-multiplexed bus

Figure 1-8. Multiplexed and non-multiplexed buses.

1.2.1 A Compatibility

Ae important part of a reliable bus architecture is vendor compatibility. This is an on-goingproblem in the microcomputer board industry because many modules are developed and


tested independently. Two boards will often be tested together only by the end user(sometimes with an embarrassing outcome for the board vendor). Due to the largenumbers of products it is impossible to verify every module, with all others. A busspecification has to be robust enough to insure that products developed independently (pastand future) will work together. When VMEbus was developed it was thought thatasynchronous architectures were more compatible than synchronous ones. Whether theyare or not has been the subject of an on-going controversy. The bus doesf however,provide reasonable compatibility. The sheer volume of independently developed VMEbesproducts has shown that this is true*

To further insure vendor compatibility a private company called VMElabs will test andcertify conformance to the VMEbus specification. If a bus module carries the VMElabsseal of approval it should be 100% bus compatible.

1.2.1.5 Bandwidth

Using its asynchronous, non-multiplexed architecture, VMEbes modules can achieve athroughput in excess of 40 Mbytes/second. Just as important, however, is its ability to letfast processors transfer data to peripherals of any speed. This allows users to tailor theirsystem to specific needs based on cost and availability.

1.2.2 Functional Modules

The VMEbus specification uses functional modules to describe its operation. A functionalmodule is a conceptual model used to describe each of the various parts of the bus. Theywere introduced to simplify its description and to provide a framework for itsunderstanding* They help to describe the interaction of the various parts of the bus. Figure1-2 shows them. Circuits on VMEbus modules may or may not be designed as modularfunctional modules. They are used only as a conceptual tool

1.2.2.1 Master

A master is a functional module that can initiate data transfer bus cycles. CPU modules andperipherals with DMA controllers are examples.

Masters drive the following signals (t optional):

AM0-AM5 DSO* LWORD*tIACK* DS1* A01-A31tWRITE* AS* D00-D31t

Masters monitor the following signals (f optional):

SYSRESET* ACFAIL*t DTACK*BCLR*t BERR* D00-D31t

1.2.2.2 Slave

Slave modules detect bus cycles generated by masters and participate in them if they areselected. Examples of slaves include memory and I/O modules.


Slaves drive the following signals (f optional):

DTACK* BERR*f DOO-DSlf

Slaves monitor the following signals (f optional):

SYSRESET* DS1* A01-A3itAM0-AM5* DSO* D0G-D31fIACK* AS*t WRTIE^LWORD*

1.2.2.3 Location Monitor

The location monitor watches the bus and asserts an on-board signal if certain addresses areselected. It allows messages to be broadcast to all modules.

The location monitor uses the following signals (f optional):

LWORD* DS1* A01-A31tAM0-AM5* DSO* AS*tIACK* WRITE*

1.2.2.4 Bus Timer

The bus timer measures how long each data transfer takes. If it takes too long it assertsBERR* to terminate the cycle. It is used to prevent lockups due to memory sizing orsystem failures, and is usually located on the slot 01 system controller module.

Bus timers monitor the following signals (t optional):

DS1* DSO* DTACK*f

1.2.2.5 Interrupter

An interrupter generates interrupt requests to an interrupt handler (another functionalmodule). During an interrupt acknowledge cycle the interrupter passes a STATUS/IDword (8,16 or 32 bits) to the interrupt handler. Because they respond to these cycles theyare a type of slave. Interrupters are sometimes called interrupt requesters. An example ofan interrupter would be a serial I/O module that requests an interrupt every time it receives acharacter.

Intemipters drive the following signals (f optional):

IRQ1*-IRQ7* BOG^BSlfBERR*f IACKOUT*

Chapter 1 - Introduction to VMEbus 14 ' The VMEbes Handbook

Interrupters monitor the following signals (f optional):

DSO* DSl*t LWORDfAS* WRTTE*t A01^A03IACKIN* IACK*t SYSRESET*

1.2.2.6 Handler

An interrupt handler responds to requests from interrupters. These modules must becapable of obtaining the data transfer bus? generating an Interrupt acknowledge cycle andreading a STATUS/ID word from the Interrupter. Interrupt handlers are commonly foundon CPU modules.

Interrupt handlers drive the following signals (t optional):

DSl*t LWORD*fAS* WRHE*f AQl ACBIACK*

Interrupt handlers monitor the following signals (f optional):

BERR* D00-D31t DTACK*SYSRESET* IRQX^MQY*

1.2.2.7 IACK* Daisy-chain Driver

During an interrupt acknowledge cycle the IACK daisy chain driver starts the IACK* daisychain. It Insures that only one Interrupter will respond with a STATUS/ID word, andprovides the correct timing for the daisy chain. It resides on slot 01 system controller.

The IACK* daisy chain driver only drives IACKOUT*. It monitors the following signals(t optional):

DS1* DSO* AS*IACK*f IACKIN*

1.2.2.8 Requester

Bus masters and Interrupt handlers use a requester to obtain the data transfer bus* Therequester uses the data transfer arbitration bus to handshake with the arbiter. The arbitergrants the bus to the requester, which allows the master to use the bus. The requester issometimes called a bus requester.

Requesters drive the following signals (f are optional):

BRQ* - BR3* (only one) BBSY*BG0OUT* - BG3OUT*

Chapter 1 - Introduction to VMEbus 15 The ¥MEbus Handbook

Requesters monitor the following signals (f are optional):

The arbiter monitors bus requests (from requesters) and grants control of the data transferbus, one master at a time.

The bus arbiter drives the following signals (t are optional):

BGOOUT* - BG3OUT* (one or more)BCLR*f

The bus arbiter monitors the following signals (t are optional):

BRO* - BR3* (one or more)BBSY* SYSEESET*

1.2.2.10 System Clock Driver

The system clock driver provides a stable 16 Mhz utility clock (SYSCLK) to all the busmodules. Because VMEbus is asynchronous this dock has no relationship to other bustiming.

1.2.2.11 Serial Clock Driver

The serial clock driver generates SERCLK (used by VMSbus). The frequency ofSERCLK depends upon the length of VMSbus. Although this functional module isdescribed by lie VMEbus specification it is defined by the VMSbes specification.

1.2.2.12 Power Monitor

The power monitor is respoesible for generating system reset and monitoring the system'sAC power source. The power monitor asserts SYSRESET* and ACFADL*.

1.23 Sub-busses

The VMEbus specification groups all of the bus signals into four sub-busses. Figure 1-2showed the relationship of these busses to the various functional modules.

L2.3.1 Data Transfer Bus

The data transfer bus is used by masters to move binary data between themselves andslaves. It is also used by interrupt handlers to fetch a STATUS/ID from interrupters duringan interrupt acknowledge cycle.This bus is composed of address lines, data lines andcontrol signals. The following signals are included in the Data Transfer Bus:

Chapter 1 - Intextocion to VMEbus 16 - The VMEbus Handbook

AddressA01-A31AM0-AM5DSO*DS1*LWORD*

DataD00-D31

ControlAS*DSO*DS1*BERR*DTACK*WRITE*

1.2.3.2 Data Transfer Arbitration Bus

VMGbus systems can have multiple masters and interrupt handlers* The data transferarbitration bus guarantees that only one master or interrupt handler can acquire the datattansfer bus at any time. Signals used by the Data Transfer Arbitetion Bus include:

BRO* BGOIN* BGOOUT* BBSY*BR1* BG1IN* BG1OUT* BCLR*BR2* BG2IN* BG2OUT*BR3* BG3IN* BG3OUT*

1.23.3 Priority Interrupt Bus

Interrupters send interrupt requests to interrupt handlers over the priority interrupt bus* Upto seven levels of intemipts can be used. This bus uses the following signals:

IRQl*IRQ2*IRQ3*IRQ4*

IRQ5*IRQ6*IRQ7*

IACK*IACKIN*IACKOUT*

The data transfer and data transfer arbitration buses are used during interrupt acknowledgecycles.

Bus

The utility bus is a collection of signals used for system reset, periodic timing, systemdiagnostics and power failures. Signals of the utility bus include:

SYSCLK* SYSRESET* SYSFAIL* ACFAIL*

L2o4 Data Transfer Cycles

VMEbus offers four types of data transfer bus cycles. This variety of cycles allow the busto adapt to the changing requirements of the system.


1.2.4.1 Read/write Cycle

Read/write cycles are used to transfer 8, 16, 24 or 32 bits of data between masters andslaves. The cycle begins when the master broadcasts an address and an address modifier.Slaves capture the address and respond to the cycle (if they are selected).

1.2.4.2 Read-modify-write Cycle

The read-modify-write cycle permits indivisible bus cycles. This cycle is especially usefulfor arbitrating shared resources in multiprocessor or multiuser systems with semaphores.

1.2.43 Block Transfer Cycle

The block transfer cycle moves a block of data between masters and slaves. Read or writeblock transfer cycles up to 256 bytes in length are permissible. This cycle is faster thanREAD/WRITE cycles because slaves are addressed only once (at the beginning of thecycle). It is especially useful for quickly moving large blocks of data.

1.2 A A Address-only Cycle

During the address-only cycle a master will generate a valid address but slaves will notrespond (the data strobes are never asserted). It allows slaves to decode an address at thesame time that a masters on-board memory doesf and speeds up the system.

1.2.5 Interrupt Acknowledge Cycle

The interrupt acknowledge cycle is initiated by interrupt handlers in response to aninterrupt. This cycle performs two functions. It passes a STATUS/ID byte (vector) andarbitrates the interrupt sources.

1.2.6 Arbitration Cycle

An arbitration cycle is performed during bus arbitration. It begins when a requestergenerates a bus request to the central arbiter. The arbiter grants the bus to the requesterwhen the bus is not busy, and the requester acquires the bus by asserting the bus busysignal (BBSY*). The requester releases the bus by negating bus busy.

1.2.7 Signal Summary

Table 1-3 shows pin assignments for the Pl/Jl and P2/J2. backplanes* The Pl/Jlbackplane carries 24 address lines, 16 data lines, all control signals and some of the powerand ground traces. The P2/J2 connector carries the extra eight address and 16 data lines,with additional power and ground pins. All of the defined P2/J2 signals are located on thecenter row of pins. The outer two rows of that connector axe user defined, and can be usedfor any purpose. In general these axe used for I/O signals or for a side bus such asVMXbus, VSBbus or VXIbus.


i l i | S ^ transition o fg j |the signal.

Each VMEbes signal faEs into one of five classes, of electrical specification These classesare called standard three-state, high current three state, standard totem»pole9 high currenttotem-pole and open collector sigeals^ Chapter 6 describes the characteristics of theseclasses in detail

1.2.7.1 A01^A31

The address bus A01-A31 is driven by masters and interrupt handlers. During data ttansfercycles they are used to broadcast short I/O (16 bit), standard (24 bit) or extended (32 bit)addresses. During these bus cycles the number of valid address lines is broadcast using theaddress modifier code AMQ-AM5.

During inteixupt acknowledge cycles interrupt handlers use AQ1-AG3 to broadcast the levelof inteixupt being acknowledged.

A01-A31 are standard three-state class signals*

1.2.7.2 ACFAIL*

The AC power failure signal ACFADL* is driven by the power monitor module. Whenasserted it signals to all modules that the system power source is about to stop. It is notused in all VMEbus systems. ACFAIL* is an open-collector class signal

Chapter 1 - Introduction to vM&ons 19 The VMHbus Handbook

Table 1-3. VMEbes pin assignments*.

Pl/Jl

Kn Number

12345678

910111213141516

1718192021222324

2526272829303132

Row A

DOGD01D02DOSD04DOSD06D07

GNDSYSCLKGNDDS1*DSO*WRITE*GNDDTACK*

GNDAS*GNDIACK*IACKIN*IACKOUT*AM4A07

A06A05A04A03A02A01-12VDC+5VDC

RowB

BBSY*BCLR*ACFAIL*BGOM*BGOOUT*BG1IN*BG1OUT*BG2IN*

BG2OUT*BG3IN*BG3OUT*BRO*BR1*BR2*BR3*AMO

AMIAM2AM3GNDSERCLK8ERDAT*GNDIRQ7*

IRQ6*IRQ5*IRQ4*IRQ3*IRQ2*IRQ1*+5VSTDBY+ 5VDC

RowC

D08D09D10DllD12D13D14D15

GNDSYSFAIL*BERR*SYSRESET*LWORD*AM5A23A22

A21A20A19A18A17A16A15A14

A13A12AllA10A09A08-t-12 VDC+5 VDC

1.2.7.3 AM0-AM5

The address modifier code AM0-AM5 is driven by masters. It accompanies an address andindicates both the size and type of address transfer. It is used by slaves to determine whichaddress lines should be decoded AM0-AM5 are standard three-state class signals.

Chapter 1 - Introduction to VMEbus 20 bus Handbook

Table 1-3 (con't).

P2/J2

Pin Number

12345678

910111213141516

1718192021222324

252627282930 .3132

Row A

User DefinedUser DefinedUser DefinedUser DefinedUser DefinedUser DefinedUser DefinedUser Defined



UserBeleedUser DefinedUserBeleedUser DefinedUser DefinedUser DefinedUser DefinedUser Defined

RowB

+5VBCGNDRESERVEDA24A25A26A27A28

A29A30A31GNB+5VDCD16D17D18

D19D20D21D22D23GNDD24D25

D26D27D28D29D30D31GND+5VBC

RowC





L2.7.4

Address strobe AS* Is driven by masters and interrupt handlers. When it is asserted ifindicates that a valid address and address modifier have been placed onto the bus. Thesignal also qualifies other signals such as LACK*. AS* is a high current three-state signal


1.2.7.5 BBSY*

Bus busy BBS Y* is driven by masters and interrupt handlers when they are using the bus.The arbiter monitors this signal to determine when it should grant the bus to another masteror interrupt handler. BBS Y* is an open-collector class signal

1.2.7.6 BCLR*

Bus clear BCLR* is driven by the bus arbiter. When asserted it informs the current masteror interrupt handler that another module is requesting the bus. The conditions under whichit is asserted depend upon the arbitration method being esed (see Chapter 3). BCLR* is ahigh ceront totem»pole class signal.

1.2.7.7 BERR*

Bus error BERR* is driven by slave or bes timer modules. A slave asserts it if an error hasoccurred during the bus cycle. The bus timer asserts it when the bus has locked-up.BERR* is an open-collector class signal.

1.2.7.8 BGQIN*^BG3IN* / BG0OUT*-BG3OUT*

The signals BGQIN* - BG3IN* and BG0OUT*-BG3OUT* are part of the bus grant daisychain and are driven by arbiters and bus requesters. The slot 01 arbiter asserts a bus grantin response to a bos request on the same level (BRO* - BR3*)* The bes grant daisy chainwill start at the slot 01 system controller and propagate from module to module until therequester that initially needed the bus receives it. Each VMEbus module has a bus grantinput and a bus grant output. They are standard totem-pole class signals.

1.2.7.9 BG0IN*-BG3IN*

BGOIN* - BG3IN* are part of the bus grant daisy chain. Each VMEbus module has anincoming BGXIN* signal and an outgoing BGXOUT*. The arbiter in the slot 01 cardposition monitors bus request signals BR0*-BR3* and grants the bus by assertingBG0OUT*-BG3OUT*.

1.2.7.10 BR0*-BR3*

Bus requests BR0*-BR3* are asserted by a requester whenever its master or interrupthandler needs the bus. Before accepting the bus the master must wait until the arbitergrants the bus by way of the bus grant daisy chain BG0IN*-BG3IN*o BRO* - BR3* areopen-collector class signals.

1.2.7.11 D00-D31

Data bus D00-D31 is driven by masters, slaves or interrupters. These are bi-directionalsignals and are used for data teasferSo Different portions of the data bus are eseddepending upon the state of.DSO*, DS1*, A01 and LWORD*. BOO - D31 are standardthree-state signals.

Chapter 1 - Introduction to YMEbes 22 The VMBbus Handbook

1.2.7.12 DSO*-DS1*

Data strobes BSD* and DS1* axe driven by masters and interrupt handlers and serve twopurposes. When combined with LWGRJD* and A01 they indicate the size and type of datatransfer. They also indicate valid data on the data bus during a write cycle9 and infomi aslave that it should place data onto the data bus during a read cycle. DSO* - DS1* are highcurrent three-state class signals.

1.2.7.13 DTACK*

Data transfer acknowledge DTACK* is driven by slaves or interrupters. During a writecycle DTACK* is asserted after the slave has latched the data on the data bus. During aread cycle or interrupt acknowledge cycle DTACK* is asserted after valid data is placedonto the data bus. DTACK* is an open-collector class signal.

1.2.7.14 GND

Ground GND is used both as a signal reference and a power return path.

1.2.7.15 IACK*

Interrupt acknowledge IACK* is driven by interrupt handlers in response to interruptrequests. It is connected to IACKIN* at slot 01 (on the backplane) to start propagation ofthe interrupt acknowledge daisy chain. IACK* can be either an open-collector or astandard three-state class signal.

1.2.7.16 IACKIN*4ACK0UT*

The interrupt acknowledge daisy chain IACKIN* - IACKOUT* is driven by the IACKdaisy chain.driver. They are used both to indicate that an interrupt acknowledge cycle is inprogress and to determine which interrupters should return a STATUS/ID. They arestandard totem-pole class signals,

1.2.7.17 IRQ1*-IRQ7*

Priority interrupt requests IRQ1*-IRQ7* are asserted by intemipters. Level seven is thehighest priority and level one the lowest. They are open-collector class signals.

1.2.7.18 LWORD*

Long word LWORD* is driven by masters. It is used in conjunction with A01, DSO* andDS1* to indicate the size of the current data-transfer. LWORD* is a standard three-stateclass signal.

Chapter I - Introduction to VMEbus 23 The VMEbus Handbook

1.2.7.19 RESERVED

The signal marked RESERVED is saved for future use. It should not be used for anypurpose.

1.2.7.20 SERCLK-SERDAT*

The serial clock (SERCLK) and serial data (SEEDAT*) signals are used for VMSbes.VMSbus is a serial bus used as an alternate data path between bus separate bus modules orsebracks.

1.2.7.21 SYSCLK

16 Mhz utility clock SYSCLK is driven by the slot 01 system controller. This clock can beused for any purpose and has no timing relationship to other VMEbus signals. SYSCLK*is a high current totem-pole class signal.

1.2.7.22 SYSFAIL*

System fail SYSFAIL* can be asserted or monitored by any module and indicates that afailure has occurred in the system. The cause and the response to the failure is userdefined, and its use is optional S YSFAEL* is an open-collector class signal

1.2.7.23 SYSRESET*

System reset SYSRESET* can be driven by any module and indicates that a reset (such aspower-up) is in. progress. SYSRESET* is an open-collector class signal

1.2.7.24 WRITE*

WRITE*, the read/write signal, is driven by masters and indicates the direction of datatransfer over the bus* It is asserted during a write cycle and negated during a read.WRITE* is a standard three-state class signal

1.2.7.25 +5 STDBY

+5 STDBY is the +5 VDC standby power supply. Its use is optional

1.2.7.26 +5 VDC, +12 VDC, 42 VDC

Three system power supplies are used. These are +5 VDC? +12 VDC and 42 VDC.

Chapter 1 - Introduction f© VMEbus 24 The VMEbus Handbook

Data Transfers

VMEbus data is transferred using a sub-bus called the Data Transfer Bus* Masters use thissub-bus to transfer data to and from slaves9 and interrapters use it to pass STATUS/IDwords to handlers. Modules with location monitors can also monitor this sub-bus lookingfor specific types of bus cycles aed interrupt an on-board processor in response. The DataTransfer Bus is asynchronous and non-multiplexed.

2.1 Bus Cycles

The Data Transfer Bus allows several types of bus cycles. These include the read/write,block transfer, read-modify-write and address-only cycles. Chapter 4 covers an additionalcycle called the interrapt acknowledge cycle. Not ail bus modules are compatible with alltypes of bus cycles. When evaluating or designing VMEbes modules, be sere that slavesare compatible with the cycles generated by the masters. For example^ a master maygenerate a read-modify-write cycle9 but not all slaves respond to it

2.1.1 Read/Write Cycle

Of all the cycle types, the read/write cycle is the most common. It is used to pass databetween a master and a slave 8,16,24 or 32 bits at a time.

Chapter 2 - Data Transfers 40 The VMEbus Handbook

2.1.1.1 Addressing

Slave addressing takes place during every read/write cycle. This is done with address linesA01-A31, a six bit address modifier code AMQ-AM5, and two control signals IACK* andLWORD*. All of these signals are qualified by the falling edge of address strobe AS*. Inaddition, the two data strobes BSD* and DSl* determine which byte location within a fourbyte group data should be read or written to, and provide the information usually given bythe missing address line A00.

2.1.1.2 Address Sizing

Three sizes of address can be used as Table 2-1 shows. These are called short I/O,standard, and extended addressing modes9 and correspond to lengths of 16, 24 and 32 bits.The size can be changed on every bus cycle which allows a wide variety of systemconfigurations. Its most obvious advantage is to enable older microprocessors to share thebus with newer ones. For example, a CPU module with a 68GGG microprocessor capableof generating 24-bit addresses may share the bus with a 32 bit 68020.

Table 2-1. Dynamic address widths.

Address ModifierType

Short I/O

Stuncfeffd

Extended

AddressBits

16

24

32

ActiveAddress Lines

AOl - A15

AOl - A23

AOl - A31

Mnemonic

A16

A24

A32

2.1.1.3 Address Modifier Code

The number of address lines that are decoded by slaves is given by the six bit addressmodifier code AMQ-AM5. This code accompanies each address, with their meaningsshown in Table 2»2* During a bus cycle the slave will monitor the address modifier, andthen determine which address lines to decode. Short I/O addresses are decoded from A01-A15, standard addresses from A01»A23t and extended from A01-A31. All slave modulesdo not respond to all address modifier codes.

Chapter 2 - Data Transfers The VMEbus Handbook

Table 2-2. Address modifier codes.

AddressModifier(Hex)

3F3E3D3B3A39

2D29

IFIEIDICIB1A1918

1716151413121110OF0EODOBOA09

XX

IACK*

111111

11

11111111

11111111111111

0

No.Address

Bits

242424242424

1616

——

——-

———

—-

323232323232

3

Transfer Type

Standard Supervisory Block TransferStandard Supervisory Program AccessStandard Supervisory Data AccessStandard Non-Privileged Block TransferStandard Non-Privileged Program AccessStandard Noe»Wvileged Data Access

Short Supervisory AccessShort Non-Privileged Access



Extended Supervisory Block TransferExtended Supervisory Program AccessExtended Supervisory Data AccessExtended Noe-Privileged Block TransferExtended Non-Privileged Program AccessExtended Noe-Privileged Data Access

Interrupt Acknowledge Cycle (uses A01-A03)

Note: All codes other than those shown are reserved for future use.Don't care state = (XX), Undefined = (-).

Besides address size, the address modifier also shows the type of bus cycle. Itdiscriminates between instruction fetches, data read/write cycles, block ttansfer cycles andwhether the cycle is generated by user or non-privileged (supervisory) programs.

The function of the IACK* signal can be associated with the address modifier codes.IACK* is asserted by interrupt Handlers to show that the current cycle is an interruptacknowledge cycle, and negated by masters to show that it is a data transfer cycle. When


evaluating or designing slave modules IACK* can be treated like a seventh addressmodifier bit. When IACK* is asserted, AM0-AM5 can be ignored by slaves.

The address modifier is an important tool With it, VMEbus modules can be as simple oras complex as the application requires. Slaves, such as a serial I/O modules, require onlyseveral bytes of address space and can use short I/O addressing. This reduces part countby decreasing the number of comparators and control logic. This is important to lower thecost of the interface as well as to conserve board space. More complex boards such asmemory or graphic controllers require standard or extended addresses because of their largememory requirements.

The address modifier also makes single (3U) and double height (6U) modules compatible,Since single height modules ese the PI connector they can monitor only A01-A23. Thislimits these modules to the short I/O and standard cycles. Double height modules,however^ can monitor an additional eight address lines on the P2 connector, and canperform 32 bit address transfers. Without the address modifier the simple P2 expansionbus would be awkward.

2.1.1.4 Mnemonics

To help select compatible modules, a series of mnemonics have been developed whichclassify the addressing modes shown in Table 2»3* A16, A24 and A32 mnemonicscorrespond to the number of address lines used in a transfer. For example an A16 si we,will respond to bus cycles generated by an A16 master.

The IEEE-1014-87 VMEbus specification requires that A32 masters generate A24 and AUcycles. Similarly A24 masters must also generate A16 cyclese Slaves do not have anysuch requirements. Earlier versions of the bus specification did not make h i

When selecting master modules make sure that they will generate all the cycles < ocfMiiPd bythe slaves (this is not guaranteed by the VMEbus specification).

2.1.1.5 Typical Read/Write Cycle

During a typical read/write cycle a master addresses a slave (described above)transfers data. The data is transferred using D00-O31, WRITE*, dataacknowledge (DTACK*) and bus error (BERR*). The data lines and the WRITE* si,are qualified using data strobes DSO* and

The timing waveform for a read cycle is shown in Figure 2-1. Here a master addresses aslave by driving A01-A31, AM0-AM5, IACK* and LWORD*. These are qualified by thefalling edge of AS*. The master also negates WRITE* and asserts data strobes DSO*and/or DSl*e The slave decodes the address^ places data onto D00-D31 and asserts datatransfer acknowledge DTACK*. When the master has latched the data, it informs theslave by negating the data strobe(s). The slave then negates DTACK* and the cycle isterminated

Chapter 2 - Data Transfers 43 The- VMFbus Handbook

Table 2-3. Mnemonics describing the various addressing modes.

Mnemonic

A16

A24

A32

Description

Generates (master) or accepts (slave, location monitor)bus cycles with short I/O (16-bit) addresses*

Generates (master) or accepts (slave, location monitor)bus cycles with standard (24-bit) addresses. A24 mastersmust also be A16 compatible,,

Generates (master) or accepts (slave, location monitor)bus cycles with extended (32-bit) addresses* A32 mastersmust also be A16 and A24 compatible.

Figure 2-1. Read cycle with address pipelining.

A write cycle is similar to a read cycle as Figure 2-2 shows. The main difference is thatdata is placed onto the data lines before the data strobes are asserted Once the slave assertsBTACK* or BERR*, the master can negate WRITE* and change the data lines. For thisreason a slave must latch the data before it asserts BTACK*.

2.1.1.6 Data Strobes

The data strobes BSO* and BS1* serve a dual functionselect which bytes are accessed As an edge sensitive

a level sensitive signal theyare used to qualify data.

Chapter 2 - Data Transfers 44 •bus Handbook

Figure 2-2. Write cycle with address pipelining.

The VMEbus specification does not use the terms DSQ* and DS1* in its timing diagrams.Instead it refers to DSA* and DSB*» This notation was introduced to prevent confusion incases where bus skew (propagation delay) causes one data strobe to fall before the other.Propagation delay times through buffers at the master may also cause these signals to besent at slightly different times.

2.1.1.7 Cycle Termination

Slaves terminate all bus cycles by asserting DTACK* or BERR*. DTACK* is the normalway to end the cycle* During read cycles the slave asserts DTACK* after driving the databus, and during write cycles the slave asserts it after it has latched the data.

BERR* can be asserted by a slave or a bus timer. When it is asserted by a slave it indicatesthat an error has occurred during the cycle. The VMEbus specification does not say whatmay have caused the error. For example^ a memory module can assert BERR* when aparity error occurs. The bus timer asserts BERR* if the bus has locked up, sometimescaused by a data strobe which has been stuck low for a long period of time.

VMEbus uses a fully interlocked handshaking mechanism with data strobes DSG* andDS1*9 DTACK* and BERR*9 At the beginning of a cycle a master must not assert eitherdata strobe until DTACK* and BERR* (from the last bus cycle) have been negated*Failing to do so may cause data to be corrupted on the current or the previous cycle. The680XX microprocessors don't do this and external circuitry must be provided on CPUboards to make them compliant.

2.1.1.8 Address Pipelining

Some microprocessors use address pipelining to speed up data transfers. Simply stated,the bus master will broadcast the address of the next bus cycle before the current cycle is


completed. As Figures 2-1 and 2-2 showed^ once the slave acknowledges the data transfer(by asserting BTACK*) the master negates AS*, places a new address oe the bus, and thenasserts AS* again. By overlapping the address broadcast with the previous cycle, bustransfers can be speeded up significantly. Slaves must be designed to function properly Inthe presence of an address pipelining cycle.

The removal of a valid address before DTACK* or BERR* are negated is sometimes calledaddress rot Similarly, changing the data lines after DTACK* or BERR* Is asserted duringa write cycle Is called data rot.

When designing or evaluating slave ieterfacesf be sure they latch all addresses and addressmodifiers before asserting DTACK* or BERR*. The address Is often latched on the fallingedge of either data strobe. Failing to do so may cause the slave to change Its data linesbefore the end of a read cycle because its on-board address has changed. During a writecycle the slave's Internal timing may be disrupted.

When evaluating or designing slaves that do not utilize address pipelining (all slaves mestfunction properly In the presence of these cycles), care should be taken when latching theaddress on the falling edge of AS*. On read cycles, AS* can be negated and re-assertedImmediately after they assert DTACK* or BERR*. If the address Is latched on the fallingedge of AS*, the slave could be presented with a new address before It negates DTACK*or BERR*, and corrupt the data. On slaves which do not implicitly participate in addresspipelining cyclesf It Is better to latch the addresses on the falling edge of either data strobe.Often the the data strobes are forfed together and used to latch the addresses.

When evaluating or designing modules that support block transfer cycles (discussedbelow), special care should be taken to Insure that address pipelining will work. Duringthe block transfer cycle the master may change A01-A31 and LWORD* after the firstfalling edge of DTACK*. The address modifier code AM0-AM5 must remain stable untilthe last falling edge of DTACK* In the block transfer cycle.

Address pipelining is conceptually related to the early BBSY* release mechanism (seeChapter 3 on Multiprocessing). During bus arbitration, a new master can assumeownership of the data transfer bus after the current master negates address strobe AS**With address pipelining the new master can begin addressing a slave even before theprevious master has completed the data transfer cycle (signified by negating the datastrobes). This reduces the overhead necessary to change masters.

2.1.1.9 Data Sizing

Like the addresses, the data bus can be dynamically configured. Data transfers of 8? 16,24and 32 bits can be made, usually without any software overhead whatsoever. This makesVMEbus products compatible over wide ranges of technology, and offers the same benefitsthat dynamic address sizing does.

Data bus sizing Is achieved by splitting the data lines into four byte wide banks: D00-D07,BQ8-O15, D16-D23 and D24-D31. The individual banks are used depending upon the sizeof data transfer. The master signals the type and size of transfer by way of data strobesBSD* and DS1*, address line A01 and LWORD*. The slave then routes data to or fromthe coixect bank

VMEbus uses a B YTE(n) convention to specify how data Is stored in memory, where (n) Isthe address offset from an even 32-Mt boundary. Table 2=4 shows this convention*


Table 2-4 Data organization in memory.

QpOTttd

BYTE(0)BYTE(1)BYTE®BYTE(3)

Byte Address(Binary)

xxxx....xxooXXXX....XX01XXXX....XX10XXXX....XX11

X = Don't care

During a transfer the master asserts DS0*f DS1*, A01 and LWORD* depending eponwhere it expects to read or write data. The level of these signals and the associated datapaths are shown in Table 2-5.

VMEbus offers four styles of bus interface which adds to its flexibility. These options areclassified using the mnemonics D08(O), D08(EO), D16 and B32. As with dynamicaddress sizing, dynamic data sizing allows older technology to work with newer* Forexample, a CPU with a 68000 microprocessor (8 and 16 bit data path) can share VMEbuswith a 68020 based CPU (8,16,24 and 32 bit data path). The same is true for slaves.

The D08(O) slave can transfer data over D00-D07. It is called a D08(O) because transfersof eight bits can be made only at odd addresses (such as byte transfers at $XXXXXX01»$XXXXXXQ3). A typical example would be an 8-bit serial I/O port. D08(O) masters arenot specifically allowed under the VMEbus specification since these are simply a subset ofthe D08(EO) master.

The D08(EO) slave is slightly different from a D08(O) because a byte can be read from thismodule at even or odd addresses. Transfers to or from these modules must be done eightbits at a time, and only one data strobe may go low at any time. An example of a masterwith this interface would be a CPU module with an 8-bit processor such as a 68008. Aslave module could be an I/O board with an 8-bit RAM IC capable of transferring data ateven and odd addresses.

•-D31. These are mostThe D16 and D32 interfaces monitor or drivecommon among CPU or memory modules.

The DEEE-1014-87 version of the bus specification requires that D16 masters, slaves andlocation monitors include the D08(EO) capability. It also requires that D32 masters, slavesand location monitors include the D16 and D08(EO) capabilities. These were both optionalunder the Revision B, C, C.1 and EEC 821 versions of the bus specification.


The VMEbus specification does not allow slaves to acknowledge their port size during atransfer. Some popular microprocessors (like the 68020 and 68030) require their slaves todo so. A common way to interface these microprocessors is to memory map the port sizes.For example, a 32-bit CPU module may configure its bus interface as a D16 master duringbus access between $00000000 and $Q0FFFFFf\ and 32;bits between $01000000 and$01FFFFFFs In this way 16 bit and 32 bit modules can reside on the same bus.


Selection of a data port size may also be done with a mode bit. A mode bit is simply a bitthe CPU sets depending upon what type of access it requires. For instance, the bit couldbe set when the master generates a D32 cycle, and cleared for a B16® The advantage of thismethod is simplicity of design. The disadvantage is that the software may need to becontinually setting and clearing the bit if a mix of boards is used in the system.

2.1.1.10 Unaligned Data Transfers

Unaligned data transfers are allowed under the VMEbes specification. As Table 2-5shows9 a VMEbus module can place two and four bytes of data at other than two or fourbyte boundaries. These are called unaligned transfers* Unalgned transfers can speed up aVMEbus system by allowing 32 bits of data to be transferred at odd addresses in two buscycles instead of three.

When a master reads or writes data it can do so in a variety of ways. For example,consider case B of Figure 2-3. Here a four byte transfer takes place at an unalignedboundary. The master can transfer the data using one of two methods. Using the firstmethod the master transfers a Single Byte(l), a Double byte(2-3) and a Single Byte(0)oThis means that the whole transfer takes three bus cycles to complete* Using the secondmethod the master will do Unaligned Byte(l-3) and a Single Byte(0) transfer. This secondmethod takes only two bus cycles. Unaligned transfer can substantially reduce the numberof VMEbus cycles to ttansfer data.

Byte(0)

Figure 2-3* Four ways that 32-bits of data can be saved in memory.

The VMEbus specification does not stipulate the order in which data is transferredto or from memory. In the example above? the Single Byte(O) transfer could take placebefore or after the Unaligned Byte( 1 -3) transfer.

Figure 2-4 shows four ways that 16-bit words may be stored in memory.


Byte(3)

Figure 2-4 Four ways that 16-bits of data can be saved in memory.

A special mnemonic called UAT specifies whether an unaligned transfer can be generatedby a master, accepted by a slave or monitored by a location monitor*

The IEEE-1014-87 version of the bus specificatioii also requires that D32 slaves andlocation monitors must accept unaligned (UAT) data transfers, D32 masters are notrequired to generate these cycles, however. The UAT function was optional for slaves andlocation monitors under earlier versions of the bus specification.

Some software compilers can be set to generate code only on even boundaries. Thisreduces the number of unaligned transfers and therefore speeds up the system. Manycompilers with this feature will not prevent data transfers at enaligned boundaries, onlyinstructions.

2.1.2 Block Transfer Cycle

The block transfer cycle is used to speed up VMEbus data transfers. Blocks of data up to256 bytes in length are moved at high speeds across the bus. The block transfer cycle issometimes called burst mode* Few VMEbus modules support the block transfer cycle.

To understand what the block transfer cycle is used for, consider a CPU module fetchingprogram instructions* When instructions axe read they are fetched in ascending order. Forexample, if an instruction is read at address $100? it will probably read the next one at $101or $102. Some computers take advantage of this by "thinking ahead" and reading datafrom the next few bytes of memory while the CPU is busy with the current instruction.Circuits which do this are often called instruction prefetch or pipelining circuits. Specialdynamic memories^ called page mode and nibble mode memories, are often used tosimplify instruction prefetch. These memories can be placed into a high speed "dump"mode which allow fast burst transfers^ and are often double or triple the speed of normalmemories.

The block transfer cycle also improves the performance of multiprocessing systems. Hereit can be used to transfer data in small bursts, reducing the overhead of bus arbitration.

The block transfer cycle is also faster than read/write cycles because the master presents anaddress only once during the cycle. The extra overhead of computing and changingaddresses does not take place. An example of a block transfer cycle is shown in Figure 2-5,


Figure 2-5o Block transfer cycle (write).

During the cycle both an address and a block transfer address modifier is presented by themaster to the slave. Once the slave is addressed, multiple bytes of data can be read orwritten (in ascending order) by toggling the data strobes. Block transfer counters on theslave automatically increment their on»board addresses. This relieves the master fromcompeting and changing the address during every cycle.

To reduce the complexity of block transfer slavesf a rule was introduced in the revision CVMEbus specification which forbids block transfers from crossing 256 byte boundaries.This provision solved several problems that existed with the block transfer cycle. Itprevented board-to-board crossings during a cycle, it reduced the address counterrequirements to eight bits, and allowed the use of commonly available nibble or page modememories (many standard memories require that block transfers don't cross 256 byteboundaries). If it must cross the boundary the master can stop the cycle, re-submit a newaddress, and do another block transfer.

The 256 byte rale also prevents a master from hogging the bes with large numbers of buscycles. Since VMEbus arbitration cannot take place with AS* asserted (see Chapter 3) abus arbitration cannot occur in the middle of a block transfer cycle. This rale will allow atleast one arbitration to occur every 256 bes cycles.

The ability to generate or accept a block transfer cycle is optional To preventincompatibility between modules^ a mnemonic caled BLT is used. If a master can generatea block transfer cycle it is called a BLT master. If a slave can accept a block transfer cycleit is called a BLT slave. When integrating a VMEbus system make sure that compatiblemodules are used.

The BLT mnemonic is not to be confused with the bacon, lettuce and tomato cycle which isnot supported by VMEbus.

Chapter 2 - Data Transfers 51 Hie VMEbus Handbook

2olo3 Eead-Moilfy-Wrlte Cycle

The read-modify-write cycle is used in multiprocessor and multiuser systems. This specialcycle allows multiple processes to share common resources such as disk controllers, serialports or blocks of memory. As the name implies, the read-modify-write cycle will read andwrite data to a memory location using one bus cycle instead of two. This prevents acommon resource from being allocated to two processes because software flags arechecked and changed in one cycle.

The read-modify-write cycle is sometimes called an indivisible cycle or a test-and-set cycle.

A possible application for the test-and-set cycle would be an airline ticket reservationsystem. Consider the situation where two people (at different locations) reserve seats on aflight from New York to London. Without the read-modify-write cycle both people couldbe assigned the same seat if both reservations were made at exactly the same time* In thiscase two processes (ticket offices) could both acquire a single resource (airline seat).

For example, assume the ticket reservations software were set up so that each seat on thefight was represented by a bit in memory. If the bit is a zero the seat is empty s and if it's aone then it's reserved. To reserve a seat, the ticketing software would first read the bit tosee if the seat were occupied. If the bit is zero the software would set it to a one. If it thebit was already set (the seat was occupied), then the software would look for another seat.In 680XX assembly code it would look something like this:

* AO = LOCATION OF MEMORY BIT REPRESENTING SEAT*

BTST.B #7s(A0) * IS THE SEAT TAKEN?BEQ GETSEAT * BRANCH IF SO

GETSEAT: BSET.B #7,(A0) * RESERVE THE SEAT

The problem occurs between the time the bit is tested (BTST.B) and it is set (BSET.B)ODuring this time several instructions are perforaied, such as BEQ. In a multiprocessing ormultitasking system, a bus arbitration could take place between the time the bit is checkedand when it is set. If another processor were running the same codes at the same time, bothcoeld get the same seat because they both read the bit as zero. The outcome would be twopassengers booked on the same seat, an embarrassing problem for the airline.

This problem can be solved using the read-modify-write cycle. In the 680XX family, aCPU can generate this cycle using the TAS (test-and-set) instruction. This instructionreads a byte, tests the condition of bit #7, sets it to a one, and writes the byte back tomemory. Rewriting the program using TAS would look something iike this:

* AO = LOCATION OF MEMORY BIT REPRESENTING SEAT

TAS (AO) * TEST BIT AlBEQ GETSEAT * BRANCH IF AVAILABLE

(Chapter 2 - Baa Transfers 52 The VMEbus Handbook

GETSEAT:

The airline reservation example is rather simplistic bet does illustrate the use of the read-modify-write cycle. Many multiprocessing systems must contend for system resourcessuch as memory buffers and peripherals.

Not all VMEbes masters or slaves will participate in the read-modify-write ythat generate or accept the cycle are said to be RMW compatible (all modules must tolerateRMW cycles on the bosf however). When evaluating or designing bus modules, look atthe software requirements to determine if modules need to be RMW compatible.

The read-modify-write cycle is shown in the timing diagram of Figure 2=6. During thecycle9 back-to-back read, and write cycles are performed while AS* is asserted In the firsthalf of the cycle WRITE* is negated^ and data is read from memory. The master modifiesihe-data, asserts WRITE*, and puts the data back. Keeping AS* asserted prevents busarbitration from occurring in the middle of the cycle (see Chapter 3), and keeps more thanone processor from reading data*

Figure 2-6. The read-modify-write cycle.

When evaluating or designing VMEbes masters capable of read-modify-write cycles, makesure they do not change their address lines during the cycle. This can cause problems onprocessors such as the 68020 which utilizes a special RMC (Read»Modify-Control) pin.Under certain conditions the 68020 can change its address lines during the read-modify-write cycle. A possible solution is to latch the address lines of the microprocessor beforethe start of every cycle.

Problems can also happen on read-modify-write slaves. A common mistake is to use AS*to drive the slave's DTACK* generator. Once the slave has been selected, use the datastrobes DSO* and DS1* to assert and negate DTACK*a If this is not done, the modulecould generate DTACK* on the first (read) half of ihe read-modify-write cycle, and lockthe bus up on the second

Chapter 2 - Data Transfers 53 The YMEbus Handbook

The address-only cycle is used to broadcast an address. No data is transferred during thecycle. This cycle is differentiated from read/write cycles in that masters do not assert eitherdata strobe. Because the data strobes are not asserted, the slave does not terminate thecycle with DTACK* or BERR*. Figure 2-7 shows the cycle.

AMO - AM5A01-A31

JACK*, LWORD*

AS*

BSA*

Figure 2-7. Address-only cycle.

The address-only cycle allows a master's local memory address decoder to work in parallelwith a slave's, and can speed up the bus in some cases. It can also simplify the design ofsome masters. For example9 a 68010 MPU with 68451 MMU can terminate a bus cycleafter the 68451 asserts AS* (the MMU aborts the external cycled The bus interface designis simplified if these cycles are allowed to happen onto VMEbos.

The ADO mnemonic is used to describe modules that can initiate or tolerate address-onlycycles. When evaluating or designing slave modules, make sure they tolerate ADO cycles.The IEEE-1014-87 version of the VMEbus specification requires that all slaves do so.Modules designed under earlier specifications do not have to.

2@2 Circuit Example - Simple 8-bit Parallel I/O Module

While most boards in a system can be purchased through established vendors^ the needoften arises where the user must design and build at least one VMEbus module. These areusually specialized I/O modules that are customized to the application. Often the resourcesdedicated to these custom projects are larger than those given to the rest of the system.Several circuits (all have been built and tested) axe presented here to aide the user inunderstanding and designing simple VMEbus interface circuits.

Figure 2-8 shows a simple circuit for an 8-bit parallel I/O module with anA16:D32:D16:D08(O) interface. This module illustrates some basic slave interfacingconcepts including address decoding, bus timing and use of the control signals. It can beused as a building block for real time clocks-, A/D converters, D/A converters and othersimple I/O functions.

A write cycle to this board causes U7 to latch and output one byte of data. A read cyclewill return data present at the input of U6. The address modifiers and address lines aredecoded with an 8-bit magnitude comparator UL Since the board is an A16 module,address modifiers $29 and $2D must be decoded as Table 2-6 shows. Note that Ul doesnot monitor AM2. This bit is considered a don't care state which simplifies the circuit


Table 2-6. Address modifier codes for 8-bit I/O module.

$29 1 0 1 0 0 1$2D 1 0 1 1 0 I


A16 slaves only need to decode address bits A01-A15, and A16-A31 can be ignored. Bydecoding only the upper three address bits A13-A15 the circuit cae be built using one 8-bitcomparator IC. The only drawback to this is the 8 Kbytes of address space the medeietakes up. Since the A16 address space is usually reserved for simple I/O devices^ largeholes in memory can be tolerated.

The P=Q output of Ul is latched using flip-flop U3e This is because the address lines onVMEbus slaves must be latched at the beginning of every cycle. To understand why,consider the timing diagram of Figure 2-9. The timing roles of the VMEbus specificationrequire that slavesjoNosU)^ after the data strobe isasserted. Once the slave asserts DTACK*f however, the master may immediately negateAS* and change the address lines. If the address lines are not latched9 the module could bede-selected in the middle of the cycle. If this happened during a read cycle the modulecould torn off its data transceiver and conupt the data latched by a master*

Figure 2-9. Bus timing shows why slaves should latch address lines.

The 8-bit I/O module uses DSO* to latch the addresses instead of AS*. If a slave does notsupport address pipelining (it mest always tolerate those cycles), it may latch its addresslines using either of these* Using the falling edge of DSO* instead of AS* in this casesimplifies the design of the module.

The master may negate and then re-assert AS* immediately after DTACK* is asserted bythe slavef as Figure 2-9 shows. This is also known as address pipelining or address rot.If the address were latched on the falling edge of AS*f and a second falling edge occurredbefore the end of the cycle, it could cause the module to turn off its output driver during aread cycle. During a write cycle it could latch unwanted data.

Since the 8-bit I/O module is a D08(O) slave, data is written and read over DQG-DG7 (seeTable 2-5). This means that the module can be written to one byte at a time at oddaddresses, and that only DSO* need be used. By strict interpretation of the VMEbusspecification this circuit is actually a A16:B32:B16:BG8(G) slave because it does not decodeDS1* and LWORD*? and responds to D32 and D16 cycles. If the board is presented withD32 or D16 cycles it will still respond but will ignore all data lines other than D00-D07.For example, during read cycles the backplane termination networks pull all the data linesup, during write cycles unused data lines are ignored.

Input data is read from a 74F374 octal flip-flop (U6). This circuit was set up so it latchesdata at the falling edge of every data strobe, and holds it steady while the master reads it.Any metastable glitches at the output of U6 will damp out before the master latches the data

Chapter 2 - Data Transfers 57 Handbook

(from the delays on U2 and U8). Data Is held at the output of the device until the masternegates data strobe DSO*.

A write cycle is similar except that data is latched using octal flip-flop U7* Data is latchedbefore the module asserts DTACK* because the master is pennitted to change the datelinesimmediately after the slave asserts DTACK*,

When evaluating'or designing VMEbus modules, the driver and receiver characteristics ofthe interface ICs must be closely checked. For examplef the circuit of Figure 2-8 assertsDTACK* with a 74F38 open-collector driver. The data lines, however, are driven with a74F374 which has standard 3-state outputs. For more information on interfacecharacteristics see Chapter 6.

By strict interpretation of the diagrams in the VMEbus specification, this module shouldmonitor SYSRESET*. Since that signal would perform no useful function on the board, itwas not used. During system reset this module is required to negate DTACK*, and stopdriving data lines DQ0-DG7 within 30 microseconds after SYSRESET* is asserted Sincemasters are required to negate the data strobes after only 20 microseconds, and this circuitresets itself every time the data strobes are negated, the monitoring of SYSRESET* isuseless. For more information on system reset refer to Chapter 5.

23 Circuit Example - A simple 16-bit Memory Module

A 16-bit memory module with 16 Kbytes of memory is shown in Figure 240* This circuithas an A24:D16:D08(EO) interface. Address decoding is similar to that of the 8-bit parallelI/O module except that it responds to A24 addresses and decodes more bits.

Table 2-7 shows the address modifiers to which it responds. Since there are four of them,a programmable logic device (U6) is used as a decoder* The logic equations for this deviceare shown in Figure 2-11. U6 asserts /STAM if IACK* and LWORD* are both negated,and an A24 address.modifier is detected Flip-flop U4 then latches /STAM after the fallingedge of either data strobe (signal CYC).

The lower VMEbus addresses are latched by U10 and Ul 1 on the falling edge of either datastrobe. Address bits A16-A23 are compared to the base address select switch using Ul,whose output is latched with U4. Since it responds to A24 addresses it does not decodeaddress lines A24-A31 •

Those unfamiliar with programmable logic may wish to consult the tutorial given at the endof this chapter (MMI). The logic equations are not hard to understand though. Thosegiven in Figure 2-11 are written in PALASM™. Here the state of each output (on the leftside of the equal sign) is asserted or negated depending upon the state of the inputs (on theright side of the equal sign). The Boolean operators of AND (*), OR (+) and NOT (/) canbe-used in the equations. For example, the equation for the latching signal CYC is:

= DSO*DS1

Chapter 2-Data Transfers 58 The VMEbus Handbook

Table 2-7» Address modifier codes for 16-bit memory module.

M M M M M M5 4 3 2 1 0

$3E 1 1 1 1 1 0 Standard Supervisory Program$3D 1 1 1 1 0 1 Standard Supervisory Data$3A 1 1 1 0 1 0 Standard Non-Privileged Program$39 1 1 1 0 0 1 Standard Non-Privileged Data

This means that the output (CYC) will go low if the inputs (DS0 and DSl) are both high.Schematically it would be the same as the circuit of Figure 2-12.

Figure 2=12. Circuit which dees the same function asPLD equation /CYC = DS0 * DS1.

Because the PLD does not assert /STAM if LWORD* is asserted, the module will notrespond to D32 or to misaligned cycles (see Table 2-5). Only single and double byte cyclesare accepted. The byte locations that data is read from or written to is controlled by thelevel of data strobes DS0* and DS1*. These, plus the state of the WRITE* signal, areused to control /OE, WE0f WEI and BTACK*. The module will accept D16 as well asD08(EO) cycles.

Data is buffered to and from the memory ICs using 74LS645A-1 bus transceivers U13 andU14. These supply the 48 mA drive current required by the VMBbos specification.

The cycle time of the memory ICs is confrolled by delay line U5.

By strict interpretation of the diagrams in the VMEbus specification, this module shouldmonitor SYSRESET*. Since that signal would perform no useful function on the boards itwas not used. During system reset this module is required to negate DTACK* and stopdriving data lines DGG-B15 within 30 microseconds after SYSRESET* is asserted Sincemasters are required to negate the data strobes after only 20 microseconds, and this circuitresets itself every time the data strobes are negated, the monitoring of SYSRESET* isuseless. For more information on system reset refer to Chapter 5.


TITLE ADDRESS DECODER CONTROLPATTERN VH0004. PDSREVISION AAUTHOR WADE PETERSONCOMPANY CC) 1988 WADE PETERSON. ALL RIGHTS RESERVEDDATE JANUARY 29, 1988

CHIP DECODE PAL16L8

AL AM5 LST AM4 AMD AM3 IACK AMI LWORD 6NDOE BDS1 BDSO DSO DS1 BDSEL DTK CYC STAM VCC

EQUATIONS

; VJffiBUS CYCLE SELECT

/CYC = DSO * DS1

; BUFFERED DATA STROBES

/BDSO = DSO

/BDS1 = DS1

; BOARD SELECT

/BDSEL = /LST * /AL

/DTK = BDSEL

; STANDARD ADDRESS MODIFIER DECODE

/STAM = IACK * LWORD * AM5 * AM4 * AM3 * Mil * /AMO+ IACK * LWORD * AM5 * AM4 * AM3 * /AMI * AMD

Figure 2-11. Logic equations for U6 in Figure 2-10.

Chapter 2 - Data Transfers 62 Hie VMEbus Handbook