2

MSP430F2013: 2KB + 256B Flash Memory128B RAM

3

MSP430MSP ( mixed signal processor)

• The CPU is small and eficient, with a large number of registers.• It is extremely easy to put the device into a low-power mode.

No special instruction is needed: The mode is controlled by bits in the status register. The MSP430 is awakened by an interrupt and returns automatically to its low-power mode after handling the interrupt.

• There are several low-power modes, depending on how much of the device should remain active and how quickly it should return to full-speed operation.

• There is a wide choice of clocks. Typically, a low-frequency watch crystal runs continuously at 32 KHz and is used to wake the device periodically. The CPU is clocked by an internal, digitally controlled oscillator (DCO), which restarts in less than 1μs in the latest devices. Therefore the MSP430 can wake from a standby mode rapidly, perform its tasks, and return to a low-power mode.

4

MSP430

• •A wide range of peripherals is available, many of which can run autonomously without the CPU for most of the time.

• Many portable devices include liquid crystal displays, which the MSP430 can drive directly.

• Some MSP430 devices are classed as application-specific standard products (ASSPs) and contain specialized analog hardware for various types of measurement.

5

Παράδειγμα ζυγαριάς

6

MSP430 FEATURES• There is a wide choice of clocks. Typically, a low-frequency watch

crystal runs continuously at 32 KHz and is used to wake the device periodically. The CPU is clocked by an internal, digitally controlled oscillator (DCO), which restarts in less than 1μs in the latest devices. Therefore the MSP430 can wake from a standby mode rapidly, perform its tasks, and return to a low-power mode.

• A wide range of peripherals is available, many of which can run autonomously without the CPU for most of the time.

• Many portable devices include liquid crystal displays, which the MSP430 can drive directly.

• Some MSP430 devices are classed as application-specific standard products (ASSPs) and contain specialized analog hardware for various types of measurement.

7

MSP430F2013

8

MSP430F2013 και πηγές ρολογιών

10

SERVOS AND PWM

11

MSP430F2013

• VCC and VSS are the supply voltage and ground for the whole device (the analog and digital supplies are separate in the 16-pin package).

• P1.0–P1.7, P2.6, and P2.7 are for digital input and output, grouped into ports P1 and P2.• TACLK, TA0, and TA1 are associated with Timer_A; TACLK can be used as the clock input to the

timer, while TA0 and TA1 can be either inputs or outputs. These can be used on several pins because of the importance of the timer.

• A0-, A0+, and so on, up to A4±, are inputs to the analog-to-digital converter. It has four differential channels, each of which has negative and positive inputs.

• VREF is the reference voltage for the converter.• ACLK and SMCLK are outputs for the microcontroller’s clock signals. These can be used to supply a

clock to external components or for diagnostic purposes.• SCLK, SDO, and SCL are used for the universal serial interface, which• communicates with external devices using the serial peripheral interface (SPI) or inter-integrated

circuit (I2C) bus.• XIN and XOUT are the connections for a crystal, which can be used to provide an accurate, stable

clock frequency.• RST is an active low reset signal. Active low means that it remains high near VCC for normal

operation and is brought low near VSS to reset the chip. Alternative notations to show the active low nature are _RST and /RST.

• NMI is the nonmaskable interrupt input, which allows an external signal to interrupt the normal operation of the program.

• TCK, TMS, TCLK, TDI, TDO, and TEST form the full JTAG interface, used to program and debug the device.

• SBWTDIO and SBWTCK provide the Spy-Bi-Wire interface, an alternative to the usual JTAG connection that saves pins.

13

Τεχνικές λεπτομέρειες….• These devices have flash memory, 1KB in the F2003 or 2KB in the F2013, and128 bytes of RAM.• Six blocks are shown for peripheral functions (there are many more in largerdevices). All MSP430s include input/output ports, Timer_A, and a watchdog timer,although the details differ. The universal serial interface (USI) and sigma–deltaanalog-to-digital converter (SD16_A) are particular features of this device.• The brownout protection (διακοπή ρεύματος) comes into action if the supply voltage

drops to a dangerous level. Most devices include this but not some of the MSP430x1xx family.

• There are ground and power supply connections. Ground is labeled VSS and istaken to define 0V. The supply connection is VCC. For many years, the standardfor logic was VCC =+5V but most devices now work from lower voltages and arange of 1.8–3.6V is speci.ed for the F2013. The performance of the devicedepends on VCC. For example, it is unable to program the .ash memory ifVCC < 2.2V and the maximum clock frequency of 16MHz is available only ifVCC ≥ 3.3V.

14

Clock Generator

• A fast clock to drive the CPU, which can be started and stopped rapidly to conserve

energy but usually need not be particularly accurate.

• A slow clock that runs continuously to monitor real time, which must therefore use little power and may need to be accurate.

15

Clock Generator

• An integrated high-speed digitally controlled oscillator (DCO) can source the master clock (MCLK) used by the CPU and high-speed peripherals. By design, the DCO is active and stable in less than 2 µs at 1 Mhz.

• MSP430-based solutions effectively use the high-performance 16-bit RISC

• CPU in very short bursts.

16

Clock Generator

• Crystal: Accurate (the frequency is close to what it says on the can, typically within 1 part in 105) and stable (does not change greatly with time or temperature). Crystals for microcontrollers typically run at either a high frequency of a few MHz to drive the main bus or a low frequency of 32,768 Hz for a real-time clock. The disadvantages are that crystals are expensive and delicate, the oscillator draws a relatively large current, particularly at high frequency, and the crystal is an extra component and may need two capacitors as well. Crystal oscillators also take a long time to start up and stabilize,often around 105 cycles, which is an unavoidable side effect of their high stability.

• Resistor and capacitor (RC): Cheap and quick to start but used to have poor accuracy and stability. The components can be external but are now more likely to be integrated within the MCU. The quality of integrated RC oscillators has improved dramatically in recent years and the F20xx provides four frequencies calibrated at the factory towithin ±1%.

17

Clock System

• Master clock, MCLK is used by the CPU and a few peripherals.

• Sub-system master clock, SMCLK is distributed to peripherals.

• •Auxiliary clock, ACLK is also distributed to peripherals.

18

Clock System

19

Clock System

• Low- or high-frequency crystal oscillator, LFXT1: Available in all devices. It isusually used with a low-frequency watch crystal (32 KHz) but can also run with ahigh-frequency crystal (typically a few MHz) in most devices. An external clock signalcan be used instead of a crystal if it is important to synchronize the MSP430 with other devices in the system.

• High-frequency crystal oscillator, XT2: Similar to LFXT1 except that it is restrictedto high frequencies. It is available in only a few devices and LFXT1 (or VLO) is usedinstead if XT2 is missing.

• Internal very low-power, low-frequency oscillator, VLO: Available in only the more recent MSP430F2xx devices. It provides an alternative to LFXT1 when the accuracy of a crystal is not needed.

• Digitally controlled oscillator, DCO: Available in all devices and one of the highlights of the MSP430. It is basically a highly controllable RC oscillator that starts in less than 1 s in newer devices.

20

Clock System

• ACLK comes from a low-frequency crystal oscillator at 32 KHz. There is no choice in almost all devices, the exceptions being those with a VLO.

• Both MCLK and SMCLK are supplied by the DCO with a frequency of around 1 MHz. This is stabilized by the FLL where present. You may wish to raise this frequency provided that VCC is high enough to support it.

21

EZ-430

• ACLK δεν είναι συνδεδεμένο σε κρύσταλλο 32 kHz στο ΕΖ430

22

Μετρητές (Timers) του MSP430F2013

• 1. Watchdog timer. Η κύρια λειτουργία του watchdog καταχωρητή είναι στο να προφυλάσσει το σύστημα από ανεπιθύμητη λειτουργία με το να το επαναφέρει μετά από καθορισμένο χρόνο. Μπορεί να χρησιμοποιηθεί και ως μετρητής χρονικών διαστημάτων, αν η προηγούμενη λειτουργία του δεν είναι επιθυμητή.

• 2. Timer_A. Τυπικά ο καταχωρητής αυτός έχει τρία κανάλια, μπορεί να χειριστεί εξωτερικές εισόδους να μετρήσει συχνότητα και να οδηγήσει εξόδους σε καθορισμένους χρόνους είτε μία φορά είτε περιοδικά. Επειδή έχει εσωτερικές συνδέσεις με άλλα τμήματα του ολοκληρωμένου μπορούμε να τον χρησιμοποιήσουμε για να μετρήσουμε τη διάρκεια ενός σήματος από το ένα τμήμα στο άλλο για παράδειγμα. Μπορεί επίσης να παράγει διακοπές (interrupts).

23

Timer A

24

Timer A• Timer_A clock source select, TASSELx: There are four options for the clock: the• internal SMCLK or ACLK or two external sources.We use SMCLK because it is• always available, which needs TASSELx = 10.• Input divider, IDx: The frequency of the clock can be divided before it is applied to the• timer, which extends the period of the counter.We use the maximum factor of eight,• which needs IDx = 11.• Mode control, MCx: The timer has four modes. By default it is off to save power.We• .rst use the simplest Continuous mode, in which TAR simply counts up through its full• range of 0x0000–0xFFFF and repeats. This needs MCx = 10.• Timer_A clear, TACLR: Setting this bit clears the counter, the divider, and the• direction of the count (it can go both up and down in up/down mode). The bit is• automatically cleared by the timer after use. It is usually a good idea to clear the counter• whenever the timer is recon.gured to ensure that the .rst period has the expected• duration.• Timer_A interrupt enable, TAIE: Setting this bit enables interrupts when TAIFG• becomes set.We do not use this.• Timer_A interrupt .ag, TAIFG: This bit can be modi.ed by the timer itself or by a• program. It is raised (set) by the timer when the counter becomes 0. In continuous mode• this happens when the value in TAR rolls over from 0xFFFF to 0x0000. An interrupt is• also requested if TAIE has been set. The program must clear TAIFG so that the next• over.ow can be distinguished.

25

Timer A• Timer block: The core, based on the 16-bit register TAR. There is a choice

of sources for the clock, whose frequency can be divided down (prescaled). The timer block has no output but a flag TAIFG is raised when the counter returns to 0.

• Capture/compare channels: In which most events occur, each of which is based on a register TACCRn. They all work in the same way with the important exception of TACCR0. Each channel can

– Capture an input, which means recording the “time” (the value in TAR) at which the input changes in TACCRn; the input can be either external or internal from another peripheral or software.

– Compare the current value of TAR with the value stored in TACCRn and update an output when they match; the output can again be either external or internal.

– Request an interrupt by setting its flag TACCRn CCIFG on either of these events; this can be done even if no output signal is produced.

– Sample an input at a compare event; this special feature is particularly useful ifTimer_A is used for serial communication in a device that lacks a dedicatedinterface.

26

Timer A• The number of channels is sometimes appended

to the name as in Timer_A3.• Capture/compare channel 0 is special in two

ways. Its register TACCR0 is taken over for the modulus value in Up and Up/Down modes, so that it is no longer available for its usual functions. It also has its own interrupt vector with a higher priority than the other interrupts from Timer_A, which all share a common vector. Therefore channel 0 should be chosen for the most urgent tasks if it is free.

27

Timer A

28

Timer A

29

Timer_A Counting ModesThe timer has four modes of operation, selected with the MCx bits:• Stop (MC = 0): The timer is halted. All registers, including TAR, retain their

values so that the timer can be restarted later where it left off.• Continuous (2): The counter runs freely through its full range from 0x0000

to 0xFFFF, at which point it over.ows and rolls over back to 0. The period is 216 = 65,536 counts. This mode is most convenient for capturing inputs and is also used when channels provide outputs with different frequencies or that are not periodic at all.

• Up (1): The counter counts from 0 up to the value in TACCR0, the capture/compare register for channel 0. It returns to 0 on the next clock transition. The period is (TACCR0+1) counts. For example, if TACCR0 = 4, the sequence of counts is 0, 1, 2,3, 4, 0, 1, . . . with period 5. Up mode is usually used when all channels provide outputs at the same frequency, often for pulse-width modulation.

• Up/Down (3): The counter counts from 0 up to TACCR0, then down again to 0 and repeats. The period is 2ΧTACCR0 counts. For example, if TACCR0=3, the sequence of counts is 0, 1, 2, 3, 2, 1, 0, 1, . . . with period 6. This is a specialized mode, typically used for centered pulse-width modulation.

30

Timer_A Counting Modes

0FFFFh

0h

CCR0

Stop/Halt Mode

Timer is halted with the next +CLK

UP Mode

Timer counts between 0 and CCR0

0FFFFh

0h

CCR0

UP/DOWN Mode

Continuous Mode

0FFFFh

0h

Continuous Mode

Timer continuously counts up

UP/DOWN Mode

Timer counts between 0 and CCR0 and 0

31

Timer_A 16-bit Counter

Stop Mode Up ModeContinuous ModeUp/Down Mode

0 00 11 01 1

CLRDividerInput

SelectInput unused un-

usedTAIFGTAIE

015

160h

TACTL

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

(w)-(0)

ControlMode

1/2 1/4 1/8

1/1, Pass0 00 11 01 1

0 00 11 01 1

ACLK MCLK

INCLK

TACLK

MC0MC1

ID1 ID0

SSEL0SSEL1

32

Timer_A 16-bit Control Register

33

Timer_A 16-bit Control Register

• Three items are given for each bit:• Its position in the word, which should not be needed • Its name, which is defined in the header file and should

be known to the debugger;• some bits are not used, which I show by a gray fill.• The accessibility and initial condition of the bit; here they

can all be read and written with the exception of TACLR, where the missing r indicates that there is no meaningful value to read. The (0) shows that each bit is cleared after a power-on reset (POR).

34

Timer A

• The flag TAIFG in TACTL is set when the timer counts to 0 and a maskable interrupt is requested if the TAIE bit is set. The family user’s guide always shows count in italics to emphasize that actions such as setting TAIFG occur only as a result of normal counting. They do not occur if the appropriate value is written directly to a register. For example, setting TACLR clears TAR but does not set TAIFG.

35

0

162h

CCTLx

rw-

15

un-SCS OUTMODx

(0)rw-(0)

CAPINPUTSELECT

CAPTUREMODE

rrw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

CCIFGCOVOUTCCICCIE

16Ehto

rw-(0)

SCCI used

015CCRx

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

rw-(0)

02

152

0172hto017Eh

to Port0

15 0

Capture/Compare Register CCRx

Comparator x

Overflow xLogic Data Bus Timer Bus

015

EQUxCAPx

0

COVx

Capture

DisabledPos. EdgeNeg. EdgeBoth Edges1 1

010 10 0

CCMx1 CCMx0

CMPx

TimerClock

1

0

SCSx

CCISx0

23

CCISx1

01CCIxB

VCCGND

CCIxA

CCIx

Capture Path

Compare Path Set_CCIFGx1

SCCIxENA Y

SynchronizeCapture

CaptureMode

Timer_A Capture Compare Blocks

36

Capture/Compare Channels• The central feature of each channel is its capture

/compare register TACCRn• In Capture mode this stores the “time”—the value in TAR

—at which an event occurs on the input; • In Compare mode it specifies the time at which the

output should next be changed and an interrupt requested. The mode is selected with the CAP bit. This is cleared by default so that the channel is in Compare mode. Any mixture of capture and compare channels can be used and the mode can be switched freely from one to the other.

40

Interrupts from Timer_A

411 1 1 PWM Set/Reset EQUx resets Outx signal, set with EQU0, clock synchronous with timer clock

0

0 0

OMx1 OMx0OMx2

0

0

0

0

Set

PWM Toggle/Reset

PWM Set/Reset

1

1

1

1

1

0

0

1

0

1

1

0

0

1 Reset

PWM Toggle/Reset

Output Mode

Toggle

Outx signal is set according to Outx bit

EQUx sets Outx signal clock synchronous with timer clock

EQUx toggles Outx signal, reset with EQU0, clock sync. with timer clock

EQUx sets Outx signal, reset with EQU0, clock synchronous with timer clock

EQUx toggles Outx signal, clock synchronous with timer clock

EQUx resets Outx signal clock synchronous with timer clock

EQUx toggles Outx signal, set with EQU0, clock synchronous with timer clock

Function Operational Conditions

OUTx (CCTLx.2)

OMx2 OMx1 OMx0

EQUx

EQU0Set

Reset

D Q

OUTx

Timer Clock

POR

TAx

Output Mode 0

Logic

OutputOutput Signal Outx

To Output Logic TAx

Timer Clock

Timer_A Output Units

43

Example shows three independent HW event captures. CCRx “stamps” time of event - Continuous-Mode is ideal.

0h

0FFFh

Capture Mode: Positive Edge

CCR1

CCR0

CCR1 CCR1

CCR0

TA0 Input

CCR1:

CCR1 CCR1

CCR2

TA1 Input

CCR0:

CCR2:TA2 Input

CCR1

Capture Mode: Both Edges

Capture Mode: Negative Edge

Interrupts can be generated

Px.x

Px.y

Px.z

Timer_A Continuous-Mode Example

44

Output Mode 4: PWM Toggle

Example shows three different asymmetric PWM-Timings generated with the Up-Mode

AutoRe-load

0FFFFh

0h

CCR0

CCR1

EQU0 EQU0EQU1 EQU1 EQU0

CCR2

TA1 Output

CCR2: PWM Reset/Set

EQU2 EQU2 EQU2


TA2 Output

CCR1: PWM Set/Reset

CCR0: PWM Toggle TA0 Output

Px.x

Px.y

Px.z

Timer_A PWM Up-Mode Example

45

Example shows Symmetric PWM Generation - Digital Motor Control

0FFFFh

0h

CCR0

TIMOV EQU0 TIMOV

CCR1

EQU0

CCR2


tpw2

tpw3

CCR3

pw1t

0 Degrees

+120 Degrees

-120 Degrees

TIMOV

hlfpert

(0.5xVmotor)

(0.93xVmotor)

(0.07xVmotor)

TA1 Output

TA2 Output

TA0 Output

Px.x

Px.y

Px.z

Timer_A PWM Up/Down Mode Example

46

C Examples, CCR0 Continuous mode ISR, TA_0 ISR

//***************************************************************

// MSP-FET430P140 Demo - Timer_A Toggle P1.0,

// CCR0 Contmode ISR, DCO SMCLK

// Description; Toggle P1.0 using software and TA_0 ISR. Toggle rate is

// set at 50000 DCO/SMCLK cycles. Default DCO frequency used for TACLK.

// Durring the TA_0 ISR P0.1 is toggled and 50000 clock cycles are added to

// CCR0. TA_0 ISR is triggered exactly 50000 cycles. CPU is normally off and

// used only durring TA_ISR.

// ACLK = n/a, MCLK = SMCLK = TACLK = DCO~ 800k

//

//

// MSP430F149

// ---------------

// /|\| XIN|-

// | | |

// --|RST XOUT|-

// | |

// | P1.0|-->LED

//

// M. Buccini

// Texas Instruments, Inc

// September 2003

// Built with IAR Embedded Workbench Version: 1.26B

// December 2003

// Updated for IAR Embedded Workbench Version: 2.21B

//**********************************************************************

#include <msp430x14x.h>

void main(void)

{

WDTCTL = WDTPW + WDTHOLD; // Stop WDT

P1DIR |= 0x01; // P1.0 output

CCTL0 = CCIE; // CCR0 interrupt enabled

CCR0 = 50000;

TACTL = TASSEL_2 + MC_2; // SMCLK, contmode

_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt

}

// Timer A0 interrupt service routine

interrupt[TIMERA0_VECTOR] void TimerA(void)

{

P1OUT ^= 0x01; // Toggle P1.0

CCR0 += 50000; // Add Offset to CCR0

}

47

C Examples, CCR1 Contmode ISR, TA_1//*****************************************************************

// MSP-FET430P140 Demo –

// Timer_A Toggle P1.0, CCR1 Contmode ISR, CO SMCLK

// Description; Toggle P1.0 using using software and TA_1 ISR.

// Toggle rate is set at 50000 DCO/SMCLK cycles.

// Default DCO frequency used for TACLK.

// Durring the TA_1 ISR P0.1 is toggled and

// 50000 clock cycles are added to CCR1.

// TA_1 ISR is triggered exactly 50000 cycles.

// CPU is normally off and used only durring TA_ISR.

// ACLK = n/a, MCLK = SMCLK = TACLK = DCO ~ 800k

// Proper use of TAIV interrupt vector generator demonstrated.

//

// MSP430F149

// ---------------

// /|\| XIN|-

// | | |

// --|RST XOUT|-

// | |

// | P1.0|-->LED

//

// M. Buccini


// September 2003


// December 2003


//**************************************************************


void main(void){ WDTCTL = WDTPW + WDTHOLD; // Stop WDT P1DIR |= 0x01; // P1.0 output CCTL1 = CCIE; // CCR1 interrupt enabled CCR1 = 50000; TACTL = TASSEL_2 + MC_2; // SMCLK, Contmode


}// Timer_A3 Interrupt Vector (TAIV) handler#pragma vector=TIMERA1_VECTOR__interrupt void Timer_A(void){ switch( TAIV ) { case 2: // CCR1 { P1OUT ^= 0x01; // Toggle P1.0 CCR1 += 50000; // Add Offset to CCR1 } break; case 4: break; // CCR2 not used case 10: break; // overflow not used }}

48

C Examples, PWM, TA1-2 upmode//***************************************************************************

// MSP-FET430P140 Demo - Timer_a PWM TA1-2 upmode, DCO SMCLK

//

// Description; This program will generate a two PWM outputs on P1.2/1.3 using

// Timer_A in an upmode. The value in CCR0, defines the period and the

// values in CCR1 and CCR2 the duty PWM cycles. Using ~ 800kHz SMCLK as TACLK,

// the timer period is ~ 640us with a 75% duty cycle on P1.2 and 25% on P1.3.

// ACLK = na, SMCLK = MCLK = TACLK = default DCO ~ 800kHz.

//

// MSP430F149

// -----------------

// /|\| XIN|-

// | | |

// --|RST XOUT|-

// | |

// | P1.2|--> CCR1 - 75% PWM

// | P1.3|--> CCR2 - 25% PWM

//

// M.Buccini


// September 2003


// January 2004


//*****************************************************

void main(void)

{


P1DIR |= 0x0C; // P1.2 and P1.3 output

P1SEL |= 0x0C; // P1.2 and P1.3 TA1/2 options

CCR0 = 512-1; // PWM Period

CCTL1 = OUTMOD_7; // CCR1 reset/set

CCR1 = 384; // CCR1 PWM duty cycle

CCTL2 = OUTMOD_7; // CCR2 reset/set

CCR2 = 128; // CCR2 PWM duty cycle

TACTL = TASSEL_2 + MC_1; // SMCLK, up mode

_BIS_SR(LPM0_bits); // Enter LPM0

}

49

C Examples, CCR0 Upmode ISR, TA_0//************************************************************************

// MSP-FET430P140 Demo - Timer_A Toggle P1.0, CCR0 upmode ISR, 32kHz ACLK

//

// Description; Toggle P1.0 using software and the TA_0 ISR. Timer_A is

// configured in an upmode, thus the the timer will overflow when TAR counts

// to CCR0. In this example, CCR0 is loaded with 1000-1.

// Toggle rate = 32768/(2*1000) = 16.384

// ACLK = TACLK = 32768, MCLK = SMCLK = DCO~ 800k

// //*An external watch crystal on XIN XOUT is required for ACLK*//

//

// MSP430F149

// ---------------

// /|\| XIN|-

// | | | 32kHz

// --|RST XOUT|-

// | |

// | P1.0|-->LED

//

// M. Buccini


// October 2003


// December 2003


//************************************************************************


void main(void)

{


P1DIR |= 0x01; // P1.0 output

CCTL0 = CCIE; // CCR0 interrupt enabled

CCR0 = 1000-1;

TACTL = TASSEL_1 + MC_1; // ACLK, upmode


}

// Timer A0 interrupt service routine

#pragma vector=TIMERA0_VECTOR

Interrupt[TIMERA0_VECTOR] void Timer_A (void)

{

P1OUT ^= 0x01; // Toggle P1.0

}

50

Simple PWM program (davies)• // simppwm1.c - Simple, slow PWM using Timer_A in Up mode from ACLK• // Period = 1s, LED1 at duty cycle D = 1/2, LED2 at D = 1/4• // Olimex 1121STK, LED1 on P2.3 = TA1, LED2 on P2.4 = TA2, active low• // J H Davies, 2007-07-17; IAR Kickstart version 3.42A• //----------------------------------------------------------------------• #include <io430x11x1.h> // Specific device• #include <intrinsics.h> // Intrinsic functions• //----------------------------------------------------------------------• void main (void)• {• WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer• // Configure ports 1 and 2; redirect P2.3,4 to Timer_A• P1OUT = BIT0 | BIT1; // Output high for Freq pin and TXD• P1DIR = BIT0 | BIT1;• P2SEL = BIT3 | BIT4; // Re-route P2.3 to TA1, P2.4 to TA2• P2DIR = BIT0 | BIT3 | BIT4 | BIT5; // Piezo and LED outputs• // Set up Timer_A for PWM on active low LEDs, channels 1 and 2• TACCR0 = 0x7FFF; // 1s period from 32KHz timer clock• TACCR1 = 0x4000; // Duty cycle D = 1/2• TACCR2 = 0x2000; // Duty cycle D = 1/4• TACCTL1 = OUTMOD_3; // Set/reset mode for negative PWM• TACCTL2 = OUTMOD_3; // Set/reset mode for negative PWM• // Start timer from ACLK, no division, Up mode, clear, no interrupts• TACTL = TASSEL_1 | ID_0 | MC_1 | TACLR;• for (;;) { // Loop forever• __low_power_mode_3(); // Remain in LPM3, CPU not needed!• } //

(nor are interrupts)• }

51

Automatic Control: Flashing a Light by PollingTimer_A

• The simplest way of generating a fixed delay with Timer_A is to wait for TAR to overflow. This is normally done by requesting an interrupt but we instead use polling.

52

8.5.3 Generation of a Precise Frequency (davies p.328)

• #define FREQUENCY 880 // Desired frequency of events• // Generally: f_timer = QUOTIENT * FREQUENCY +

REMAINDER• // or QUOTIENT = f_timer / FREQUENCY; REMAINDER =

f_timer % FREQUENCY• #define QUOTIENT 37 // values for 32KHz timer clock• #define REMAINDER 208• // ----------------------------------------------------------------------• #pragma vector = TIMERA1_VECTOR• __interrupt void TIMERA1_ISR (void) // Flag NOT cleared

automatically• {• static uint16_t shortfall = 0; // Accumulated (summed) shortfall• TACCTL1_bit.CCIFG = 0; // Acknowledge interrupt• P2OUT ˆ= (BIT0|BIT5); // Toggle piezo sounder• shortfall += REMAINDER; // Update accumulated shortfall• if (shortfall >= FREQUENCY) { // Over threshold for extra

count?• TACCR1 += (QUOTIENT + 1); // Yes: extra count in output

period• shortfall -= FREQUENCY; // Subtrct correction from shortfall• } else {• TACCR1 += QUOTIENT; // No: usual count• }• }

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LED Flashing by Polling Timer_A

• Listing 4.16: Program timrled1.c to Flash LEDs with a frequency of roughly 1Hz• by polling free-running Timer_A.• // timrled1.c - toggles LEDs with period of about 1.3s• // Poll free -running timer A with period of about 0.65s• // Timer clock is SMCLK divided by 8, continuous mode• // Olimex 1121STK , LED1 ,2 active low on P2.3,4• // J H Davies , 2006 -06 -12; IAR Kickstart version 3.41A• // ----------------------------------------------------------------------• #include <io430x11x1.h> // Specific device• // Pins for LEDs• #define LED1 BIT3• #define LED2 BIT4• void main (void)• {• WDTCTL = WDTPW|WDTHOLD; // Stop watchdog timer• P2OUT = ˜LED1; // Preload LED1 on , LED2 off• P2DIR = LED1|LED2; // Set pins for LED1 ,2 to output• TACTL = MC_2|ID_3|TASSEL_2|TACLR; // Set up and start Timer A• // Continuous up mode , divide clock by 8, clock from SMCLK , clear timer• for (;;) { // Loop forever• while (TACTL_bit.TAIFG == 0) { // Wait for overflow• } // doing nothing• TACTL_bit.TAIFG = 0; // Clear overflow flag• P2OUT ˆ= LED1|LED2; // Toggle LEDs• } // Back around infinite loop• }

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Output in the Up Mode: Edge-AlignedPulse-Width Modulation

55

PWM LED FLASH TA0

• TACCR0 = 0x3FFF; // (1/2)s period with 32KHz clock

• TACCTL0 = OUTMOD_4; // Toggle mode , no interrupts

• // Start timer from ACLK , no division , Up mode , clear , no interrupts

• TACTL = TASSEL_1 | ID_0 | MC_1 | TACLR;• for (;;) { // Loop forever• __low_power_mode_3 (); // Remain in LPM3 ,

CPU not needed• } // (nor are interrupts)

56

Edge-Aligned PWM

57

Edge-Aligned PWM

• Listing 8.14: Very slow pulse-width modulation at 1 Hz on an Olimex 1121STK in simppwm1.c. LED1 has duty cycle D1 = 1/2 and LED2 has D2 = 1/4 .

• // Set up Timer_A for PWM on active low LEDs , channels 1 and 2• TACCR0 = 0x7FFF; // 1s period from 32KHz timer clock• TACCR1 = 0x4000; // Duty cycle D = 1/2• TACCR2 = 0x2000; // Duty cycle D = 1/4• TACCTL1 = OUTMOD_3; // Set -reset mode for negative PWM• TACCTL2 = OUTMOD_3; // Set -reset mode for negative PWM• // Start timer from ACLK , no division , Up mode , clear , no

interrupts• TACTL = TASSEL_1 | ID_0 | MC_1 | TACLR;• for (;;) { // Loop forever• __low_power_mode_3 (); // Remain in LPM3 , CPU not needed• } // (nor are interrupts)

58

Led brightness

59

Led brightness

60

Flash led sw delay• // flashled.c - toggles LEDs with period of about 1s• // Software delay for() loop• // Olimex 1121STK, LED1,2 active low on P2.3,4• // J H Davies, 2006-06-03; IAR Kickstart version 3.41A• //----------------------------------------------------------------------• #include <msp430x11x1.h> // Specific device

• // Pins for LEDs• #define LED1 BIT3• #define LED2 BIT4• // Iterations of delay loop; reduce for simulation• #define DELAYLOOPS 50000

• void main (void)• {• volatile unsigned int LoopCtr; // Loop counter: volatile!

• WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer• P2OUT = ~LED1; // Preload LED1 on,

LED2 off• P2DIR = LED1|LED2; // Set pins with LED1,2 to output• for (;;) { // Loop forever• for (LoopCtr = 0; LoopCtr < DELAYLOOPS; ++LoopCtr) {• }

// Empty delay loop• P2OUT ^= LED1|LED2; // Toggle LEDs• }• }

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Flash led με timer Α(Χωρίς Interrupts)

• // timrled2.c - toggles LEDs with period of about 1.0s• // Poll timer A in Up mode with period of about 0.5s• // Timer clock is SMCLK divided by 8, up mode, period 50000• // Olimex 1121STK, LED1,2 active low on P2.3,4• // J H Davies, 2006-06-16; IAR Kickstart version 3.41A• //----------------------------------------------------------------------• #include <io430x11x1.h> // Specific device

• // Pins for LEDs• #define LED1 BIT3• #define LED2 BIT4

• void main (void)• {• WDTCTL = WDTPW|WDTHOLD; // Stop watchdog timer• P2OUT = ~LED1; // Preload LED1 on,

LED2 off• P2DIR = LED1|LED2; // Set pins for LED1,2 to

output• TACCR0 = 49999; //

Upper limit of count for TAR• TACTL = MC_1|ID_3|TASSEL_2|TACLR; // Set up and start Timer A• // "Up to CCR0" mode, divide clock by 8, clock from SMCLK, clear timer• for (;;) { // Loop

forever• while (TACTL_bit.TAIFG == 0) { // Wait for overflow• }

// doing nothing• TACTL_bit.TAIFG = 0; // Clear overflow flag• P2OUT ^= LED1|LED2; // Toggle LEDs• }

// Back around infinite loop• }

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Flash led με timer Α(Vissim Αυτόματη Παραγωγή κώδικα με Interrupts)

• /*** VisSim Automatic C Code Generator Version 7.0A14 ***/• /* Output for blink-f2013 at Mon Oct 27 22:28:04 2008 */

• #include "math.h"• #include "cgen.h"• #include <msp430x20x3.h>

• extern CGDOUBLE Zed;

• static __interrupt void cgMain();• static SIM_STATE tSim={0,0,0• ,0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0};• SIM_STATE *sim=&tSim;

• #pragma vector=TIMERA0_VECTOR

• static __interrupt void cgMain()• {• static int _squareCnt1=0;• if ((++_squareCnt1 > 500?(_squareCnt1>=1000?_squareCnt1=0,1:1):0))• P1OUT |= 0x1;• else• P1OUT &= 0xFFFE;

• }

• main()• {• WDTCTL = WDTPW + WDTHOLD; // Disable Watchdog• TACCR0 = 0x2710; // Timer Period• TACTL = 0x214; // Timer Control• #define dspWaitStandAlone() __enable_interrupt(); while (1) { LPM1;}• BCSCTL1 = CALBC1_1MHZ; // Use calibrated DCO settings• DCOCTL = CALDCO_1MHZ;• BCSCTL2 = 0x0; // MCLK and SMCLK sel• BCSCTL3 = 0x20; // VLO, range, & CAP sel• TACCTL0 |= CCIE; // Enable Timer A interrupt• TACTL |= 0x10; // Start Timer A• P1DIR = 0x1;• simInit( 0 );• startSimDsp();• dspWaitStandAlone();• return 0;• }

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Led PWM (eZ430) με Interrupts• // eZ430led2.c - self-dimming LED on P1.0 in eZ430 using SD16A• // PWM controlled by software, about 100Hz from ACLK = VLO,• // SD16A measures light during off phase of PWM• // Calibrated 8MHz DCO, no crystal, ACLK from VLO, power from JTAG (SBW)• // J H Davies, 2007-09-30; IAR Kickstart version 3.42A• //----------------------------------------------------------------------• #include <io430x20x3.h> // Header file for this device

• #include <intrinsics.h> // Intrinsic functions• //#include <stdint.h> // Standard integer types• #define LED_OUT P1OUT_bit.P1OUT_0 // Output to LED on P1.0• #define LED_ANALOG SD16AE_bit.SD16AE0 // Enable analog input from LED• #define RANGE 4096 // Dynamic range of values from SD16• #define PWM_MAX 128 // Maximum value of duty cycle• #define DIVISOR (RANGE/PWM_MAX) // For converting SD16 -> PWM• #define SENSE_TIME 2 // Cycles of TACLK needed for SD16

• //uint16_t dutyCycle = PWM_MAX; // Duty cycle computed from SD16• unsigned int dutyCycle = PWM_MAX;

// Start at maximum (but LED off)• void main (void)• {• WDTCTL = WDTPW | WDTHOLD; // Stop watchdog• BCSCTL1 = CALBC1_8MHZ; // Calibrated range for DCO• DCOCTL = CALDCO_8MHZ; // Calibrated tap and modulation• BCSCTL2 = DIVS_3; // SMCLK = DCO / 8 = 1MHz• BCSCTL3 = LFXT1S_2; // Select ACLK from VLO (no crystal)• P2SEL = 0; // Digital i/o rather than

crystal• P2REN = BIT6|BIT7; // Pull Rs on unused pins (6 and 7)• P1REN = ~BIT0; // Pull Rs on all pins except 0• P1DIR = BIT0; // To drive LED on P1.0• LED_OUT = 0; // LED initially off (active high)• // Configure SD16A: clock from SMCLK, no division, internal reference on• SD16CTL = SD16XDIV_0 | SD16DIV_0 | SD16SSEL_1 | SD16REFON;

64

Led PWM (eZ430) με Interrupts (2)

• // Unipolar, single convs, OSR = 32, interrupts on finish• SD16CCTL0 = SD16UNI | SD16SNGL | SD16OSR_32 | SD16IE;• // PGA gain = 16, input channel A0+/-, result after 4th conversion• SD16INCTL0 = SD16GAIN_16 | SD16INCH_0 | SD16INTDLY_0;• // Timer_A for software-assisted PWM using channel 1, up to TACCR0 mode• TACCR0 = PWM_MAX + SENSE_TIME; // Overall period• TACCR1 = dutyCycle; // Initial duty cycle• TACCTL1 = CCIE; // Interrupts on compare• // Start Timer_A from ACLK, undivided, up mode, clear, interrupts• TACTL = TASSEL_1 | ID_0 | MC_1 | TACLR | TAIE;• for (;;) { // Loop forever• __low_power_mode_3(); // All action in interrupts• }• }• //----------------------------------------------------------------------• // Interrupt service routine for CCIFG1 and TAIFG; share vector• //----------------------------------------------------------------------• #pragma vector = TIMERA1_VECTOR• __interrupt void TIMERA1_ISR (void) // Shared ISR for CCIFG1 and TAIFG• {• switch (__even_in_range(TAIV, TAIV_TAIFG)) { // Acknowledges int• case 0: // No interrupt pending• break; // No action• case TAIV_TAIFG: // TAIFG vector• // Start PWM duty cycle by turning LED on and updating duty cycle• LED_OUT = 1; // Turn LED on; duty cycle always > 0• TACCR1 = dutyCycle; // Update duty cycle from SD16 reading• break;• case TAIV_CCIFG1: // CCIFG1 vector• // Finish PWM duty cycle by turning off LED, then measuring light level• LED_OUT = 0; // End of duty cycle: Turn off LED• LED_ANALOG = 1; // Switch LED to SD16A input A0+• SD16CCTL0_bit.SD16SC = 1; // Start SD16A conversion• // Change mode from LPM3 to LPM0 on exit to provide SMCLK for SD16• __bic_SR_register_on_exit(LPM3_bits);• __bis_SR_register_on_exit(LPM0_bits);• break;• default: // Should not be possible: ignore• break;• }• }

65

Led PWM (eZ430) με Interrupts (3)

• //----------------------------------------------------------------------• // ISR for SD16A: compute new duty cycle in range [1, PWM_MAX]• //----------------------------------------------------------------------• #pragma vector = SD16_VECTOR• __interrupt void SD16_ISR (void) // Acknowledged when SD16MEM0 read• {• static unsigned int floor = 0xFFFF - RANGE; // Dark reading from SD16

• LED_ANALOG = 0; // Switch LED back to digital output

• if (SD16MEM0 < floor) { // Update floor if new reading is lower• floor = SD16MEM0;• dutyCycle = 1; // Minimum value; never go

down to 0• } else if (SD16MEM0 >= (floor + RANGE - DIVISOR)) {• dutyCycle = PWM_MAX; // Maximum value (saturates)• } else {• dutyCycle = (SD16MEM0 - floor) / DIVISOR + 1;• }• // Change mode from LPM0 to LPM3 on exit: SMCLK no longer needed• __bic_SR_register_on_exit(LPM0_bits); // (not really necessary)• __bis_SR_register_on_exit(LPM3_bits);• }

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