WINLABIvan Seskar

Rutgers, The State University of New Jerseywww.winlab.rutgers.edu

Contact: Ivan Seskar, Associate Directorseskar (at) winlab (dot) rutgers (dot) edu

Cognitive Radio Kit Framework : Experimental

Platform for Dynamic Spectrum Research

WINLAB

Cognitive Radio (CR) platforms

MIT Airblue

USRP2USRP

RICE WARP PlatformU. Of Colorado

• Research community already has a variety of platforms for CR research

Microsoft Sora

WINLAB

Cognitive Radio platform issues

Problems with existing (experimental) platforms: do we wait for Moore’s law to catch up or we need new hardware architectures for CR? “Analog” issues: range (frequency, power), agility, cost,

scalability, future proofing “Digital” issues: scalability, power consumption, performance

vs. flexibility, cost, future proofing Ease of “use” issues: how do we program/control these

platforms?

Large scale experiments in realistic environments Nation-wide (experimental) cognitive radio spectrum allocation Multiple testbeds with different objectives GENI advanced technology demonstrator of cognitive radio

networks

Address New Application Needs Spectrum sensing, vehicular networking

WINLAB

Spiral II GENI project: CR kit

Wide-tuning Digital Radio (WDR) block diagram

Range of baseband FPGA platforms

4 (2) configurable radio modules for phased or smart antenna applications with

Phase I: Each module allows two 25 MHz bands from 300 to 6000 MHz

Phase II: Each module allows two different 300 MHz bands from 100 to 7500 MHz

Each module supports independent full duplex operation.

1 usec RF frequency switching time

Switched antenna diversity for both TX and RX channels.n

WINLAB

Why CRKIT Framework ?

Focus on APP Development

NOT complete Radio

Abstract lower level design complexities from Users

INNOVATION CYCLE

Live system runs

Focus on Creativity, not Engineering Complexity :

Split Baseband in two domain spaces : Dynamic – Swappable Communication

APPs (creative problem)

Static - Open-sourced System-on-Chip (complex engineering problem)

CRKIT = make real-time and wide-tuning radio a viable solution for large scale experiments.

Build Radio :

Non trivial effort Substantial barrier to entry Many engineering man-hours

needed Requires cross-disciplinary

expertise

WDR from Radio Technology Solutions

FSoC Features

Access to lower level resources thru APIs VITA radio transport protocol for radio control Networking capable node Support up to four dynamic APPs Library of Open-sourced Communication APPs Static Framework utilization level < 15% for

V5SX95, even less for newer technologies, for ex. Virtex7 .

Transparent to underlying FPGA technology. Can be ported to future HW platforms and

newer FPGA technologies.

WINLAB

CRKIT Framework Overview

Baseband Processor :

FPGA-based off-the-shelf board Multitude of high-speed IOs : GigE, USB, PCIe Control up to 4 full-duplex wideband radios FPGA-based System-on-Chip (FSoC)

implementation Wide-tuning Radio (WDR) Module :

Wide-tuning range : 100MHz to 7.5GHz 36MHz bandwidth 50Msps 12-bit ADC, 200Msps 12-bit DAC 1us switch between frequencies

CRKIT

HWPlatform

SWPlatform

ORBITIntegration

Wide-tuningRadio

FlexibleBaseband

PHYLayer Exp.

Exp.Scalability

Embedded HOST

FPGA-SoC

Comm.APPs

RadioAPIs

OMF

WINLAB

FPGA SoC OverviewFPGA SoC components :

1. Ethernet Port (static)• Gigabit Ethernet rate• frame synchronization• frame generation/formatting

2. Packet Processor (static) • packet classification/forwarding• Control packets -> Processor Core• Data packets -> APP• Memory management for APP data• IP/VITA packet generation/formatting

3. Application (dynamic)• User specific designs e.g. simple QPSK/QAM,

OFDM, FHSS, DSSS…• Support up to 4 APPs simultaneously• Swappable APPs, can either reside in RAM or

downloadable through Ethernet port.

4. RF Port (static)• interfacing to DA/AD

5. RMAP Processor (static)• Sub-system interfacing and control• Address decoding• RF SPI Control

6. Processor Core (static)• 32-bit Softcore processor • bus interconnect• interfacing to 32MB DRAM• interfacing to 16MB FLASH

Three distinct data flows through system:

1) APP/Processor Core to outbound ethernet port2) Inbound ethernet port to APP3) Inbound ethernet port to Processor Core

WINLAB

CRKIT Transport Layers

Framework domain (static)

APP domain (dynamic)

ETH Layer – Ethernet Physical layer only, no MAC. Only Ethernet frames with Broadcast MAC or matching destination MAC addresses are forwarded to IP layer.

IP Layer (Fast Path) – Hardware based implementation Only a subset of IP and UDP functions. Fast track is reserved for APP data related

traffic Data IP packets are routed to the fast track

based on specific UDP port number.

IP Layer (Slow Path) – Software based implementation Support TCP as this is done in SW e.g.

processor core. Slow track is reserved mostly for control

related traffic : CRKit hardware configuration (register map access) and RF control.

Any IP packets with UDP port number not matching the fast track UDP port number will be routed to the slow track.

Note : for Address Resolution Protocol (ARP) the IP layer is bypassed, we parse the packets based on Ethernet frame Ethertype field.

VRT Layer – VITA Radio Transport layer, only a subset of

VITA standard is supported. VRT layer is optional, bypass this layer if not

used. VRT useful to mux multiple radio streams to a

single pipe, and demux at the other end. Standardized radio packet types: 1) Data for

signal data transmission, could be digitized I/Q samples. 2) Context for control information such as set frequency, power level, bandwidth and so forth.

Framework Domain :

User Specific Layer - since we are in the APP domain, users have their freedom to add any new layers they may wish.

Wireless PHY – again user specific implementation.

Application Domain :

WINLAB

Inbound Data FlowPCORE CMD FORMAT

If (V==1) then VITA context packetElse non-VITA packet use ethertype field for further parsingEndif;

Forward ethernet payload if :

incoming MAC = dMAC incoming MAC = Broadcast

Append Ethertype field (16-bit) to ethernet payload

if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000-1004) then forward UDP payload to VITA Receiver

else

forward packet to PCORE

Ethertype = 0x0800 - IPv4 0x0806 - ARP

Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM.

PortID LookupTable

WINLAB

Inbound Register Map

Registers visible to PCORE

For UDP Port 1000 Traffic(VITA)

StreamID lookup(direct-mapped) APP Identifier

For non-VITA trafficUDP 1001 => P0UDP 1002 => P1UDP 1003 => P2UDP 1004 => P3

WINLAB

Outbound Data Flow

VRT Receiver

Lookup using PortID

Lookup using PortID

if V-Flag then Enable VITA formatting

If IP-Flag then IP packet processing.

WINLAB

Outbound Packet Processor RMAP

Lookup using PID

Data/Context

VITA header

VITA enable flag

StreamID Lookup Table MAC/IP Lookup Table

IP header

Lookup using PID

IP enable flag

WINLAB

CRKIT Register Address Map

Upper 4 MSBs :

0x0-0x1 : PCORE0x2 : CRKITOthers : Unused

0x0 : CMN0x1 : ETH0x2 : PKT0x4-0xB : APP0xC : DAC IF0xD : ADC IF

INTSPI, LEDDCM/CLOCKCE

WINLAB

CRKIT Programming Model

Network

HOST CRKIT

Applicationdevelopment

CRKITdevelopment

Comm.APP

EmbeddedSW

GUI Algorithm

SystemDebugging

SystemTest

HW Configuration

IP Networking

MathworksSimulink

CR DSAHost

CMD ParsingVHDL/Verilog

DHCP/ARP ETH/VITALookup Tables/

RF

Java, C# C C

WINLAB

APP Development Flow

MATLAB Simulink Flow

CRKITFlow

APP Specification

Design dynamicAPP

APP Validation

Compile APP

Link APP toFramework

CompileFramework

GenerateFPGA bit file

Downloadto Hardware

PCOREboots

Execute CRKITEmbedded SW

Xilinx ISE Flow

CRKIT Embedded SW

HWConfig.

NetworkingHostCMD Parsing

1. Get IP address using DHCP2. Discover HOST3. Configure CRKIT hardware4. Parse HOST commands

Lookup TableConfiguration

RF Control

dynamicConfig.

(ETH/VITA)

initialconfig.

WINLAB

Innovation Cycle

Algorithms/Models

LiveExperiments

BuildRadioidea

Feedback

Creative Processes

Engineering Processes

WINLAB

APP Simulink Environment

APP

PCORE DRIVER

BMUDRV

BMUMON

RFLPBK

CMD

.txt file

ETH

.txt files

.txt files

data

RegisterRead/Write

IOValidation

DataVerification

ChannelModel

Send X data packets

I/Q

I/Q

WINLAB

APP Simulink Testbench

WINLAB

Rendezvous APPs

WINLAB

QPSK Transmitter

WINLAB

QPSK Receiver

WINLAB

Rendezvous APP – FPGA Utilization

WINLAB

ORBIT Integration

ORBIT SB6Actual SB6 with two

CRKITs

OPEN TO ORBIT COMMUNITY !

WINLAB

Conclusion

CRKIT = Advanced Radio System enabling experimental research in CR and DSA techniques

Powerful combination of Wideband Radio and Flexible Baseband Processing

FSoC Static and Dynamic domain spaces

APP development for Creativity and Productivity => MATLAB/Simulink

Framework development for Engineering Complexity => Traditional Hardware design flow

ORBIT Integration => User Friendliness Experience + Experimentation Scalability

WINLAB

Future Work

Extend APP library : OFDM-based waveform APP

Upgrade Static framework to support live loadable APPs from Network :1. Clock Management2. Run-time Reconfiguration

Port Linux to PCORE

Integrate CRKIT fully into ORBIT Management Framework (OMF)

Extreme Digital Radio (XDR) : 800MHz Bandwidth Upgrade baseband processor board to newer and higher performance FPGA

technologies