winlab cr platform
DESCRIPTION
WINLAB CR Platform. Ivan Seskar Rutgers, The State University of New Jersey www.winlab.rutgers.edu Contact: Ivan Seskar, Associate Director s eskar (at) winlab (dot) rutgers (dot) edu. Cognitive Radio (CR) p latforms. - PowerPoint PPT PresentationTRANSCRIPT
WINLABIvan Seskar
Rutgers, The State University of New Jerseywww.winlab.rutgers.edu
Contact: Ivan Seskar, Associate Directorseskar (at) winlab (dot) rutgers (dot) edu
WINLAB CR Platform
WINLAB
Cognitive Radio (CR) platforms
WINLAB WINC2R System
USRP2USRP
RICE WARP PlatformU. Of Colorado
• Research community already has a variety of platforms for CR research
Microsoft Sora
WINLAB
Cognitive Radio platform issues
Problems with existing (experimental) platforms: do we wait for Moore’s law to catch up or we need new hardware architectures for CR? “Analog” issues: range (frequency, power), agility, cost,
scalability, future proofing “Digital” issues: scalability, power consumption, performance
vs. flexibility, cost, future proofing Ease of “use” issues: how do we program/control these
platforms? Large scale experiments in realistic environments
Nation-wide (experimental) cognitive radio spectrum allocation Multiple testbeds with different objectives GENI advanced technology demonstrator of cognitive radio
networks Address New Application Needs
Spectrum sensing, vehicular networking
WINLAB
Spiral II GENI project: CR kit
Wideband Digital Radio (WDR) block diagram
Range of baseband FPGA platforms
4 (2) configurable radio modules for phased or smart antenna applications with
Phase I: Each module allows two 25 MHz bands from 300 to 6000 MHz
Phase II: Each module allows two different 300 MHz bands from 100 to 7500 MHz
Each module supports independent full duplex operation.
1 usec RF frequency switching time
Switched antenna diversity for both TX and RX channels.n
WINLAB
CR Kit Timeline 2/1/10 - Redesign, manufacturing, testing and integration of
frequency-extended Phase I radio card for use in stand-alone cognitive radio system.
3/16/10 - Integration of Phase I radio card with off-the-shelf components to develop a stand-alone cognitive radio platform; validation with basic tests; demonstration
7/20/10 - Initial integration of stand-alone cognitive radio platform with v0.1 software, initial integration into ORBIT Management Framework, and demonstration.
7/20/10 - Make stand-alone cognitive radio system available for use by selected (GENI) researchers.
9/30/10 - Release a full set of design information for stand-alone cognitive radio system “kit”, including hardware and v0.1 software.
12/1/10 - Design, manufacturing, testing and integration of infrastructure-class Phase II radio card featuring wideband operation, for use in stand-alone and infrastructure class cognitive radio platforms.
WINLAB
OCRP Tx Architecture
WINLAB
OCRP Architecture v1
WINLAB
OCRP Architecture v2
WINLAB
OCRP Architecture (with uP)
WINLAB
OCRP Application Block
Application sub-blocks OCRP provides a control block and a
register map to support the application
The user may or may not use these blocks, (i.e., the User Application may contain its own control logic and its own register map).
User specific logic/functions are contained in the User Application module. The User Application must conform to the interface provided by OCRP
Application Interfaces System Control :
1. Application Register map values are provided using Parameter setting options e.g. app_param_valid , app_param_data
2. Data pointer and size information are provided such that Application Block can fetch data/control information from buffer.
DAC :1. Direct access to DAC
Buffer : 1. App fetches buffer data without intervention
from System Control. Note that buffer data could be either data or control frame.
WINLAB
User Application Example: Waveform Generator
This example uses the application data fetch block and register map provided by OCRP.
The application consists of a sine wave generator, an additive white gaussian noise generator and a modulator. One of these blocks can be selected by sending a control command to the system.
Data can be sent to the modulator by a Data Command.
WINLAB
OCRP Library Outline
Libraries : Common
a. DAC I/Fb. ADC I/Fc. SPI d. Register Mape. …
Communicationa. Modulator/Demodulatorb. Encoder/Decoderc. Interleaver/Deinterleaverd. OFDM
1. Frequency Offset Estimation2. Frequency Offset Correction3. Timing Synchronization4. Cyclic Prefix insertion5. …
e. …
DSPa. AWGN Generatorb. Sine Generatorc. DFT/FFTd. FIR/IIR Filtere. …
Networkinga. Ethernetb. PCIec. RS232d. …
Processora. uP e.g. Microblazeb. Bus e.g. PLBc. Bus interface e.g. IPIFd. RAM/FLASH interfacese. …
Xilinxa. RAM/ROM/FIFOb. DCM/PLLc. …
Board Specifica. Board specific modules which
cannot be shared across multiple projects.
WINLAB
OCRP Library Outline (cont’d)
Project Specifica. Project specific modules, example
: OCRP framework, top level module.
b. Project specific application module, including register map definition, example : OCRP application module with specific register map definition.
c. Project specific User Application module, example : OCRP waveform generator.
d. Note : any modules which can be shared across projects shall NOT be under Project Specific library, but should be propagated to upper libraries such as COMMON, COMMUNICATION and so forth…
WINLAB
OCRP Tx Architecture
Wibo SPI
Application Block
Dibo SPI
DAC Interface
wibo_senwibo_sclkwibo_sdatawibo_u2_sen radio_io5 radio_io6 radio_io7
dibo_sdata
dibo_sclkdibo_sen
tx_synctx_data
other outputs
other outputs
RxEthernetInterface
Buffer
SystemController
MemoryControl
Command FIFO
CommandDescriptorGenerator
WINLAB
OCRP Application Block
Application DAC Interface
BufferInterface
buf_addr[15:0]
tx_data_i[15:0]
buf_rd
buf_data[31:0]
data_out_valid
tx_data_q[15:0]
app_req
app_param_addr[7:0]
app_param_data[23:0]
app_ptr[15:0]
app_size[15:0]
SystemControl
Interface
app_done
app_type[1:0]
app_param_valid
The OCRP provides a control block and a register map to support the application
The user may or may not use these blocks, (i.e., the user application may contain its own control logic and its own register map).
The user application must conform to the interface provided by OCRP
System Control Interface :1. Application Register map values are provided using
Parameter setting options e.g. app_param_valid , app_param_data
2. Data pointer and size information are provided such that Application Block can fetch data/control information from buffer.
DAC Interface: 1. Direct access to DAC
Buffer Iterface:1. App fetches buffer data without intervention from System
Control. Note that buffer data could be either data or control frame.
WINLAB
User Application Example: Waveform Generator
This example uses the application data fetch block and register map provided by OCRP.
The application consists of a sine wave generator, an additive white gaussian noise generator and a modulator. One of these blocks can be selected by sending a control command to the system.
Data can be sent to the modulator by a data command.