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Page 1: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

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Page 2: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory 4. Component Selection 5. Final Circuit Design and Block Diagram 6. Input Stage 7. Output Voltage Offset 8. Signal Processor 9. Mute Control 10. Modulator Feedback 11. Parallel Power Output 12. Bypass Filtering 13. Output Filter 14. Power Stage 15. Heat Management 16. Grounding and EMC Considerations 17. PCB Layout 18. Costs and Parts List 19. Performance and Testing 20. Bibliography 21. Appendix !

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1. Introduction and Project Objectives This project is centered on the design considerations required for Class-T amplification. More specifically, this report will document all design aspects associated with the project, focusing on overall circuit design and analysis, component selection and placement, electromagnetic compatibility and proper grounding, and printed circuit board (PCB) design and layout. Furthermore, this report will provide a cost breakdown and parts list, along with suggestions for retailers and PCB fabrication houses. The perfect amplifier wouldn’t introduce noise, distortion, or coloration of the original audio signal, and would be capable of providing infinite power gain without inefficiencies or heat management issues. Unfortunately this is not a perfect world, and amplifier design is a delicate balancing act between different compromises and trade-offs. With this in mind, a functional description needs to be established in order to design an amplifier that fits certain performance characteristics. ! Functional Description

The overall goal of this project is to produce a high-quality Class-T amplifier capable of powering both 4! and 8! stereo speakers continuously at levels around 90 dB SPL with 15 dB SPL of headroom in order to handle musical peaks with minimum distortion. This design utilizes Tripath Technology’s TC2001 signal processor and TP2050 power output integrated circuits. Based off of the product specifications, the overall design will be capable of providing 50W of continuous power per channel at .005% third order harmonic distortion (THD). Using Tripath’s proprietary Digital Power Processing Technology will allow both the audio fidelity of Class-AB and the power efficiency of Class-D amplifiers. A combination of both through-hole and surface mount components will allow overall versatility and customization to a specific speaker type. ! Overall Design Goals With the factors described above taken into account, this amplifier should:

1) Fit budget constraints ($500 max) 2) Have high-fidelity and accuracy 3) Sustain 90 dB SPL (+15 dB headroom) 4) Require minimum heat-sinking 5) Be compact in size 6) Look professional and high quality

!!

!!

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2. Analog and Digital Signals In a field once dominated by analog equipment, the use of digital technology is rapidly gaining popularity in high-fidelity audio amplification. Naturally, there is a rift among audiophile circles; each claiming that one type of amplification is superior to the other. However, this is simply a matter of taste, as both can offer high-quality sound when properly designed. Class-T is a digital signal processor and amplifier, and in order to understand the theory behind how this is accomplished, it is important to understand the basics of both analog and digital signals. ! Analog Analog signal is simply a continuous time varying voltage. This means that over a given time period, the amplitude of a voltage waveform is constantly changing. A common example of an analog signal is a microphone. The electrical signal produced by a microphone varies continuously with changes from the acoustic source. The input and output of this Class-T amplifier are in analog form.

! Digital Digital signal differs from analog in the fact that both time and amplitude of a signal has been made discreet1. This simply means that the signal is broken up into individual sections in both domains. In this design, time is broken up into individual sections set by the sample rate. The voltage is also discreet, as it can only take the form of a set number of voltages. This is set by the resolution, which will be described in the next section. The following picture provides a visual representation of the content just covered2:

1 "Digital Signals," 2011, Wikipedia, 18 Apr. 2011 <http://en.wikipedia.org/wiki/Digital_signal>. 2 Michael Stutz, “Practical Considerations of ADC Circuits,” 2000, Design Science Liscense, 18 Apr. 2011 < http://www.allaboutcircuits.com/vol_4/chpt_13/10.html>.

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3. ADC and DAC Conversion Theory

At the heart of Tripath’s signal processor design is the Sigma-Delta analog-to-digital converter. Understanding the theory behind its operation is of the utmost importance, as this converter is responsible for amplifying the analog audio input signal and converting it to a digital switching pattern. ! Sigma-Delta Theory The backbone of the sigma-delta converter consists of simple analog components (a comparator, voltage reference, a switch, and one or more integrators and analog summing circuits), and proprietary digital signal processing developed by Tripath3. Analog Device’s Design Center4 provides a very clear visual explanation of the sigma-delta topology as shown below. For a basic explanation, a VIN of 1 Volt will be used, and it will be assumed that every component has been reset to zero. The input voltage is first summed with the output of a feedback digital-to-analog converter (DAC). An integrator then adds the output of this summing node to a value it has stored from the previous integration step (initially zero). A comparator outputs logic 1 if the integrator output is greater than or equal to zero volts and logic 0 otherwise. A 1-bit DAC feeds the output of the comparator back to the summing node: +VREF for logic 1 and -VREF for logic 0. The major property behind sigma-delta is derived from this constant feedback loop. This ensures that the average of the bitstream output represents the average input signal.5 As the input signal increases, more 1s are added to the bitstream, and conversely, as the input signal decreases, more 0s are added to the bitstream. In order for this system to work so that it adequately reflects the original audio input signal, a high sample rate is used (will be covered in more detail shortly). The screenshot on the following page shows the basic operation of each of the above steps in the sigma-delta ADC. It should be noted that in this example the output bitstream is represented by the Latch waveform, and not the comparator. The digital clock frequency is set by the TC2001 at 650kHz.

3 Walt Kester, “ADC Architectures III: Sigma-Delta ADC Basics”, 2009, Analog Devices, MT-022 Tutorial. 4 “Sigma-Delta ADC Tutorial”, 2011, Analog Devices, 18 Apr. 2011 <http://designtools.analog.com/dt/sdtutorial/sdtutorial.html>. 5 Uwe Beis, “An Introduction to Delta Sigma Converters,” 2008, Electronics, 18 Apr. 2011 <http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html>.

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The previous description shows how an analog signal is encoded into a digital format using the sigma-delta method to continuously reflect the average analog input level. In order to avoid quantization noise produced by the conversion of analog signals to digital signals, sigma-delta uses a combination of over-sampling and noise shaping to minimize noise in the actual audio bandwidth. The Nyquist Theorem states that a sample rate of two times the highest frequency should be used in digital. A perfect sigma-delta ADC has an RMS quantization noise of q/!12 uniformly distributed within the Nyquist band of dc to fs/2 (where q is the value of an LSB and fs is the sampling rate)6. The quantization noise produced using the Nyquist theorem is shown in section A of figure on the following page. As you can see, the amount of noise present in the signal is unacceptable. To combat this effect, a process known as over-sampling is used. This simply means that the sample rate is set much higher than the Nyquist Theorem definition. For example, following the Nyquist Theorem, the sample rate would be two time 20kHz (the max frequency in the audio band), resulting in 40kHz. The TC2001 signal processor used in this Class-T amplifier design has a sample-rate of 650kHz. This spreads the quantization

6 Walt Kester, “ADC Architectures III: Sigma-Delta ADC Basics”, 2009, Analog Devices, MT-022 Tutorial.

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noise out over a larger area as shown in section B of the figure below. The high and low pass filters set by separate section still set the audio band from 20Hz to 20kHz, but the noise present in the audio band is now much less. To further combat quantization noise present in the audio band, a process known as noise shaping is used. This consists of proprietary digital filtering designed by Tripath Technology, Inc. The effects of noise-shaping filters are shown in section C in the figure below. A

A low pass filter is required at the output of the amplified digital signal. In this amplifier design, a passive low-pass crossover is used to demodulate the digital signal by taking the average signal level out of the bitstream. “You can regard the bitstream as a signal with its information in the lower frequency band and lots of noise above it7”.

7 Uwe Beis, “An Introduction to Delta Sigma Converters,” 2008, Electronics, 18 Apr. 2011 <http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html>.

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4. Component Selection Component selection for a circuit design is critical, as it has a significant impact on overall performance. Knowledge of various component materials, their specific applications, and cost versus performance is necessary. The following sub-sections cover the major components used in this design, and why certain types were selected for their intended purposes. ! Capacitors Capacitor losses due to dielectric material have a noticeable effect on audio quality and noise performance, and certain dielectric materials are more suited to specific applications. Furthermore, capacitor construction and resonance plays an important role in the performance of audio-grade capacitors. For an in depth technical paper about the mechanical construction of capacitors, visit Humble Homemade Hifi8. Decoupling capacitors, also known as bypass capacitors, play one of the most important roles in this amplifier design. The purpose of a decoupling capacitor is to decouple one part of an electrical network from another9. In the case of this design, decoupling capacitors are used for two major purposes. First of all, decoupling capacitors are placed in parallel (see picture below10) on every component power input pin to ground. This serves the purpose of providing any AC signal that may be superimposed on the DC power line with an immediate path to ground. In order to understand how this works we need to only look at how a capacitor behaves with AC and DC signals.

For DC signal, a capacitor acts as an open circuit. Current will initially flow through the capacitor until it is charged to the level of the applied source voltage (5VDC or 30VDC). Once the capacitor reaches its charged state, it effectively blocks DC current from passing through. This can be explained by the following formulae: I = (Vs – Vc) / R Where I is the charging current, Vc is the voltage across the capacitor, Vs is the source voltage, and R is the circuit resistance.

8 Tony Gee, “Capacitor Test,” 2011, Creative Commons, 24 Apr. 2011 <http://www.humblehomemadehifi.com/Cap.html>. 9 "Decoupling Capacitor," 2011, Wikipedia, 24 Apr. 2011 <http://en.wikipedia.org/wiki/Decoupling_capacitor>. 10 Kevin Ross, “The Basics,” 2009, Creative Commons, 24 Apr. 2011 <http://www.seattlerobotics.org/encoder/jun97/basics.html>.

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At time zero, there is no voltage across the capacitor. Once the voltage across the capacitor reaches the source voltage the current now become zero. This effectively separates the DC voltage and current, and is the basis for a decoupling capacitor. However, for an AC signal, the alternating current discharges the capacitor as it changes current direction. This charging and discharging allows the capacitor to pass AC current. This relates to decoupling because it will pass AC to ground, while blocking DC. Again, this will separate any AC noise present in the power supply, thus improving noise related issues in the circuitry. In addition to their noise filtering functions, decoupling capacitor are also used to store extra charge needed during peak loads. Music is very dynamic and decoupling capacitors are used to hold and provide extra charge when the power supply levels droop due to peak power conditions. Different capacitor types are used for the different decoupling purposes described above. Ceramic capacitors are used primarily for high frequency decoupling and are non-polarized11. These are available in relatively low capacitance values, and are useful for power supply bypassing, coupling, timing, and high-voltage applications, making them suitable for Class-T circuit design. Aluminum electrolytics are commonly used as energy storage decouplers, as they can store more charge. Great care is needed when using these, as polarity is an issue. In many designs, including this one, a combination of the two are used as decouplers to cover all the areas described above. Finally, the proper placement of these components is highly important. Tripath recommends keeping the decoupling capacitors as close as possible to the components pins. Coupling capacitors, also known as DC blockers, work with the same principles explained above, but serve an entirely different purpose. Instead of being placed in parallel with a signal source, they are placed in series. These are commonly used on the inputs and outputs of individual component stages of an amplifier. In theory, this would allow only the analog source signal to pass through to the amplifier circuitry, and vice versa, would allow only an analog output signal to pass to the speakers. Coupling capacitors were used only on the inputs of this design, while a DC voltage offset circuit is used to limit the DC output at the speaker terminals. Quality of the input capacitor is important. First of all, overall circuit noise is dependent primarily on the quality of the first components in the audio chain. If an input component introduces noise, this noise will then be amplified created a high noise floor. This is obviously something to be avoided in a high-fidelity audio system. The input capacitor also has an important role in shaping the sound of the amplifier. Therefore, a premium film capacitor was chosen for this application. ClarityCap’s ESA film capacitor were

11 Zed Audio, “Capacitors,” 2005, Zed Audio Corporation, 24 Apr. 2011 <http://www.zedaudiocorp.com/Technical/Capacitors.htm>.

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chosen for input coupling capacitors, as they offer more clarity and spatiality12, while still being affordable. Filtering capacitors are also used in this amplifier circuit on the output filter. High-quality film capacitors were chosen, as they are generally used in audio filters13, and can withstand high ripple currents caused by the switching outputs. Tripath also recommends the use of film capacitors for this application. The filtering capacitor is used with the output inductor to form an LC low-pass filter (explained in detail in output filter section). ! Resistors Resistor selection also has a significant impact on the overall tonal characteristics of an amplifier’s sound. In general, resistors add a ‘glazed’ and ‘hashy’ noise in the treble region and can dilute stereo focus14. Some of the major resistor types that were considered in this design were metal-film, carbon-film, and bulk-foil, as they are commonly used resistors in audio applications. Choosing which type to use was relatively easy due to availability and pricing. Of the three types, metal-film was readily available and inexpensive. ! Inductors Output inductor selection is yet another critical design step. Tripath states that the core material and geometry of the output filter inductor affects the amplifier distortion levels, efficiency, power dissipation and electromagnetic interference output. Core material also has a direct effect on the produced magnetic field and core saturation. Iron powder toroidal cores were chosen to minimize magnetic radiation and interference. 22AWG litz wire was chosen to further minimize losses. ! Potentiometer A high quality potentiometer is also necessary for high-quality stereo applications. An ALPS Blue Velvet potentiometer was chosen because it offers quality sound and good channel tracking. As discussed with the input capacitors, high quality is of importance, as this component is first in the audio-chain. In order to control the volume of both channels simultaneously, a duel-gang potentiometer with an audio taper was used. Duel-gang means that two potentiometers are controlled by one input shaft. The Blue Velvet was chosen due to minimal difference in channel control. An audio taper was chosen because audio devices operate on a logarithmic (non-linear) scale. This is necessary so that when the volume control is at the halfway point, the audio level is at half of its maximum volume level.

12 Tony Gee, “Capacitor Test,” 2011, Creative Commons, 24 Apr. 2011 <http://www.humblehomemadehifi.com/Cap.html>. 13 Zed Audio, “Capacitors,” 2005, Zed Audio Corporation, 24 Apr. 2011 <http://www.zedaudiocorp.com/Technical/Capacitors.htm>. 14 Martin Coloms, “Piece de Resistance,” 1996, SAS Audio Labs, 24 Apr. 2011 <http://www.sasaudiolabs.com/resistor.htm>.

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! Through-Hole versus Surface-Mount Certain components were chosen as through-hole or surface-mount to offer versatility in this amplifier’s design. Both the input stage components (explained later) and output filter components (also explained later) are through-hole components so that the low-and high-pass filters, and overall gain can be changed and experimented with. This also allows for the customization of this amplifier for a specific set of speakers and was a major design choice. All other components were surface-mount to minimize area, ground loops, and to facilitated high frequencies.

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5. Final Circuit Design and Block Diagram The following schematic is the final circuit design for this Class-T amplifier. A larger schematic is included in the Appendix for reference.

The following block diagram breaks down the above circuit into individual stages, which will be described in the following sections.

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6. Input Stage The input stage of the circuit consists of the input signal source, the volume potentiometer, the input capacitor (CI), the input resistor (RI), and the feedback resistor (RF). This stage and its components are responsible for two important design factors. The input resistor and feedback resistor provide the AC gain for the input stage. The TC2001 signal processor is configured as an inverting operational amplifier for each channel. An inverting amplifier’s gain set by the formula:

The resistors for RF and RI were chosen as through-hole components in the final design so that the input stage gain can be easily changed. In Tripath’s test schematic, the input stage gain is designed as a constant gain amplifier with values of 20k! for each resistor. However, a conventional line-level input may not have enough gain for inefficient loudspeakers, especially if they're 8 ohms. The peak-to-peak voltage for consumer audio line input is

.894 VPP and USA professional audio is 3.473 VPP15. Tripath states that for maximum

performance, the input stage gain should be set so that the maximum input signal level will drive the input stage output to 4VPP. In order to provide a balance between the two, the component values chosen for this design were 28k! for the feedback resistor and 20k! for the input resistor, giving an overall stage gain of 1.4. This is subject to change, and a final input stage gain will be decided after testing. The other major section of this stage is the input capacitor. Its purpose is to act as an AC coupler. As discussed in the previous section, the purpose behind this is to block any DC components present in the audio input signal. The value for the input capacitor can be calculated once a value for the input resistor has been determined. This calculation is performed using the equation: Given an input resistance of 20k!, the input capacitor value is calculated to be 2.2uF. In addition, the quality of this component should be taken into consideration, as any component early in the audio chain will have significant effects on the overall noise present at the output of the amplifier. The entire input stage also sets the lower limit of the overall bandwidth in the amplifier design. The input capacitor and the input resistor set the low frequency pole. Tripath 15 "Line Level," 2011, Wikipedia, 24 Apr. 2011 <http://en.wikipedia.org/wiki/Line-level>.

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recommends that this pole be set below 10Hz. The high-pass cutoff frequency can be calculated by the same formula below by rearranging it to solve for fP: Finally, the input resistor sets the input impedance in conjunction with the volume potentiometer seen by the signal source. In order to reduce noise pick-up while also providing a manageable load to the input source, and potentiometer value of 50k! was chosen to present an overall input impedance of 70k!.

7. Output Voltage Offset The output voltage offset stage consists of the trimmer potentiometer (ROFB), voltage-divider resistors (ROFA and ROFC), and the decoupling capacitor (COF). The main purpose behind this circuit sub-section is to manually trim the DC offset on the output of the TK2050 power output. The resistors ROFA and ROFC are set up as a voltage divider in order to limit the DC offset range allowing for more precise adjustment. The capacitor (COF) is simply a decoupling capacitor used to block AC noise interference from the 5V source, which would ultimately show up at the speaker outputs.

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8. Signal Processor The signal processing stage consists of the TC2001 signal processor, R54, R53, RREF, and C7. It should be noted that all of the recommended values from Tripath were used, as they are critical to the TC2001’s performance. The TC2001 integrated circuit houses the sigma-delta analog-to-digital converter, which was covered in a previous section. For a recap, this signal processor is in charge of amplifying the analog input signal and converting it to a digital switching pattern. The resistors R54 and R53 are used to set the over/under supply voltage sensing. R54 is used to set the positive power stage sensing and R53 is used to set the negative power stage sensing. Any internal bias

currents will be disabled by locking out the TC2001 when the required voltage level is above or below these levels. The reference resistor (RREF) is used to set the internal reference voltage of the TC2001. Tripath states that this level is about 1.2 VDC.

The operational amplifiers within the TC2001 are set up as single-ended inputs (see picture on left). This simply means that one of the inputs is receiving an input signal, while the other is grounded. In the TC2001 design, the non-inverting inputs are both tied to a common ground through C7. One of the frequent issues associated with single-ended inputs is common-mode interference. Common-mode noise is a result of any signal that is common in waveform and phase on multiple conductors16. The value of C7 (BIASCAP) is selected to filter out any common-mode voltages presented to the input amplifiers17. The value of C7 was not deviated from, as it was determined by Tripath in order to provide a 2.5 VDC bias required by the TC2001.

16 G. Randy Slone, The Audiophile’s Project Sourcebook (New York: McGraw-Hill, 2002) 294. 17 Tripath Technology, Inc, TK2050 Technical Information (Revision 1.1 – October 2002)

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9. Mute Control The mute control stage consists of the MCP101 voltage supervisory circuit and a decoupling capacitor (C1). The MicroController MCP101 is an integrated circuit that provides the TC2001 with a logic high voltage level on the MUTE pin on power up and power down. This prevents any “thumps” or transients from occurring on the speaker outputs. The purpose of the capacitor is simply to act as a decoupler. A test circuit was bread boarded, and the following waveform shows the results of the test:

The above screenshot shows that the MCP101 provides a logic high voltage level on power up until it reaches a safe operating voltage level. The MCP101 threshold for this level is 4.5VDC. Once this value is reached, the output pin produces a logic low voltage level, which is required to un-mute the TC2001 signal processor. After all the considerations taken in the design of this amplifier, I noticed that an error was made in this subsection regarding the proper routing of the decoupling capacitor. As shown in the schematic, I have it set up as an AC coupling capacitor, which will block the necessary power supply voltage from entering the integrated circuit. This can be fixed through the use of a few jumpers, and will be changed in the PCB layout for the next prototype of this amplifier.

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10. Modulator Feedback The modulator feedback stage consists of feedback resistors (RFBB and RFBC) and a feedback capacitor (CFB). As shown in the picture to the left, there are four total feedback lines, as there is a positive and negative feedback loop for each of the two channels. The feedback is taken directly from the power output stage before the output filter. Tripath recommends that this signal be routed directly from the inductor pins to minimize any noise pick-up The modulator is responsible for converting the signal from the input stage to the high-voltage output signal18. In order to set the appropriate gain level for the output signal, both the maximum power supply voltage (30 VDC) and maximum modulator feedback level need to be taken into consideration. Tripath states that the maximum gain into the modulator section should be set to about 4VPP to avoid clipping. Again, this is set by the input gain stage through the resistors RI and RF, and is dependent of the input signal level. The overall amplifier gain is the product of the input stage gain and modulator stage gain as shown in the following formula:

By looking at the above formula, it can be determined that the modulator gain is dependent on the values of RRBB and RFBC. These values are set through the following formula:

In this design, the value of VCC is 30VDC and the value for RFBB was chosen to be 1k!. Plugging these values into the above formula gives a value of 14k! for the RFBC resistor. Now that all the component values have been calculated, they can be plugged into the AVTK2050 gain formula, producing a final gain of 21.

Component selection for this stage is also critical to the overall performance of this stage. The feedback resistor RFBC needs to be selected so that it has a power rating greater than PDISS = VCC

2/(2RFBC) in order to dissipate enough heat without failure. In the case of this design, the resistor power rating must be greater than .032W. 1/8-Watt resistors were picked to meet this requirement. 18 Tripath Technology, Inc, TK2050 Technical Information (Revision 1.1 – October 2002)

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The feedback delay capacitor CFB is responsible for lowering the idle switching frequency and filtering high frequency noise present in the feedback signal, thus improving amplifier performance19. Tripath states that the value of CFB should be offset so that the idle switching frequency differs by 40 kHz. This is designed to reduce any crosstalk and noise summation between channels. In this design, values of 390pF and 470pF were used and were based on the Tripath test schematic.

19 Tripath Technology, Inc, TK2050 Technical Information (Revision 1.1 – October 2002)

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11. Parallel Power Output The output power stage consists of two TP2050 power slug integrated circuits, and their associated components. All the component values are critical to the performance of the TP2050s, and were not changed or deviated from in this design. The TP2050 can be set up in two configurations. For stereo mode, the TP2050 is set up as a dual full bridge and can drive two 8! speakers with one chip. The TP2050 can also be configured in parallel as a single full bridge, which doubles the current capacity, but requires the use of two chips for stereo operation (one per channel). This amplifier design utilizes one TC2001 signal processor to control one TP2050 in parallel mode per channel, as it offers impressive performance advantages.

The major decision factor for parallel configuration over stereo configuration was due to performance factors. The following graphs indicate that the paralleled outputs have a significant advantage in performance aspects. Furthermore, this set-up allows greater versatility, as it can power both 8! and 4! loads.

Notice that the continuous power output in parallel (left) offers better performance than stereo (right).

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12. Bypass Filtering The bypass filter stage for the power output sections simply consist of a capacitor (CHBR). The purpose of these capacitors is to filter out AC noise from the 30VDC power supply, and to act as a high-frequency bypass to filter unwanted switching frequencies. A bypass capacitor must be placed from VCC to ground for each of the four MOSFET transistors in the TP2050. A 50V rating for these capacitors is required because they are subjected to the full supply range.

13. Output Filter

The output filter stage consists of output inductors (Lo) and their corresponding output capacitors (Co), a Zobel network consisting of a capacitor (CZ) and a resistor (RZ), and a differential mode capacitor (CDM). Through-hole for testing and customization The output filter serves multiple purposes. First of all, it is responsible for setting the low-pass cutoff frequency for the amplifiers bandwidth. As stated previously, the input stage determines the high-pass cut-off frequency through the input resistor and capacitor. Likewise, the output filter determines the low-pass cut-off frequency through a second-order LC low-pass filter consisting of the output inductor and

capacitor.

This section is also responsible for demodulating the amplified switching pattern from the output of the TP2050. This acts as a passive filter that averages the output signal in order to regain the original analog signal. The cutoff frequency and quality factor of the filter are determined by the formulas:

fc = 1/(2!LOCO) and Q = RLCO/"LOCO The cut-off frequency using a 15uH inductor and .22uF capacitor gives a value of 87.6kHz. This will effectively filter out the analog components from the switching signal while blocking quantization noise from the speaker outputs. Remember that the signal shaping from the sigma-delta effectively pushes the quantization noise band out of the

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audio bandwidth. The quality factor of the amplifier using an 8! and the same inductor and capacitor values gives a Q of .96. Q is a dimensionless factor used to describe how under-damped or over-damped a filter is20. Damping determines how quickly a signal decays. In other words, the Q of a filter has a direct effect on the response of the amplifier. A Q factor less than " is defined as over damped, meaning there is no oscillation of an input signal and there is a very quick decay of the signal. Conversely, a Q factor greater than " is defined as over damped, meaning there is possible of some oscillation and a slower decay. A major design choice in the output filter was to make all components through-hole. This facilitates the ability to fine-tune this amplifier for a specific set of speakers. For example a speaker with an impedance of 4! will behave differently than a speaker with an impedance of 8!. The above Q value was calculated as .96, which is a slightly under-damped response. By replacing the load with a set of speakers with a 4! impedance, the Q factor now becomes .48, which is slightly under-damped. A final output filter Q will be determined after testing is done with a specific set of speakers. A second important section within the output filter is the RC Zobel network consisting of a resistor (RZ) and a capacitor (CZ). The purpose of a Zobel network is to flatten out the impedance seen by the amplifier power output stage. This is placed in parallel with the speaker outputs. This wouldn’t be necessary if we were dealing with a purely resistive load. However, due to the reactive nature of loudspeakers, a consistent impedance is not presented to the TP2050 input. Finally, a differential capacitor is placed in parallel with the speaker outputs in order to filter out any differential currents that may have resulted in the circuit.

20 "Q Factor," 2011, Wikipedia, 30 Apr. 2011 <http://en.wikipedia.org/wiki/Q_factor#Q_factor_and_damping>.

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14. Power Stage The power stage consists of multiple sections and filters with specific purposes. These consist of power indication, supply decoupling for both the 5V and VCC voltages, a 5V voltage-

regulator, and power supply terminal and switch. This stage consists mainly of decoupling capacitors and voltage regulator. As discussed in a previous section, decouplers prevent any AC noise from interfering with the DC power lines. Electrolytic capacitors were used in conjunction with ceramic capacitor to provide decoupling for the TC2001 and TP2050 integrated circuits. Electrolytics were used because they can store extra charge in order to supply any extra current needed for peak current demands due to musical transients. These were placed as close as possible to their respective ICs in order to facilitate immediate response. Ceramics were used due to their ability to filter out any high-frequency content from the switching pattern. The power indication portion of the power stage consists simply of an LED in series with a resistor. As soon as power is switched on, a blue LED will light up indication current flow. The resistor is there to limit the current entering the LED. The LED’s brightness can be changed simply by replaced the resistor value. An LM7805 voltage regulator from ST Microelectronics was picked to convert the 30VDC power supply voltage to 5VDC required by the TC2001 input section. This voltage regulator was chosen for its thermal characteristics and availability. Heat sinking was a major consideration when picking the voltage regulator case type. 25VDC need to be dropped in order for the regulator to output 5V from a 30V source. The supply current for the TC2001 is state in the Tripath specification sheet as 60mA. Therefore, the total power that needs to be dissipated by the voltage regulator is 25V*60mA = 1.5W. The LM7805 is available in multiple different packages, and the T0-220 case was picked because it had the best thermal handling capabilities while taking up a small amount of space. Just to be safe, a small heat sink rated at 1.5W was added. A switch was picked that was rated above the 30VDC and 3.3A provided by the power supply for safety purposes. A diode is going to be placed across the terminals to provide a path for any current flow held by inductance of the overall circuit to prevent potentially sparking.

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15. Heat Management

Thermal management is incredibly important in amplifier design. The average amplifier is horribly inefficient, and inefficiency creates heat. Therefore, heat management is mandatory in order to prevent amplifier and component failure, and to meet safety standards. One major benefit of Class-T amplifier design is that it can theoretically reach 100% efficiency. Like most things, in real life it doesn’t quite work out this way. However, a Class-T amplifier is still capable of achieving significantly higher efficiency than other amplifier topologies. The following graph shows a realistic efficiency of this amplifier, and was provided in the Tripath specification sheet: The above graph shows that this amplifier can realistically achieve an efficiency of around 90%. So is it really necessary to have heat sinking? This is entirely dependent of the heat management abilities of the TP2050 integrated circuits. The junction-to-case thermal resistance of the TP2050 power slug is the major factor determining overall amplifier performance. The junction-to-case resistance value describes the case’s temperature rise in degrees Celsius relative to each Watt it is called upon to dissipate. The actual value of the TP2050 is 2.5oC/W. This can be applied to this design by considering the amount of power that needs to be dissipated as heat. The TP2050 can realistically generate 40W of power per channel. The power that needs to be dissipated can then be calculated by taking the inverse of the efficiency and multiplying it by the power output for one channel. This results in a value of 4 Watts that needs to be dissipated per channel. This would result in only a 10oC rise per channel, for a total rise of 20oC. This is a realistic expectation of heat sinking requirements. Due to the dynamic range of music, even if you pushed the volume of the amplifier up until you heard considerable distortion from clipping, you still wouldn’t be

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close to an “average” power output to the speaker system21. This shows that one of the major benefits of Class-T amplifiers is that it requires very little heat sinking. In order to take care of the 20oC that needs to be dissipated, this amplifier design uses a combination of conduction, convection, and radiation. This design utilizes an aluminum plate on the underside of the PCB board, which thermally couples the TP2050s to the aluminum enclosure. This serves two purposes. First of all, the aluminum plate acts as a small heat sink in itself. Secondly, because aluminum is a good conductor, it passes the thermal energy from the TP2050s to the aluminum case. Although the inside of the enclosure will be above room temperature (25oC), it will still offer extra transfer of heat through convection to the aluminum case. Also, due to large surface area of the aluminum case, more of the heat will be transferred into the surrounding air by radiation. Ultimately, this will cause the case to be warm to the touch22, and will appropriately dispel of any heat that needs to be dissipated.

16. Grounding and EMC Considerations

One commonly overlooked factor in the design of circuits and printed circuit boards deals with proper grounding techniques and its effect on electro-magnetic compatibility. Henry Ott points out in this design paper “Ground – A place for Current to Flow23”, that ground is an often-neglected portion of circuit design and layout. According to his definition, ground is considered an equipotential point or plane that serves as a source or sink for current, and goes on to state that many designers don’t actually concern themselves with the path current takes to return to its source. Performance of a circuit can be significantly increased if a few simple considerations are taken into account when laying out ground routes. The first important consideration for proper grounding deals with the fact that current naturally returns to its source along the path of lowest impedance. Impedance is described as an opposition to current flow, and consists of both resistive (real) and reactive (imaginary) components.

By observing the flow of current from the picture on the left, we can track the current as it leaves the source and passes through the load resistance. But what happens after the load resistance is grounded? When presented with multiple impedance paths, the return current will take the 1! impedance path because it is less.

21 G. Randy Slone, The Audiophile’s Project Sourcebook (New York: McGraw-Hill, 2002) 280. 22 Winsome Labs, Jay Hennigan. Personal interview. 4 Aug. 2011. 23 Henry Ott, Ground – A Place for Current to Flow (New Jersey: Bell Laboratories, 1983) 1.

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This simple example can also be directly transferred into circuit board design. Of the two components dealing with an impedance path, the resistive portion will remain relatively constant. It can then be concluded that minimizing the impedance is mainly dependent on reactivity, and the main culprit behind reactive impedance can be directly linked to ground path inductance. This concept can be explained by considering the partial inductance of wires. The formula for partial inductance is shown in the following formula:

in Henries

Although this looks relatively complex, it still tells us two very important things. The inductive reactance is dependent on both rw (the radius of a trace or wire) and on l (length of the signal path). It was just shown that inductance is dependent on both trace width and the length of the signal path. It should also be pointed out that the overall signal path length is determined by the entire loop area (from source through ground back to source). The above formula also shows that this loop area has the most significant impact on partial inductance of a trace or wire. Therefore, allowing the current to return to its sources as locally and compactly as possible can minimize loop length. The use of a ground plane is a common solution that maximizes rw and minimizes the loop area. A ground plane can only be used with multi-layer boards, as it is an entire layer to itself. This has two noteworthy effects on ground loops. The first is that ground is now a large-radius plane. This will decrease the overall reactive impedance by increasing rw. Secondly, grounding to a plane will provide the signal path with an infinite amount of possibilities to reach the source in the shortest way possible. If a ground plane is used in a circuit board design, another important aspect of grounding needs to be considered. As explained in a previous section, Class-T amplification deals with both digital and analog signals. Sharing both signal types on the same ground plane will result in problems as high-level noisy digital signals contaminate low-level analog signals. Separating the digital ground currents from the analog ground currents is accomplished through mixed signal partitioning. One option for separating digital and analog signals is to completely separate the ground plane layer (shown on left). However, in complex designs such as a Class-T amplifier, there are many potential problems associated with doing this. The major problem is that traces cannot be routed over a split in the plane. This would result in an increase in radiation and crosstalk, and more importantly would result in a massive return loop24. As discussed previously, a larger return loop would result in increased overall inductance, ultimately affecting the ground loop impedance. A better option for separating the ground planes is to connect them at a single point (shown on right).

24 Clayton R. Paul, Introduction to Electromagnetic Compatibility (New Jersey: Wiley-Interscience, 2006) 358.

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Henry Ott pointed out that although there is a small connection between the two planes that it is actually a better layout. First of all, the ground planes are separated. Secondly, the traces that need to cross planes will not go over a split. Furthermore, Henry went on to explain that the return signal from the ground loop will not stray into a different ground plane and introduce noise, but will follow the traces as closely as possible due to magnetic field intensity created by a trace. All wires (or traces) produce some sort of magnetic field as current passes through them. The return currents are attracted to these magnetic fields, and so have a tendency to follow the source trace. The graph below shows how as return current distribution in a ground plane as a percentage of the current contained within an x/h distance from the center of the magnetic field produced by a trace. By considering ground as a low impedance path for a return signal, and applying the above material to a circuit board design, electromagnetic interference and any other unwanted radiations can be prevented with no extra cost.

17. PCB Layout

After selecting the components to be used in the design, the printed circuit board (PCB) layout began. The layout editor that was used in the project was the Easily Applicable Graphical Layout Editor (EAGLE). All component layout was done to try and adhere to EMC considerations, placing emphasis on proper grounding and component layout. The following screenshots document my progress in designing .brd file in EAGLE for a Class-T prototype. The following section shows my progress from a new .brd file through my final Tampv23 version. A printout of the power and ground planes were also added.

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4/17/2011 1:23:20 PM f=0.95 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv2.brd

+LEDMUTE

red

MCP101

MCP101

CH1- CH1+CH2+CH2- SLEEVETIP SLEEVESHUNTSWVCC SWGND SWPWR

TC2001

TK2050TP2050IN1

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C12-2

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4/17/2011 1:24:04 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv3.brd

+LE

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4/17/2011 1:25:18 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv4.brd

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H1

6.2k

Page 32: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:26:34 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv7.brd

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3CFB4

RFBB1RFBB2RFBB3RFBB4

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3

RCA4

RCA2

RCA1

TC20

01

TK20

50TP

2050

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4C7

CS

AL

CS

CE

R

CDM2

CZ1

CO2

CO1

CO

3C

O4 C

Z2

CDM1

RZ2

RZ1

CHBR1CHBR2CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C30-2

C14-2

C12-2

C18-2 C18-1

C12-1

C21-1C21-2

C31-1C31-2

C30-1

C14-1

R37-1R37-2

R40-1R40-2

LO1

LO2

LO3

LO4

IC1

COICCIIC

CS1

C1

HEATSINK

RV

CC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 33: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:26:51 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv7test.brd

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3CFB4

RFBB1RFBB2RFBB3RFBB4

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3

RCA4

RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7

CS

AL

CS

CE

R

CDM2

CZ1

CO2

CO1

CO

3C

O4 C

Z2

CDM1

RZ2

RZ1

CHBR1CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C30-2

C14-2

C12-2

C18-2 C18-1

C12-1

C21-1C21-2

C31-1C31-2

C30-1

C14-1

R37-1R37-2

R40-1R40-2

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS

1

C1

HEATSINK

RV

CC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 34: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:27:07 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv8.5.brd

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C18-1

C12-1 C21-1

C21-2

C31-1

C31-2

C30-1

C14-1

R37-1

R37-2

R40-1

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3

RCA4

RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7C

SA

L

CS

CE

R

CDM2

CZ1

CO2

CO1

CO

3C

O4 C

Z2

CDM1

RZ2

RZ1

CHBR1CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS

1

C1

HEATSINK

RV

CC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 35: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:27:22 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv8.brd

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C18-1

C12-1 C21-1

C21-2

C31-1

C31-2

C30-1

C14-1

R37-1

R37-2

R40-1

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3

RCA4

RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7C

SA

L

CS

CE

R

CDM2

CZ1

CO2

CO1

CO

3C

O4 C

Z2

CDM1

RZ2

RZ1

CHBR1CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS

1

C1

HEATSINK

RV

CC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 36: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:27:39 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv9.brd

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3

RCA4

RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7

CS

AL

CS

CE

R

CDM2

CZ1

CO2

CO1

CO

3C

O4 C

Z2

CDM1

RZ2

RZ1

CHBR1CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS

1

C1

HEATSINKR

VC

C

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 37: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:27:57 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv10.brd

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3

RCA4

RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7

CS

AL

CS

CE

R

CDM2

CZ1

CO2

CO1

CO

3C

O4 C

Z2

CDM1

RZ2

RZ1

CHBR1CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS

1

C1

HEATSINKR

VC

C

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 38: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:27:57 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv10.brd

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3

RCA4

RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7

CS

AL

CS

CE

R

CDM2

CZ1

CO2

CO1

CO

3C

O4 C

Z2

CDM1

RZ2

RZ1

CHBR1CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS

1

C1

HEATSINKR

VC

C

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 39: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:29:54 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv11.brd

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNTSWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS1

C1

HEATSINK

RV

CC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 40: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:30:15 PM \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv12.brd

MC

P101

MC

P101

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNTSWVCC

SWGND

SWPWR

CI2- CI2+

CI1+CI1-

+LE

DV

CC

blue

RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3RFBC4

C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS1

C1

HEATSINK

RV

CC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

Page 41: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:30:31 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv13.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

CI2- CI2+

CI1+CI1-

+LEDVCC

blue RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4

C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1CO

IC

CIIC

CS1

C1

HEATSINK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805TV.1uF

.33u

F

560uF

.1uF

H1

6.2k

Page 42: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/7/2011 4:53:11 PM f=1.54 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv14.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

CI2- CI2+

CI1+CI1-

+LEDVCC

blue RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4

C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 43: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:30:45 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv14.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

CI2- CI2+

CI1+CI1-

+LEDVCC

blue RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 44: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:31:00 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv15.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

CI2- CI2+

CI1+CI1-

+LEDVCC

blue RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 45: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:31:17 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv16.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

SWGND

CI2- CI2+

CI1+CI1-

+LEDVCC

blue RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 46: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:31:30 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv17.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

VCC

CI2- CI2+

CI1+CI1-

+LEDVCC

blue RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 47: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:31:45 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv18.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

VCC

CI2- CI2+

CI1+CI1-

+LEDVCC

blue RCA3 RCA4

RCA2RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 48: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:31:57 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv19.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

VCC

CI2- CI2+

CI1+CI1-

+LEDVCC

blueRCA3

RCA4RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3

CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 49: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:32:11 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv20.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

VCC

CI2- CI2+

CI1+CI1-

+LEDVCC

blueRCA3

RCA4RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CSC

18-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F

.1uF

15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH

7805

TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 50: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:32:25 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv21.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

VCC

CI2- CI2+

CI1+CI1-

+LEDVCC

blueRCA3

RCA4RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

HE

ATS

INK

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

JUMPERJUMPER1

JUMPER2

JUMPER3

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F.1

uF15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH78

05TV

.1uF

.33uF

560uF

.1uF

H1

6.2k

Page 51: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

4/17/2011 1:32:41 PM f=1.43 \\mtucifs\dfshome\zacarlso\eagle\TAmp Project\Tampv22.brd

TP2050

TP2050

500k

500k

500k

500k.1

uF

.1uF

470p470p390p

390p

1k1k1k1k

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

10k10k

TK2050

TP2050

ROFA1

ROFA2

ROFC2ROFC1

COF1

COF2

CFB1CFB2CFB3

CFB4

RFBB1RFBB2RFBB3RFBB4

C30-2

C14-2

C12-2

C18-2

C21-2

C31-1

C31-2

C30-1

C14-1

R37-2

R40-2

MC

P10

1

MC

P10

1

CH1-

CH1+

CH2+

CH2-

SLEEVE

TIP

SLEEVESHUNT

SWVCC

VCC

CI2- CI2+

CI1+CI1-

+LEDVCC

blueRCA3

RCA4RCA2

RCA1

TC20

01

ROFB1

ROFB2

RI1

RI2

RF1

RF2

R53

RR

EF

R54

RFBC1RFBC2RFBC3

RFBC4C7

CS

AL

CS

CE

R

CD

M2

CZ1

CO

2C

O1

CO

3C

O4

CZ2

CD

M1

RZ2

RZ1

CHBR1

CHBR2

CHBR3CHBR4

CHBR5

CHBR8

CHBR6CHBR7

CS

C18

-1

C12

-1

C21-1

R37

-1

R40

-1

LO1

LO2

LO3

LO4

IC1

COIC

CIIC

CS1

C1

RVCC

WIPER1 WIPER2

GROUND1 GROUND2

INPUT1 INPUT2

JUMPERJUMPER1

JUMPER2

JUMPER3

TC20

01

20k

20k

28k

28k

11k

8.2k

22k

.1uF

100u

F

.1uF

.1uF

.22u

F

.22u

F.2

2uF

.22u

F.2

2uF

.22u

F.1

uF15

15

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

.1uF

560uF

.1uF .1

uF

.1uF

10k

10k

15uH

15uH

15uH

15uH78

05TV

.1uF

.33uF

560uF

.1uF

6.2k

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18. Costs and Parts List The parts list for this project was too extensive too put into a document in this report. Eventually, the Excel sheet will be available on a Wordpress blog that is currently being designed. Until then, please take note of the attached Excel sheet to view all the component list. This will include information regarding retailers, manufacturers, and EAGLE library part numbers. You can also contact the designer at zacarlso.mtu.edu for more information. The final cost of this project (including shipping) was:

19. Performance and Testing

This section will be filled out once the amplifier is fully built.

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20. Bibliography

Beis, Uwe, “An Introduction to Delta Sigma Converters,” 2008, Electronics, 18 Apr. 2011 <http://www.beis.de/Elektronik/DeltaSigma/DeltaSigma.html>.

Coloms, Martin, “Piece de Resistance,” 1996, SAS Audio Labs, 24 Apr. 2011

<http://www.sasaudiolabs.com/resistor.htm>. Gee, Tony, “Capacitor Test,” 2011, Creative Commons, 24 Apr. 2011

<http://www.humblehomemadehifi.com/Cap.html>. Hennigan, Jay, Winsome Labs. Personal interview. 4 Aug. 2011. Kester, Walt, “ADC Architectures III: Sigma-Delta ADC Basics”, 2009, Analog Devices, MT-

022 Tutorial. Ott, Henry, Ground – A Place for Current to Flow (New Jersey: Bell Laboratories, 1983). Paul, R. Clayton, Introduction to Electromagnetic Compatibility (New Jersey: Wiley-

Interscience, 2006). Ross, Kevin, “The Basics,” 2009, Creative Commons, 24 Apr. 2011

<http://www.seattlerobotics.org/encoder/jun97/basics.html>. Slone, G. Randy, The Audiophile’s Project Sourcebook (New York: McGraw-Hill, 2002). Stutz, Michael, “Practical Considerations of ADC Circuits,” 2000, Design Science Liscense, 18

Apr. 2011 <http://www.allaboutcircuits.com/vol_4/chpt_13/10.html>. Tripath Technology, Inc, TK2050 Technical Information (Revision 1.1 – October 2002). "Q Factor," 2011, Wikipedia, 30 Apr. 2011

<http://en.wikipedia.org/wiki/Q_factor#Q_factor_and_damping>. Zed Audio, “Capacitors,” 2005, Zed Audio Corporation, 24 Apr. 2011

<http://www.zedaudiocorp.com/Technical/Capacitors.htm>. "Decoupling Capacitor," 2011, Wikipedia, 24 Apr. 2011

<http://en.wikipedia.org/wiki/Decoupling_capacitor>. "Digital Signals," 2011, Wikipedia, 18 Apr. 2011 <http://en.wikipedia.org/wiki/Digital_signal>. "Line Level," 2011, Wikipedia, 24 Apr. 2011 <http://en.wikipedia.org/wiki/Line-level>. “Sigma-Delta ADC Tutorial”, 2011, Analog Devices, 18 Apr. 2011

<http://designtools.analog.com/dt/sdtutorial/sdtutorial.html>.

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21. Appendix

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Page 59: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

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Page 62: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

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Page 63: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

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Page 64: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

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Page 65: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

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Page 77: wiki.vpa.mtu.eduwiki.vpa.mtu.edu/wiki/images/e/e7/FINALReport.pdf · Contents Page 1. Introduction and Project Objectives 2. Analog and Digital Signals 3. ADC and DAC Conversion Theory

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