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January 2014 2

Agilent Technologies

Welcome

Matt Ozalas

RF Power Amplifier

Design Engineer

Agilent EEsof EDA

J. Scott Gatley

Associate VP of

Marketing and Sales

WIN Semiconductors Corp

http://www.winfoundry.com/en_US/index.aspx

Overview

Matthew Ozalas

[email protected]

RF Power Amplifier Design Engineer

© 2014 Agilent Technologies, Inc.

3

Thermal issues cause significant problems for today's RF power amplifier (PA) designs

implemented in GaAs, GaN, SiGe and other IC processes. Fortunately, new design tools

and techniques based on electro-thermal analysis can help designers identify and correct

thermal problems before it's too late. This webcast illustrates a PA design methodology that

utilizes the combination of electro-thermal simulation technology from Agilent EEsof EDA,

and electro-thermal-enabled process design kits (PDKs) from WIN Semiconductor. The

design methodology is used to reduce thermal impairments and improve performance of a

three-stage PA for WLAN applications using WIN's HO2U HBT Process.

Agenda

Introduction to thermal considerations in RF Power Amplifiers (from a design-centric perspective):

• The Basics: Heating in Active Devices

– Self Heating / Mutual Heating / Time Varying Heating

• Typical Thermal Considerations in PA design – Reliability /Device Level Performance / Memory Effects

• PA Design Example and Electro-thermal Simulation – WIN Process Overview

– 3 Stage PA / Output Cell Design / Active Bias Network Design / Layout


4

Thermal Resistance, in °C/W: Converts the power

dissipated through the device into the operating

temperature of the device.

Self Heating


5

PdissRTT thambientdevice *

)2(

)2(ln

)(2

1

sub

sub

tLW

tWL

WLRth

Material κ (W/cm•K)

GaAs 0.46

GaN 1.3

SiC 3.5

Si 1.5

Ge 0.6

(κ is a function of T!)

(This equation applies for a rectangular geometry with

Length and Width and substrate thickness)

Thermal

Conductivity

Mutual Heating


6

Parallel Devices

TOP VIEW

SIDE VIEW IC Substrate

Thermal Epoxy

Heat Sink

or PCB w/

Thermal VIAs

Active Devices

Can view this in a similar

manner as S-Matrix

1 2 3 333231

232221

131211

RRR

RRR

RRR

Rij

Self Heating

Terms Usually less interaction

between non-adjacent

terms (lower R)

j

iij

P

TR

Thermal R’s

add in series

~10 °C/W

~20 °C/W

Values used in this

example work

Time Varying Heating


7

ththth CR

Thermal Time Constant: Time it takes

for the heat generated to build to

steady state or to dissipate

Single Time Constant Example (Rth/Cth1 only):

Pulsed GSM Signal at 1/8 Duty Cycle

Pulse=580us

Rise=28 usec

Intrinsic Device

temp tracks RF

power burst well

Thermal Network is modeled as a RC

Network(s) for fast pulses

Intrinsic Device ~ns to us

Die or Wafer

Package

~ms

~s

Die + Device

temp delayed in

responding

Thermal Considerations in PA Design

Long Term Failure

Device Performance

Thermal Stability

Memory Effects


8

Self Heating

Mutual Heating

Time Varying Heating

Designing for Long Term Reliability


9

http://www.nitronex.com/pdfs/AN-012%20Thermal.pdf

kT

Ea

CeMTTF

Important Observations:

• Time to failure is log-related to junction temperature

– Estimate of Tj crucial to design for reliability

• Verification is typically done using accelerated lifetime testing (ALT)

– Testing typically on the order of hundreds to thousands of hours

– Involves testing at higher device temperatures

– Can involve also increasing device current density / operating voltage

• IE: MTTF α Je-n

• MTTF Requirement

– Handset ~104 hours

– Base Station ~106 hours

– Instrumentation / Aerospace >>106

Arrhenius’ Equation

General Form

Nitronex GaN

Device

(Mean Time to Failure)

Device Electrical Considerations

GaAs HBT

• Moderate Power and Current Density

– Handset: Size/Cost

• Vbe (↓) vs. Temperature (↑)

• Beta (↓) vs. Temperature (↑)

– Different than standard Si BJT!

GaN

• High Power and Current Density

• Base Station: Cooling System / Heatsink

– VGSQ (↑) vs. Temp (↑)

• Or IDS (↓) vs. Temp (↑)


10

dT

dVbeRthVc

R

Ic

V

dIc

dV

dT

dVbe

dIc

dT

dIc

dVbe

dIc

dV

dIc

dV

gmd

BTbe

IcT

be

be

**

0*

01

Runaway Heating (GaAs)


11

Introduction of base ballast R stabilizes device

(Blue and pink curves)

Tradeoffs: IR Drop @ Base Node

Slightly Lower PAE due to Ib*Rb

VcIcRthTT A *

BT RIc

Is

IcVVbe ln

Condition for

Thermal runaway:

gm goes infinite!

or 1/gm goes to zero

Typically

-1.1 mV/C

Ic↑

T↑ Vbe↓

Turn

Bias

on

Device Draws Current

Device

Heats Up

Vbe Drops

Positive Term Negative Term

Here we assume that

ballast is intrinsically

part of the device

(so Vb includes the

ballast resistance)


12

Memory Effects

• Common causes of Memory Effects in Power Amplifiers:

– Bias Network Impedance at Modulation Frequency

– Device Level Phenomena (Dispersion and Trapping)

– Electrothermal :

12

Full Electro-Thermal Simulation

13

Iteration loop is

done automatically

until powers and

temperatures are

self-consistent

Circuit Simulator

Read temperatures

Solve electrical equations

Write power dissipation

Thermal Simulator

Read power dissipation

Solve thermal equation

Write temperatures PDISS

TDEVICES

Thermal

technology

files


WIN Semiconductors

Technology Overview

February 2014

15 WIN Semiconductors

Founded October 1999 – based Taipei, Taiwan

Two 150mm GaAs fabs with 25,000 wfr. monthly capacity

Pure-play manufacturer of ICs for wireless communication

Successful IPO in Taiwan, Dec. 2011

Leading III-V semiconductor manufacturer worldwide

WIN Corporate Profile


High Volume Production

Fab A - Broad range of technologies

Fab B - Volume GaAs, GaN, Cu Pillar, Test,

and QFN pkg.

WIN delivered more than 2.5B RF chips in

2012

Cellular, WiFi, and non-consumer markets


Econom

ies o

f S

cale

Economies of Scope

High Volume

Low Volume

GSM PA

GSM

Switch

(W)CDMA

PA

Wi-Fi PA &

Switch

Infrastructure

VSAT

CATV

Fiber-optic

Defence

Diversified Markets

Diversified Technology

Diversified Applications

Diversified Markets & Products

Lower Profitability Risk

Instrumentation


HBT pHEMT

BiHEMT (H2W) Services

HBT pHEMT

• Integration technology (HBT + pHEMT)

• Integrate PA, switch, LNA and control

logic

RF Power

Amplifier (PA)

for:

• Mobile phone

• GSM

• WCDMA

• Wi-Fi (WLAN)

• LTE

Switches for:

• Mobile phone

• Wi-Fi (WLAN)

High

Frequency (10-

100 GHz)

power

amplifier and

low noise

amplifier

• Die level DC test

• RF test

• Cu Bumps

• QFN Packaging -

Proto/Low Volume

Characterization:

• Power

• Noise

• Linearity

WIN Technology


WIN Technology Portfolio HBT

4th generation HBT - die shrink, improved ruggedness

1um MMIC VCO process

Enhancement/Depletion (E/D) pHEMT 2nd and 3rd generation 0.5um E/D pHEMT

0.25um E/D pHEMT technology released Dec 2011

BiHEMT 2um HBT combined with 0.5um E/D pHEMT (‘H2W’)

0.5um D-mode pHEMT & HFET Microwave PA, CATV processes, High linearity Switches

Short gate length, high performance pHEMT 0.25um, 0.15um and 0.1um pHEMT MMIC processes

GaN on SiC 0.25um, 28V released; Developing 0.5um, 50V, and sub-0.25um


WIN Power Amp Technlogies

PP25-21 PP15-50/51 PP15-12/22 PL15-12 PP10-10/11

Gate length 0.25 μm 0.15 μm 0.15 μm 0.15 μm 0.1 μm

Operating Frequency

Up to 20GHz Up to 30 GHz Up to 30 GHz Up to 60 GHz Up to 90GHz

Max Drain Bias 8 V 6 V 5V 4 V 4 V

Idmax(Vg=0.5V) 490 mA/mm 620 mA/mm 630 mA/mm 600 mA/mm 760 mA/mm

Peak Gm 410 mS/mm 460 mS/mm 490 mS/mm 490 mS/mm 725 mS/mm

Vto -1.15 V -1.35 V -1.35 V -0.7 V -0.95 V

BVGD 20 V (18V min) 16V (14V min) 11 V (9V min) 9 V (8V min) 9 V (8V min)

fT 65 GHz 90 GHz 90 GHz 100 GHz 130 GHz

fmax 190 GHz 185 GHz 185 GHz 150 GHz 180 GHz

Power Density (2X75μm)

1100 mW/mm

@ 8V, 10GHz

870 mW/mm

@ 6V, 29GHz 800 mW/mm

@ 5V, 29GHz

345 mW/mm

@ 3V, 29GHz

860 mW/mm

@ 4V, 29GHz

(2X50μm) 830 mW/mm

@ 6V, 29GHz

(4X75μm)


WIN PA Technologies (2)

PP50-12

0.5μm Double Recess Power PHEMT

8V operation

Vt=-1.5V, Gm=200 mS/mm, IDSS ~350 mA/mm, VB=22V, ft=35 GHz

P1dB >900mW/mm @ 10 GHz, >50%PAE

Used for 10-20W power amplifiers

HBT

Multiple families for handset an infrastructure PAs


Electro-Thermal Simulation

PDKs provided for all WIN Semiconductors technologies

Electro-Thermal Analysis

WIN - First foundry to support electro-thermal simulation in ADS - October 2013

Close collaboration with Agilent

PDKs updates for on HBT-based technologies

Expanding to pHEMT

Thermal Technology File

WIN PDK

Thermal Technology File

• Defines thermal conductivity and volumetric

heat capacity for each material in the

process

• Defines where heat is dissipated for each

device (heat source) in the process


WIN Summary

WIN has grown to become the world’s largest leading manufacturer of GaAs MMICs Clear, simple business model only servicing customer’s product

development & production

Broadest breadth of technology, largest installed manufacturing capacity

Continued investment in capacity and technology

4th generation HBT, new BiFET, 0.25 m E/D, 0.1 m pHEMT

Cu pillar, TKS QFN plastic packaging, GaN

Electro-Thermal simulations in Aglient ADS PDKs

25

Context for PA Design

PA

WIN HBT Process

Product (Module) Layout

Switch Ctrl

PA IC: WIN HBT Process

PA Schematic

WLAN Product Diagram


Brief Overview of Full Power Amplifier

• Target: 802.11g (2.42 GHz), P1dB>31 dBm, G>30 dB, PAE>50%@P1dB

26

M=6

M=36


Extraction of Static Thermal Parameters

• Most device models include self heating parameters

– Relatively easy to extract thermal parameters from static models…

27

Simple DC simulation

Sweep temperature

Thermal R (varies w/ T, P)

Thermal C

Transient Bias Sim

Fast Rise Time on IB

(@85C)

Transient Value =

Static DC Value


Output Stage: Initial Design Approach

28


Output Stage: Implementation

• Simulate and calculate Tj by hand: Tj=85+(0.71*((406/36)+30)=114.3 °C

29

ETH Simulation shows peak

array temperature of 131.5 °C

@ Pout = 31 dBm

Electro-thermal simulation

has lower gain due to hotter devices

(Pdiss=Pdc + Pin_rf - Pout_rf)


Current Hogging

30

500 Ohm Base Ballast

Full Array current balance (w/ 250 and 350 ohms base ballast per finger)

1

2

3

4

5

6

1

2

3

4

5

6

No Base Ballast

Higher Rb leads to tighter

device current distribution

Icdev vs. Ibarray

Middle Devices

steal current Current Balanced

across devices


Device Review: Bipolar Heterojunction

31

P-N Diode Rectification:

)2cos(22

)cos(*

);2cos1(5.0cos...)(cos)cos(*:

)cos(*

...

2

1

2

112,

222

11

2

21

/

tvava

tvaI

AAtvatvaIOutput

tvviLet

vavaIeII

D

D

iio

VTVD

sD

Strong RF signal on base creates rectified DC current

Band Diagram of HBT

Forward Biased

PN Heterojunction

Reverse Biased

PN Junction Majority electrons flow from the

emitter to the base across the

forward biased PN diode,

where they become minority

carriers and are swept across

the reverse biased base

collector diode


Bias Network Design

32

Device “turns off”:

Gain Compresses

I-Source

Topology

Active

Top-

ology

Bias Point Dynamically Adjusts

Gain Expands

DC Current Increases

with RF drive

DC Current is Static


At a lower temp,

the mirror Vbe

is higher

33

Temperature Dependence

“Beta Helper” Topology

rfRbmir VbeVVbe

Vbe vs. Temperature, WIN device

)(ln1

)(ln

)(ln

**

TIs

Ic

r

RbVVbe

TIs

IcV

TIs

IcgmRbVVbe

VbeVVbe

rf

rf

Trfm ir

rf

rf

Trf

rf

rf

Trfm ir

rfRbmir

Well known characteristic

of PN junction diodes:

Diode voltage is CTAT

(complementary to absolute

temperature), driven by the

saturation current Is

↓T, ↑V ↑Ic

Assume that the mirror device

has a lower temperature than

the RF device…

Then the current in the RF

device must increase to

match the new Vbe set point (Rb will counteract this effect slightly)


34

Layout and Gain Compression

• To track Vbe, mirror reference is set as a sub-multiple of the main array

• To achieve high PAE, reference current Iref is minimized

– The current density of the mirror device typically is lower than the current density of the RF

device (mirror will run cooler than the main array)

• If the mirror is placed close to the RF array, the temperature of the mirror reference

device is usually dominated by mutual heating from the RF array

• The physical placement of the mirror device impacts RF compression

Main

RF Array Thermally Coupled

Bias Device

M=36

Ic=500 mA

nc~65%

M=2

Ic=3 mA

~5 mA/dev

1.5 mA

/dev

Jcmir ≠ Jcrf


More on Multistage PA Design

• To achieve flat gain profile (AM/AM and AM/PM), driver stages are typically

designed to act as predistorters for the power stage

• The shape of the gain and phase compression characteristic dictate output

distortion (ACLR & EVM)

35

Stage 2 Compresses

Stage 3 Expands

Stage 3 Lags

Stage 1 Leads

Flat Gain Response

Flat Phase Response


Case Study: Electro-thermal Simulation

• Here we have two WLAN PA layouts to demonstrate the differences between

simple self heating and full electro-thermal analysis. The three conditions are:

– Simple Self Heating Simulation

– Electro-thermal Simulation with moderately thermal-coupled bias networks

– Electro-thermal Simulation with a poorly thermal-coupled bias networks

S2

S3

S1

S2

S3

S1

Moderately Coupled Bias Networks Poorly Coupled Bias Networks


37

Self Heating

Moderate T Coupling

Poor T Coupling

Total Phase Shift

Poor T Coupling

Self Heating

Moderate T

Coupling

Hottest RF Device

Coolest RF

Device

Mirror

Device

Tamb=25C


Back to Reliability…

• Temperature is hotter in the PA than our original estimate by ~35°C

– PA is less efficient at slightly lower Pout

– Bias network and driver stage interactions need to be considered too…

• Thermally decoupling the mirror device causes the PA to run hotter

– If Tmir<Trf, Ibias ↑…. leading to Trf ↑ …. causing Tmir<Trf… leading to Ibias ↑

• To get a good estimate of max temperature, we need to consider the full

PA, with the bias network, over a wide power range –

38

Max Temp

of moderate

coupled bias

(Full PA)

Self Heating=Red

Moderate Coupling=Blue

Poor Coupling=Pink


Layout and Memory Effects

39

• Consider a temperature isolated mirror device (A):

– On the upramp, the RF device is only marginally hotter than the mirror

– But on the downramp, the RF device is much hotter than the mirror

• To minimize memory effects, the devices should be thermally coupled (B)

Bias Configuration

Trf>Tmir, Ibias↑

Mirror RF


Thermal Memory Effects

40

Single Device’s Thermal Response to fast pulse, ETH Simulation

(each trace is a different transient sim on a different time scale--

we apply a stepped bias and watch the device heat up)

Device Level Models

usually capture only

rise on this scale!

Bias Device

Power Device

Power Device

Bias Device

(Log Scale)

Time scale for this example!

0.4 dB

0.2 dB

0 dB

Red=Self Heating

Pink=Poorly Coupled Bias Networks

Blue=Moderately Coupled Bias Networks

Self heating model does

not react on this time scale!

Pout (dBm)

Ga

in (

dB

)


41

Summary

Areas where electro-thermal simulation is important for RF Power Amplifier Design:

• Reliability – Mutual heating can lessen long term lifetime substantially

– PA level interactions can result in hotter devices than initially predicted by hand calculations

• Initial hand estimate: 114°C, actual full PA value: 168°C

• Balancing Heat and Current in Power Devices – Minimum ballast values to avoid runaway likely still lead to current imbalance

• Device Performance – Placement of Bias Networks relative to RF devices impacts overall amplifier

performance, and level of coupling depends on application:

• Gain Compression / Output Spectrum / Memory Effects


References and Acknowledgements

Thanks to Rick Poore and Mike Glasbrener for review and

extensive technical discussion!


42

Rth Geometry Dependence: “A Study of New Base Pushout Effects in Modern Bipolar Transistors”, PhD Thesis, UCLA,

1997, Zampardi

Reliability and Operating Lifetime: “Power Amplifier Reliability”, IMS2011 Presentation, (Menozzi IEEE)

Ballasting: “Current Gain Collapse in Microwave Multifinger Heterojunction Bipolar Transistors Operated at Very High Power

Densities”, (Liu et al., IEEE)

Rth Extraction: “Direct Extraction Technique to Derive the Junction Temperature of HBT’s under High Self Heating Bias

Conditions” (Marsh IEEE)

Thermal Coupling and Topology: “Thermal Coupling in Integrated Circuits: Application to Thermal Testing” (Altet et. al,

IEEE)

…. For more information, see these other MWJ Webcasts:

For the Technology Surrounding the PA: “Beyond CMOS vs. GaAs, Finding the Best Technology Mix for a Handset PA”

For Electro-thermal Simulation: “Integrated Electro-Thermal Solution Delivers Thermally Aware Circuit Simulation”

You are invited to our next webcast


43

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ADS Product Planner

Agilent EEsof EDA

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