EE141

1

EE141EE141--Fall 2011Fall 2011Digital Integrated Digital Integrated CircuitsCircuitsCircuitsCircuits

TuThTuTh 1111--12:3012:30

Instructor: Borivoje Nikolić

EE141EECS1411

241 Cory241 Cory

What is this class all about?What is this class all about?

Introduction to digital integrated circuit design. Models concepts metrics constraintsModels, concepts, metrics, constraints What constitutes a good design

What will you learn? Understanding, designing, and optimizing digital

circuits with respect to different quality metrics: cost, speed, power dissipation, and reliability

Practical design using state-of-the-art tools

EE141EECS1412

EE141

2

Practical InformationPractical Information

Instructor Prof Borivoje NikolićProf. Borivoje Nikolić

550B Cory Hall, 643-9297, bora@eecsOffice hours: M 11am-12pm, Th 1-2pm

TAs: Matthew Weiner, mgweiner@eecs

Office hours: Tu 2-3pm, TBD Matthew Spencer, mespence@eecs

Office hours: W 3-4pm, TBD

Web page:

EE141EECS1413

p ghttp://bwrc.eecs.berkeley.edu/Classes/ICDesign/EE141_f11/

Discussions and LabsDiscussions and Labs

Discussion sessionsM 5 6 M tt W i 299 C M 5-6pm, Matt Weiner, 299 Cory

F 2-3pm, Matt Spencer, 299 Cory Same material in both sessions!

Labs (125 Cory – Not 353 Cory) M 3-6pm Tu 3-6pm Computers to the left of entrance doors

EE141EECS1414

Computers to the left of entrance doors

Please choose one lab session and stick with it!

EE141

3

M

8 9 10 11 12 1 2 3 4 5 6

Lab(Matt S.)125 Cory

OH(Bora)

550B Cory

Your EECS141 WeekYour EECS141 Week

DISC*(Matt W.)

299 Cory

TAmtgT

W

R

Lab(Matt W.)

125 Cory

Lec(Bora)241 Cory

ProblemSets Due

Lec(Bora)

OH(B )

OH(Matt S.)

TBD

OH(Matt W.)

TBD

EE141EECS1415

R

FDISC*

(Matt S.)299 Cory

(Bora)241 Cory

* Discussion sections will cover identical material

(Bora)550B Cory

Class OrganizationClass Organization

~9 Assignments

One design project with three phases

Labs: 5 software, 1 hardware

2 midterms, 1 final Midterm 1: Wednesday, October 5, evening

EE141EECS1416

Midterm 2: Thursday, November 3, evening

Final: Wednesday, December 14, 8-11am

Visit to a company in November (likely)

EE141

4

Some Important AnnouncementsSome Important Announcements

Please don’t bring food/drinks to 125 Cory Designated round table Designated round table

Lab rules: http://california.eecs.berkeley.edu/iesg/labs/labinfo/labrules.asp

Lab reports due one week after the lab

Please use the newsgroup for asking questions (Piazza)

Project is done in pairs

EE141EECS1417

Project is done in pairs

Labs, homework is done individually

No late submission

Don’t even think about cheating!

Grading PolicyGrading Policy

Homeworks: 10%

Labs: 10%

Projects: 20%

Midterms: 30%

Final: 30%

EE141EECS1418

EE141

5

Class MaterialClass Material

Textbook: “Digital Integrated Circuits – A D i P ti ” 2nd d b J R b ADesign Perspective”, 2nd ed, by J. Rabaey, A. Chandrakasan, B. Nikolić

Class notes: Web page Lab Reader: Web page Check web page for the availability of tools

EE141EECS1419

WebcastWebcast

The class is available on webcast.berkeley.edu Screencast and audio podcast available

EE141EECS14110

EE141

6

The Web SiteThe Web Site

Class and lecture notes

Assignments and solutions

Lab and project information

Exams

Many other goodies …

The sole source of information

EE141EECS14111

The sole source of information http://bwrc.eecs.berkeley.edu/icdesign/eecs141_f11

Print only what you need: Save a tree!

SoftwareSoftware

Cadence Widely used in industry

Online tutorials and documentation

HSPICE for simulation

EE141EECS14112

EE141

7

Getting StartedGetting Started

Assignment 1: Getting SPICE to work –see web-page

Due next Thursday, September 1, 5pm

NO discussion sessions or labs this week.

EE141EECS14113

First discussion sessions in Week 2 (M)

First software lab in Week 3

Important AnnouncementImportant Announcement

No lecture next Tuesday (Sept 30)

Makeup lecture tomorrow: Friday, Sept. 26, 3pm in 540AB Cory

EE141EECS14114

EE141

8

Digital Integrated CircuitsDigital Integrated Circuits

Introduction: Issues in digital designTh CMOS i t The CMOS inverter

Combinational logic structures Sequential logic gates Design methodologies Interconnect: R, L and C Timing

EE141EECS14115

Timing Arithmetic building blocks Memory and array structures

IntroductionIntroduction

Why is designing digital ICs different today than it was before?

Will it change in future?

EE141EECS14116

future?

EE141

9

The First ComputerThe First Computer

The Babbage

EE141EECS14117

The Babbage Difference Engine 25,000 parts

cost: £17,470

ENIAC ENIAC -- The First Electronic Computer (1946)The First Electronic Computer (1946)

EE141EECS14118

EE141

10

The Transistor RevolutionThe Transistor Revolution

EE141EECS14119

First transistorBell Labs, 1948

The First Integrated Circuits The First Integrated Circuits

Bipolar logicp g1960’s

EE141EECS14120

ECL 3-input GateMotorola 1966

EE141

11

Intel 4004 MicroprocessorIntel 4004 Microprocessor

Intel, 1971.2 300 transistors (12mm2)2,300 transistors (12mm2)740 KHz operation (10m PMOS technology)

EE141EECS14121

Intel Pentium 4 MicroprocessorIntel Pentium 4 Microprocessor

Intel, 2005.125 000 000 transistors 125,000,000 transistors (112mm2)3.8 GHz operation (90nm CMOS technology)

EE141EECS14122

EE141

12

Intel Core 2 MicroprocessorIntel Core 2 Microprocessor

Intel, 2006.291 000 000 transistors 291,000,000 transistors (143mm2)3 GHz operation (65nm CMOS technology)

EE141EECS14123

Intel Xeon (E7Intel Xeon (E7--8800)8800)

Intel, 2011.2 600 000 000 transistors 2,600,000,000 transistors (513mm2)2.4 GHz operation (32nm CMOS technology)

EE141EECS14124

EE141

13

Intel 22nm Test Chip (2009)Intel 22nm Test Chip (2009)

Intel, ~2009.2 900 000 000 transistors 2,900,000,000 transistors 364Mb memory array

EE141EECS14125

0.092μm2 SRAM cell

Some Major ChangesSome Major Changes

Transistors are changing shape

EE141EECS14126

32nm transistors 22nm transistors

Intel

EE141

14

Moore’s LawMoore’s Law

In 1965 Gordon Moore noted that theIn 1965, Gordon Moore noted that the number of transistors on a chip doubled every 18 to 24 months.

He made a prediction that i d h l ill d bl i

EE141EECS14127

semiconductor technology will double its effectiveness every 18 months

Moore’s LawMoore’s Law

1615IO

N

1413121110

9876543L

OG

2 O

F T

HE

NU

MB

ER

OF

ON

EN

TS

PE

R I

NT

EG

RA

TE

D F

UN

CT

I

EE141EECS14128

210

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

CO

MP

O

Electronics, April 19, 1965.

EE141

15

Evolution in ComplexityEvolution in Complexity

EE141EECS14129

1000

10000

Transistor Counts in Intel's Microprocessors

Core2

Transistor CountsTransistor Counts

0 1

1

10

100

1000

nsi

sto

rs [i

n m

illio

ns]

80286 386DX

486DX486DX4

Pentium

Pentium Pro

Pentium II

Pentium MMX

Pentium III

Pentium 4

Itanium

Itanium II i7

EE141EECS141

0.001

0.01

0.1

1970 1975 1980 1985 1990 1995 2000 2005 2010

Tran

4004

8008 8080

8086

8088

30

Doubles every 2 years

EE141

16

10000

Frequency Trends in Intel's Microprocessors

Pentium III

Pentium 4 Core2

i7

FrequencyFrequency

Has been doubling

10

100

1000

Fre

qu

ency

[MH

z]

8086

8088

80286

386DX

486DX486DX4

Pentium

Pentium Pro Pentium II

Pentium MMX

Pentium III

ItaniumItanium II

i7Has been doublingevery 2 years

Nearly flat

EE141EECS141

0.1

1

1970 1975 1980 1985 1990 1995 2000 2005 2010

F

4004

8008

8080

8088

31

1000

Power Trends in Intel's Microprocessors

Power DissipationPower Dissipation

10

100

Po

wer

[W

]

808680286 486DX

Pentium

Pentium Pro

Pentium II

Pentium III Pentium 4

ItaniumItanium II Core 2

i7

Has been > doublingevery 2 years

EE141EECS141

0.1

1

1970 1975 1980 1985 1990 1995 2000 2005 2010

4004

80088080

8088386DX

32

Has to stay ~constant

EE141

17

Not Only MicroprocessorsNot Only Microprocessors

CellPhone

Digital Cellular Market(Phones Shipped)

1996 1997 1998 1999 2000

PowerManagement

Small Signal RF

PowerRF

EE141EECS14133

Units 48M 86M 162M 260M 435M Analog Baseband

Digital Baseband

(DSP + MCU)

(data from Texas Instruments)(data from Texas Instruments)

Why Scaling?Why Scaling? Technology shrinks by 0.7/generation With every generation can integrate 2x more

functions per chip; chip cost does not increase significantly

Cost of a function decreases by 2x But … How to design chips with more and more functions? Design engineering population does not double every

EE141EECS14134

Design engineering population does not double every two years…

Hence, a need for more efficient design methods Exploit different levels of abstraction

EE141

18

Challenges in Digital DesignChallenges in Digital Design

DSM 1/DSM

“Microscopic Problems”• Ultra-high speed design• Interconnect• Noise, Crosstalk• Reliability, Manufacturability• Power Dissipation• Clock distribution

“Macroscopic Issues”• Time-to-Market• Millions of Gates• High-Level Abstractions• Reuse & IP: Portability• Predictability• etc.

DSM 1/DSM

EE141EECS14135

Clock distribution.

Everything Looks a Little Different…and There’s a Lot of Them!

?

Productivity TrendsProductivity Trends

1,000,000

10,000,000

10,000,000

100,000,000

Logic Tr./ChipTr./Staff Month.

10,000

1,000

er C

hip

(M)

10,000

100,000

Mo

.

1

10

100

1,000

10,000

100,000

33 5 3 5 5

10

100

1,000

10,000

100,000

1,000,000

xxx

xxx

x

21%/Yr. compoundProductivity growth rate

x

58%/Yr. compoundedComplexity growth rate

100

10

1

0.1

0.01

0.001

Lo

gic

Tra

nsi

sto

r p

e

0.01

0.1

1

10

100

1,000

Pro

du

ctiv

ity

(K)

Tran

s./S

taff

-M

Co

mp

lexi

ty

EE141EECS14136

2003

1981

198 3

1985

1987

1989

1991

199 3

1995

1997

1999

2001

2005

2007

2009

Source: Sematech

Complexity outpaces design productivity

Courtesy, ITRS Roadmap

EE141

19

Design Abstraction LevelsDesign Abstraction Levels

SYSTEM

+

CIRCUIT

GATE

MODULE

EE141EECS14137

n+n+S

GD

DEVICE

This ClassThis Class

Introduces basic metrics for design of i t t d i it h t d lintegrated circuits – how to measure delay, power, etc.

Groups layout rectangles into transistors and wires Transistors and wires into gates Gates into functions

EE141EECS14138

(Functional blocks into systems) – e.g. EECS150

Need to verify that the assumptions are valid

EE141

20

Next LectureNext Lecture

Introduces basic metrics for design of integrated circuits – how to measure delay, power, cost, etc.

Brief intro to IC manufacturing and design

R b It i t !

EE141EECS14139

Remember: It is tomorrow!