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The MOS TransistorMOS Transistor Model

EE141- Spring 2005Lecture 4

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Today’s lecture

Basic MOS transistor operationLarge-signal MOS model for manual analysisThe CMOS inverter at a first glance

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Important!

Labs start next weekYou must show up in one of the lab sessions next weekIf you don’t show up you will be dropped from the class» Unless you let me know that you still want to be in

the classHomework 2 due next Thursday, February 3.

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What is a Transistor?

VGS ≥ VTRon

S D

A Switch!

|VGS|

A MOS Transistor

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Switch Model of CMOS Transistor

Ron

|VGS| < |VT||VGS| > |VT|

|VGS|

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NMOS and PMOS

V GS0

NMOS Transistor

S D

G

S D

G

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The MOS Transistor

Polysilicon Aluminum

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MOS Transistors -Types and Symbols

D

S

G

D

S

G

G

S

D D

S

G

NMOS Enhancement NMOS

PMOS

Depletion

Enhancement

B

NMOS withBulk Contact

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Threshold Voltage: Concept

n+

p-substrate

DSG

B

VGS+

–

Depletionregion

n-channel

n+

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The Threshold Voltage

Threshold

Fermi potential

2φF is approximately - 0.6V for p-type substratesγ – the body factorVT0 is approximately 0.45V for our process

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The Body Effect

-2.5 -2 -1.5 -1 -0.5 00.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

0.85

0.9

VBS

(V)

VT (V

)

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The Drain CurrentCharge in the channel is controlled by the gate voltage:

Drain current is proportional to charge and velocity:

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The Drain Current

Combining velocity and charge:

Integrating over the channel:

Transconductance:

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Transistor in Linear

n+n+

p-substrate

D

SG

B

VGS

xL

V(x) +–

VDS

ID

MOS transistor and its bias conditions

Linear (Resistive) mode

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Transistor in Saturation

n+n+

S

G

VGS

D

VDS > VGS - VT

VGS - VT+-

Pinch-off

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Saturation

For VGD < VT, the drain current saturates

Including channel-length modulation

( )22 TGSn

D VVLWkI −

′=

( ) ( )DSTGSnD VVVLWkI λ+−

′= 1

22

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Modes of Operation

Cutoff:

VGS < VT ID = 0

Resistive:

VT < VGS ; VGS − VT > VDS

( )22 TGSn

D VVLWkI −

′=

Saturation:

VT < VGS ; VGS − VT < VDS

( )

−−

′=

22

2DS

DSTGSn

DVVVV

LWkI

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Current-Voltage RelationsA Good Ol’ Transistor

QuadraticRelationship

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VDS (V)

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

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A model for manual analysis

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Current-Voltage RelationsThe Deep-Submicron Era

LinearRelationship

-4

VDS (V)0 0.5 1 1.5 2 2.5

0

0.5

1

1.5

2

2.5x 10

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Early Saturation

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Velocity Saturation

ξ (V/µm)ξc = 1.5

υn

(m/s

)υsat = 105

Constant mobility (slope = µ)

Constant velocity

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Velocity Saturation

IDLong-channel device

Short-channel device

VDSVDSAT VGS - VT

VGS = VDD

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ID versus VGS

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10

-4

VGS(V)

I D(A

)

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

VGS(V)I D

(A)

quadratic

quadratic

linear

Long Channel Short Channel

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ID versus VDS-4

VDS(V)0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

0 0.5 1 1.5 2 2.50

1

2

3

4

5

6x 10-4

VDS(V)

I D(A

)

VGS= 2.5 V

VGS= 2.0 V

VGS= 1.5 V

VGS= 1.0 V

Resistive Saturation

VDS = VGS - VT

Long Channel Short Channel

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Including Velocity Saturation

Approximate velocity:

And integrate current again:

In deep submicron, there are four regions of operation:(1) cutoff, (2) resistive, (3) saturation and (4) velocity saturation

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Regions of Operation

Long Channel Short Channel

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An Unified Modelfor Manual Analysis

S D

G

B

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Regions of Operation

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

DSV (V)

I D(A

)

VelocitySaturatedLinear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

0 0.5 1 1.5 2 2.50

0.5

1

1.5

2

2.5x 10

-4

DSV (V)DSV (V)

I D(A

)

VelocitySaturatedLinear

Saturated

VDSAT=VGT

VDS=VDSAT

VDS=VGT

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A PMOS Transistor

-2.5 -2 -1.5 -1 -0.5 0-1

-0.8

-0.6

-0.4

-0.2

0x 10

-4

VDS (V)

I D(A

)

Assume all variablesnegative!

VGS = -1.0V

VGS = -1.5V

VGS = -2.0V

VGS = -2.5V

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Transistor Model for Manual Analysis

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The Transistor as a Switch

VGS ≥ VTRon

S D

ID

VDS

VGS = VD D

VDD/2 VDD

R0

Rmid

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The Transistor as a Switch

0.5 1 1.5 2 2.50

1

2

3

4

5

6

7x 10

5

VDD

(V)

Req

(Ohm

)

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The Transistor as a Switch

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The CMOS Inverter: A First Glance

Vin Vout

CL

VDD

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CMOS Inverter

Polysilicon

In Out

VDD

GND

PMOS 2λ

Metal 1

NMOS

OutIn

VDD

PMOS

NMOS

Contacts

N Well

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Two Inverters

Connect in Metal

Share power and ground

Abut cells

VDD

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CMOS InverterFirst-Order DC Analysis

VOL = 0VOH = VDD

VM = f(Rn, Rp)

VDD VDD

Vin 5 VDD Vin 5 0

VoutVout

Rn

Rp

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CMOS Inverter: Transient Response

tpHL = f(Ron.CL)= 0.69 RonCL

V outVout

R n

R p

V DDV DD

V in 5 V DDV in 5 0

(a) Low-to-high (b) High-to-low

CLCL

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CMOS Properties

Full rail-to-rail swingSymmetrical VTCPropagation delay function of load capacitance and resistance of transistorsNo static power dissipationDirect path current during switching

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Future Perspectives

25 nm MOS transistor (Folded Channel)