week 4 - university of waterloopami.uwaterloo.ca/~basir/ece124/week4-3.pdf · 2012-01-27 ·...

WEEK 4.3

ECE124 Digital Circuits and Systems

Decoders implemented with NAND gates

  SomeBmes, in implementaBon decoders are done with NAND gates rather than AND gates.

  With NAND gates, the table illustraBng the decoder operaBon would look like this:


  This only has the effect of inver2ng the outputs…

  So pay a8en2on… In using a decoder, it is useful to know when the output is intended to be ac2ve high, or ac2ve low!

enable

x

y

d0

d1

d2

d3

Decoder trees

d0

d1

d2

d3

x

y

enable


  If we have decoders with enables, we can use mulBple, small decoders to implement larger decoders.

  Represent a smaller decoder as a box with inputs and outputs (we know how it works).

Example decoder tree: 4‐to‐16 decoder Using 2‐to‐4 decoders

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

d0

d1

d2

d3

x

y

enable

x1

x2

x3

x4

y0

y11

y10

y9

y8

y7

y6

y5

y4

y3

y2

y1

y12

y13

y14

y15


  Inputs are x1 (MSB), x2, x3, and x4 (LSB).

  Outputs are y0, , y15.

  The two most‐significant bits x1 and x2 are used to enable the appropriate decoder in the second stage.

  The two least‐significant bits x3 and x4 are used to generate the correct output in the second stage.

FuncBon implementaBon with decoders

d0

d1

d2

d3

x

y

enable

d5

d4

d6

d7

z

a

b

c f

1


  If we have a decoder and an OR gate handy, we can also implement funcBons too…

  Consider implemenBng f(a,b,c) = ∑(1,4,6,7) using a decoder and an OR‐gate to pick off the correct minterms.

Encoders

  Performs the inverse operaBon to a decoder.

  Encoder has 2n or fewer input lines and n output lines.

  The output is the binary code corresponding to the input value.

  Can make the circuit using OR‐gates.


Example of an encoder

  An example of an 8‐to‐3 encoder:


7

Priority encoders

  Simple encoder has problems:

  Assumes that only one input is acBve (high) at any given Bme. When mulBple inputs are high, there is an undefined output.

  Produces the output of 000 when no input is acBve (high) which is the same as d0 begin acBve (high) so there is an ambiguity.

  A priority encoder gives priority to higher numbered inputs. It also has a validity output to indicate the all inputs are not zero.

  Example: 4‐to‐2 priority encoder:


MulBplexers

  Combinatorial circuit block that has data inputs, select inputs and a single data output.

  Data is passed from one of the inputs through to the output based on the se^ng of the select lines.

  For n‐inputs, we need ceil( log2(n) ) select inputs.

  MulBplexers have their own symbol.


M U X

x0

Xn-1

Inputs

m=CEIL(LOG2 n) S0 Sm-1

Y=Output

If S=0=00..00,Y=X0 If S=1=00..01, Y=X1 If S=2=00..10,Y=X2 …. … … n=10, m=CEIL(LOG210)=CELI(3.3219280949)=4

Example of a 2‐input mulBplexer

s

x0

x1

f

0

1


  IllustraBon of a 2‐input mulBplexer:

  Can always write the SOP for a mulBplexer easily;   It is the appropriate se^ng of the control signal(s) AND‐ed with the appropriate

input (the control signals “gate” the AND).

Example of a 4‐input mulBplexer

s1s0

x0x1

f

00

11

0110x2

x3


  IllustraBon of a 2‐input mulBplexer:

  The SOP for the 4‐input mulBplexer is:

MulBplexers trees

s1

x1 0

1x3

x0 0

1x2

s0

f

0

1


  We can build larger mulBplexers from smaller mulBplexers.

  Example: 4‐input MUX using several 2‐input MUX:

S’1.X0+S1.X2

S’1.X1+S1.X3

f=S’0( )+ S0( ) S’1.X0+S1.X2 S’1.X1+S1.X3

ImplementaBon of an n‐input funcBon using (n‐1) input mulBplexer


  We can implement an n‐input funcBon using an (n‐1) input MUX by examining the truth table.   The first n‐1 inputs in the truth table become the control lines, and the last

input in the truth table is fed appropriately to the MUX inputs.

x0x1

x2x2

f

00

11

0110x2

!x2

Shannon decomposiBon

  We don’t need an (n‐1) input mulBplexer to implement an n‐input funcBon using mulBplexers.   Building a 4‐input MUX from 2‐input MUX should sort of indicate that we can

implement logic func2ons using any sort of MUX (parBcularly 2‐input mulBplexers).

  Inputs to the logic funcBon become the select lines, and we connect 0 or 1 to the data inputs of the MUX – the correct value (0 or 1) appears at the output given the se^ng on the select lines.

  Breaking a funcBon down for a MUX implementaBon is called Shannon Decomposi2on.

  We should run through the math, since it is why it works…


Cofactoring A B C F 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 1 1 1 1 0


F1(A=0,B,C)=B’.C+B.C’

F2(A=1,B,C)=B’.C’+B.C’

F(A,B,C)=A’.F1(A=0,B,C)+A.F2(A=1,B,C)

Cofactors

  Consider any Boolean funcBon f = f(x0, x1, , xn). We can always factor the funcBon with respect to any variable, say x0.


  The terms f(0, x1, … , xn) and f(1, x1, … , xn) are the cofactors of f with respect to x0.

  NoBce the x0 no longer appears in either of the cofactors; it has been factored out.

  We can think of cofactors as dividing the truth table of f into halves.   The rows in which x0 = 0 are grouped together.   The rows in which x0 = 1 are grouped together.

  A MUX is used to select the proper half of the truth table based on the value of x0.

Example using only 2‐input mulBplexers (1)

  Implement the following funcBon using 2‐input mul2plexers only (i.e., no logic gates).


  SoluBon is to cofactor with respect to some of the variables unBl we don’t need any logic gates (i.e., no product terms leg).

M U X

x0

x2 M U X

x1

x2

X’2

Example using only 2‐input mulBplexers (2)

x1

x2 0

1!x2

x2 0

1x2

x0

f

0

1


  Our final circuit using only 2‐input MUX is (simplified and unsimplified):

x1

x2 0

1!x2

x2

x0

f

0

1

DemulBplexers

  Recall that a mulBplexer selects from mulBple inputs and directs this input through to the output.

  A demulBplexer does the opposite – it switches a single data input onto one of several output lines.

  Note: A demul2plexer is simply a decoder in which the meaning of the inputs has changed.

  The decoder enable becomes the data input.   The decoder data inputs become the select lines.

  Depending on how the decoder data inputs (select lines) are set, the selected output will follow the decoder enable (data input)


Tri‐State Buffers (1)

x y

oe


  In addiBon to 0 and 1, we need the concept of an open circuit, or a high impedance state.

  A circuit that allows us to disconnect the output (open circuit) is called a tri‐state buffer):

  The signal oe is the output enable:   When oe = 1, y = x, and   when oe = 0 the output y is disconnected from input x

Tri‐State Buffers (2)

  Tri‐state buffers are useful when we want mulBple signals to drive a single wire at different Bmes.

  We can use the output enables to control which source drives a wire.

  We can implement mulBplexers with tri‐state buffers.

  Tri‐state buffers are useful in bus‐based design when we have mulBple sources of informaBon that travel down the same set of wires (e.g., the data bus in a computer).


MulBplexers built using decoders and tri‐state buffers

y

d0

d1

d2

d3

x

y

enable

i0

i1

i2

i3

select

enable


  IllustraBon of a 4‐to‐1 mulBplexer made with tri‐state buffers and a decoder:

Busses

  These slides are included since an upper‐year instructor quesBoned if students in ECE124 were taught this idea… Hence some explicit notes.

  A bus is simply a bundle of mulBple wires running together which carry data from one place to another; e.g., “a 16‐bit bus, a 32‐bit bus, a 64‐bit bus”.

  We represent a bus using a bold line with a “slash” through it possibly labeled with the number of individual wires contained in the bus.


Busses

  Imagine that each wire in the bus has different sources of informaBon. In other words, there are mulBple drivers for each wire.   You CANNOT have mulBple sources driving the same wire at the same Bme! This

could, for example, cause electrical shorts if one source wants to drive a logical‐1 (+ve voltage) while another source wants to drive a logical‐0 (0 voltage).

  How can we prevent the “mulBple driver problem” ???


Busses

  Could make each wire be driven by a mulBplexer. Then, the select lines on the mulBplexer control whose can drive the wire at any given Bme…

  Will never have more than one source driving a wire at a Bme.


In this illustration, there are 8 multiplexers; one for each wire in the bus!

Busses

  Can accomplish the same thing using tri‐state buffers and a decoder to force the enable signals on the tri‐state buffers to values such that only one tri‐state buffer is ever on (other tri‐states are in high impedance state).

  Will never have more than one source driving a wire at a Bme.


In this illustration, there are 8 tri-states; one for each wire in the bus!

Output enables coming from decoder; only 1 enable signal is active (at most) meaning only one driver ever connected.

week 4 - university of waterloopami.uwaterloo.ca/~basir/ece124/week4-3.pdf · 2012-01-27 ·...

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