week 02

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Week 2 - Processor Technologies Complex Instruction Set Computing (CISC) Complex Instruction set computing (CISC) primary purpose is to enable single instruction to execute a multiple low level operations. Generally a load from memory, arithmetic operation and memory storage. CISC allows capability of multi-step operations or addressing using single instructions to address models. CISC was back dated from reduced instruction set computer (RISC) Before the RISC concept was introduced, computer architects attempted to bridge semantic gap which designed instruction sets supporting high level programming. This was done to construct procedure calls, loop control and complex addressing models. This allowed single instructions to be combined by data structure and array accessory. These compact instructions resulted in smaller program sizes and fewer main memory accesses. This resulted in a large amount of money being saving on the cost of computer memory and dick storage in early 1960s and onwards. This meant faster execution in programming productivity which even applied to high level languages as such assembly language. Microprocessors are still programmed in assembly language for certain applications. Reduced Instruction Set Computing (RISC) . Reduced instruction set computing is a CPU design and was introduced as opposite to complex which simplified instructions to enable higher performance. The whole strategy of RISC was to add simplicity to instructions for much faster execution. RISC uses a small highly optimized set of instructions, whereas CISC uses more specialized set of instructions. Load and store architecture is used where memory is normally accessed only through specific instructions by RISC. Network on a Chip Network on a Chip is a communication subsystem on an integrated circuit. Network on a chip can span synchronous and asynchronous clock domains or use unlocked asynchronous logic. This technology applies on networking theory and methods to on chip communication. This has made improvement over conventional bus and cross bar interconnections, compared to other designs. Network on a Chip has been shown to improve scalability in addition to the power efficiency.

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Page 1: Week 02

Week 2 - Processor Technologies

Complex Instruction Set Computing (CISC) Complex Instruction set computing (CISC) primary purpose is to enable single instruction to execute a multiple low level operations. Generally a load from memory, arithmetic operation and memory storage. CISC allows capability of multi-step operations or addressing using single instructions to address models. CISC was back dated from reduced instruction set computer (RISC)

Before the RISC concept was introduced, computer architects attempted to bridge semantic gap which designed instruction sets supporting high level programming. This was done to construct procedure calls, loop control and complex addressing models. This allowed single instructions to be combined by data structure and array accessory.

These compact instructions resulted in smaller program sizes and fewer main memory accesses. This resulted in a large amount of money being saving on the cost of computer memory and dick storage in early 1960s and onwards. This meant faster execution in programming productivity which even applied to high level languages as such assembly language. Microprocessors are still programmed in assembly language for certain applications.

Reduced Instruction Set Computing (RISC).

Reduced instruction set computing is a CPU design and was introduced as opposite to complex which simplified instructions to enable higher performance. The whole strategy of RISC was to add simplicity to instructions for much faster execution.

RISC uses a small highly optimized set of instructions, whereas CISC uses more specialized set of instructions. Load and store architecture is used where memory is normally accessed only through specific instructions by RISC.

Network on a Chip

Network on a Chip is a communication subsystem on an integrated circuit. Network on a chip can span synchronous and asynchronous clock domains or use unlocked asynchronous logic. This technology applies on networking theory and methods to on chip communication. This has made improvement over conventional bus and cross bar interconnections, compared to other designs. Network on a Chip has been shown to improve scalability in addition to the power efficiency.

Page 2: Week 02

This is a Single Chip PCI Fast Ethernet NIC Controller DM9102D

Comparison of Architectures For Different Microprocessors

ARM is the industry's leading supplier of microprocessor technology. They offer the wide range of microprocessor cores. ARM are known as the “Architecture for the Digital World” as they have development tools and software for more than 30 billion processors. ARM are the industries top supplier for majority of application markets and offer the widest range of microprocessors cores for top performance.

Cortex application processors are commonly used in mobile internet devices. They perform with 32 and 64 bit for next generation of mobile internet devices and come in single and multi core. The processers support the following devices:

Smart Phones

Smart Books and Net books

EBook readers

Digital TV

Home Getaways

There are many microprocessors available in the market. They differentiate between manufactures and consumers need to choose wisely depending upon which media device they intend to use. Certain micro processers may need to be used to suit the user’s needs.

Page 3: Week 02

Below is a chart which compares and contrasts the important features found on some of the most

popular chips in the market today.

Transistors CPU Speed L2 CacheFront-Side Bus Speed

Celeron 7,500,0001.06 GHz - 2 GHz

256 KB,full speed

133 MHz and 400 MHz

Pentium II 7,500,000233 MHz - 450 MHz

512 KB,half speed

100 MHz

Pentium III 9,500,000450 MHz - 1 GHz

256 KB,full speed

133 MHz

Pentium III Xeon

28,100,000500 MHz - 1 GHz

256 KB - 2 MB,full speed

100 MHz

Pentium 4 55,000,0001.4 GHz - 3.4 GHz

256 KB,full speed

800 MHz

K6-II 9,300,000500 MHz - 550 MHz

N/A 100 MHz

K6-III 21,300,000400 MHz - 450 MHz

256 KB,full speed

100 MHz

Athlon (K7) 22,000,000850 MHz - 1.2 GHz

256 KB,full speed

200 MHz and 266 MHz

Athlon XP 37,500,000 1.67 GHz384 KB,full speed

266 MHz

Duron N/A 700-800 MHz64 KB,full speed

200 MHz

PowerPC G3 6,500,000233 MHz - 333 MHz

512 KB, 1 MB,half speed

100 MHz

PowerPC G4 10,500,000400 MHz - 800 MHz

1 MB,half speed

100 MHz

Athlon 64105,900,000

800 MHz1 MB,half speed

1.6 GHz

G5 58,000,000 2.5GHz 512 KB 900MHz - 1.25GHz

Next Generation Hardware for Smart Homes

Page 4: Week 02

Since Immerge has produced products which allow users of smart family homes to upload and share media content via the media server. I thought having an voice activation for every hardware device would be useful to launch applications without having to search manually which may save users time and effort. Using voice activation for hardware for such TV's and computers may be most effective. A voice recorder device will need to be attached to every system allowing voice commands to be transferred. Giving family users the option to add additional word commands to the device will be useful, since some users may prefer to give commands which is not pre added.

Having security in smart homes is crucial as highly valuable hardware could be in risk of being stolen. Installing eye scanners in every room may be beneficial for the home users. The eye scanner will operate by scanning the pattern of each house user’s iris and provided by the software, the main server administrator will have the option to save each house users unique pattern. If an stranger enters a room with an unidentified iris pattern, the house users will be alerted via text message. The server administrator will also be alerted on his computer screen, showing the live recording of the camera in the room the person is currently in. The iris pattern will automatically be saved on the computer. The administrator will have software installed giving the option to alert the police immediately within seconds. If there is a case where the administrator is not at home, security buttons will be provided to the house users allowing them to alert the police.

References

Arm.com. 2014. Processors - ARM. [online] Available at: http://www.arm.com/products/processors/index.php [Accessed: 6 Mar 2014].

Webopedia.com. 2014. Microprocessor Comparison Chart - Webopedia.com. [online] Available at: http://www.webopedia.com/quick_ref/processor.asp [Accessed: 6 Mar 2014].

Wikipedia. 2014. Network on a chip. [online] Available at: http://en.wikipedia.org/wiki/Network_On_Chip [Accessed: 13 Mar 2014].

Wikipedia. 2014. Complex instruction set computing. [online] Available at: http://en.wikipedia.org/wiki/Complex_instruction_set_computer [Accessed: 13 Mar 2014].

AG, S. 2014. 2.2.7 DM9102D: DACOM West. [online] Available at: http://www.dacomwest.de/produktauswahl/davicom/macphy/dm9102d.html [Accessed: 13 Mar 2014].