vlsi2 feasibility
TRANSCRIPT
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Audio Steganography Core
Feasibility PresentationTeam BUNI 2
Ben Doherty, Jeremy Gummeson
Chris Campetti, Phil Murray
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Datapath Block Diagram
SPI_CLK
SPI_MOSI
SPI_SS
SPI InterfaceSPI_MISO
Register File
PRNG
DES3 Crypt
Stego CODEC
AUDIO_IN
AUDIO_CLK
AUDIO_LRSEL
AUD IO_OUT
rw1
des_
rs
6
addr132
wrdata1
rddata1 32
prn
2
seed
32
rddata032
addr06
rw0
key3
56
key2
56
key1
56
des_
in64
des_
out
64
6
decrypt
wrdata032
get_prn
load_seed
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Pseudo Random Number Generator
Linear feedback shift register design
32 bit shift register with XOR gates tapped atoptimized locations. Tap points have been researched for optimal
randomness [1]
232 1 = 4,294,967,295
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PRNG
32 flip-flops
2 inv_1
31 mux2_2
9 nand2_1
1 or2_1
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PRNG Test Results
seed_in = 32hC0_29_A2_BD;
11, 01, 00, 00, 10, 01, 00, 11, 10, 11, 10,
After 10,000 Iterations:
Occurrences of 00: 2548
Occurrences of 01: 2434
Occurrences of 10: 2486Occurrences of 11: 2532
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Register file Standard Cell References of Register file.
Reference Library Unit Area Count Total Area------------------------------------------------------------------------
and2_1 vtvtlib25 69.984001 2080 145566.718750 and3_1 vtvtlib25 83.980797 64 5374.770996 dp_2 vtvtlib25 265.939209 4096 1089287.000000
inv_1 vtvtlib25 41.990398 2060 86500.218750 mux2_2 vtvtlib25 97.977600 4096 401316.250000 nand2_1 vtvtlib25 55.987202 384 21499.085938 nand3_1 vtvtlib25 69.984001 512 35831.808594 nor2_1 vtvtlib25 41.990398 5144 215998.609375 nor3_1 vtvtlib25 55.987202 640 35831.808594 or2_1 vtvtlib25 69.984001 576 40310.785156 ------------------------------------------------------------------------
Total 10 references 2077517
2.077mm2 area just for register file. Most significant size consumer on chip.
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3DES Encryption
3 64-bit keys (56 + 8 bits parity)
64-bit inputs and outputs
48 cycle generation time
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DES3 Algorithm
Overall # Comb. LUs: 3018
Overall # Seq. LUs: 128
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CODEC
Drop-in replacements for addingmessage to a Digital Audio Stream, ora MIDI Stream.
Other stream formats possible andwill be looked into.
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Timing Considerations
fs is arbitrary, Low quality at about 8kHz, but less data can be
hidden in the stream (16,000 bits/sec => 2,000bytes/sec of encoded data) MAXIMUM
Typical applications @ 44.1kHz 11,012 bytes/second MAXIMUM Will be significantly less based on proportion of
samples with sufficient magnitude in audiostream
Bit Clock must run at least 256*fs This will allow DES to complete
encryption/decryption
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Why Hardware? Low cost, low power, inline watermarking without CPU
Can generate hardware to do MIDI or Digital Audio Stream
Can store message in register file for watermarkingpurposes
Possibly write another CODEC module which can take messagein serially for arbitrary message sizes High data storage rate in CD-quality audio streams
Very small devices for covert ops
Possibly run on watch battery: relatively low frequencysystem
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References [1] Sung, R; Sung A; Chan P; Mah, J; Linear Feedback Shift Registers
http://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/Drivers_Ed/lfsr.html
[2] Keller S; Smid M; Modes of Operation Validation System
http://csrc.nist.gov/publications/nistpubs/800-17/800-17.pdf
http://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/Drivers_Ed/lfsr.htmlhttp://www.ece.ualberta.ca/~elliott/ee552/studentAppNotes/1999f/Drivers_Ed/lfsr.html