8/10/2019 VLSI Testing CIrucits

http://slidepdf.com/reader/full/vlsi-testing-cirucits 1/1

Course Code & Title : VL7301 Testing of vlsi circuits

PART A5* 2 = 10 Marks

1. What are the impacts of accessi ilit! on testing" (Outcome: a, Learning Skills: Understand)#. $efine controlla ilit! and o serva ilit!" (Outcome: a, Learning Skills: Remember)3. What are the t!pes of $%T Techni ues" (Outcome: a, Learning Skills: Remember)'. (tate the rule for )scillators & cloc*s +ith their respect diagram" (Outcome: a, Learning Skills:

Understand),. $ra+ the diagram for L(($ dou le latch design" (Outcome: a, Learning Skills: Understand) PART B 1*8+2*16 = 40 Marks

-. a / plain in detail a out %ull serial integrated scan & on serial scan in 2eneric scan aseddesign" 377 (Outcome: a,LearningSkills:Remember) 45

(OR) b) / plain s!stem level DFT approaches (Outcome: a,LearningSkills:Remember) 45

7. a / plain the follo+ing ad hoc design for testa ilit! techni ues 4i Test points (Outcome: a,LearningSkills:Remember) 45

4ii 6nitiali ation and 8onosta le multivi rators (Outcome: a,LearningSkills:Remember) 45

(OR) $efine Testa ilit!" / plain riefl! a out their Trade off 9Controlla ilit! & ) serva ilit!" 3,, 4Outcome: a, Learning Skills: Understand) 41-

5. a / plain in riefl! a out the Classical scan ased design" Outcome: a, Learning Skills:

Understand) 41- (OR)

/ plain the follo+ing $%T Techni ues 3-- 4i artitioning counters & shift registers 4- 4ii artitioning of large com inational circuits 4, 4iii Logical ;edundanc! & 2lo al feed path 4,

repared ! Verified ! <pproved !