vlsi testing lecture 14: built-in self-test
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VLSI Testing Lecture 14: Built-In Self-Test. Dr. Vishwani D. Agrawal James J. Danaher Professor of Electrical and Computer Engineering Auburn University, Alabama 36849, USA [email protected] http://www.eng.auburn.edu/~vagrawal IIT Delhi, Aug 26, 2013, 2:30-3:30PM. Contents. - PowerPoint PPT PresentationTRANSCRIPT
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 1
VLSI Testing
Lecture 14: Built-In Self-Test
VLSI Testing
Lecture 14: Built-In Self-Test
Dr. Vishwani D. AgrawalJames J. Danaher Professor of Electrical and
Computer EngineeringAuburn University, Alabama 36849, USA
[email protected]://www.eng.auburn.edu/~vagrawal
IIT Delhi, Aug 26, 2013, 2:30-3:30PM
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 2
ContentsContents Definition of BIST Pattern generator
LFSR Response analyzer
MISR Aliasing probability
BIST architectures Test per scan Test per clock Circular self-test Memory BIST
Summary
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 3
Define Built-In Self-TestDefine Built-In Self-Test Implement the function of automatic test
equipment (ATE) on circuit under test (CUT). Hardware added to CUT:
Pattern generation (PG) Response analysis (RA) Test controller
CUT
StoredTest
Patterns
Storedresponses
PinElectronics
Comparatorhardware
Test control HW/SW
ATE
PG
RA
CUT
Go/No-go signature
Tes
t co
ntr
ol
log
icCK
BISTEnable
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 4
Pattern Generator (PG)Pattern Generator (PG)
RAM or ROM with stored deterministic patterns Counter Pseudorandom pattern generator
Feedback shift register Cellular automata
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 5
Pseudorandom IntegersPseudorandom Integers
0
5
1
3
7
6 2
4
Start
+3
Sequence: 2, 5, 0, 3, 6, 1, 4, 7, 2 . . .
0
5
1
3
7
6 2
4
Start
+2
Sequence: 2, 4, 6, 0, 2 . . .
Xk = Xk-1 + 3 (modulo 8) Xk = Xk-1 + 2 (modulo 8)
Maximum length sequence: 3 and 8 are relative primes.
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 6
Pseudo-Random Pattern Generation
Pseudo-Random Pattern Generation
Standard Linear Feedback Shift Register (LFSR)
Produces patterns algorithmically – repeatable
Has most of desirable random # properties
May not cover all 2n input combinations
Long sequences needed for good fault coverage
either hi = 0, i.e., XOR is deleted or hi = Xi
Initial state (seed): X0, X1, . . . , Xn-1
must not be 0, 0, . . . , 0
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 7
Matrix Equation for Standard LFSR
Matrix Equation for Standard LFSR
X0 (t + 1)
X1 (t + 1)...
Xn-3 (t + 1)
Xn-2 (t + 1)
Xn-1 (t + 1)
10...00
h1
01...00
h2
00...001
……
………
00...10
hn-2
00...01
hn-1
X0 (t)
X1 (t)...
Xn-3 (t)
Xn-2 (t)
Xn-1 (t)
=
X (t + 1) = Ts X (t) (Ts is companion matrix)
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 8
LFSR Implements a Galois Field
LFSR Implements a Galois Field
Galois field (mathematical system): Multiplication by X same as right shift of LFSR Addition operator is XOR ( )
Ts companion matrix: 1st column 0, except nth element which is always 1
(X0 always feeds back) Rest of row n – feedback coefficients hi Remaining identity matrix means a right shift
Near-exhaustive (maximal length) LFSR Cycles through 2n – 1 states (excluding all-0)
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 9
LFSR PropertiesLFSR Properties Must not initialize to all 0’s – hangs
If X is initial state, LFSR progresses through states
X, Ts X, Ts2 X, Ts
3 X, …
Matrix period:
Smallest k such that Tsk = I
k = LFSR cycle length
Maximum length k = 2n-1, when feedback (characteristic)
polynomial is primitive
Example: 1 + X+ X3
Characteristic polynomial:
1 + h1 x + h2 X2 + … + hn-1 Xn-1 + Xn
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 10
LFSR: 1 + X + X3LFSR: 1 + X + X3
D QX2
D QX1
D QX0
X2 X1 X0
CK
RESET
000
100 001
110 010
111 101
011
RESET
Test of primitiveness: Characteristic polynomial of degree n must divide 1 + Xq for q = n, but not for q < n
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 11
LFSR as Response AnalyzerLFSR as Response Analyzer Use cyclic redundancy check code (CRCC) generator
(LFSR) for response compacter Test data bits from circuit POs are compacted CRCC divides the PO polynomial by its characteristic
polynomial Leaves remainder of division in LFSR Must initialize LFSR to seed value (usually 0) before
testing After test – compare signature in LFSR with pre-
computed signature of fault-free circuit
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 12
Example Modular LFSR Response Analyzer
Example Modular LFSR Response Analyzer
LFSR seed is “00000”
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 13
Signature by Logic Simulation
Signature by Logic Simulation
Input bitsInitial State
10001010
X0
010001111
X1
001000010
X2
000100001
X3
000010101
X4
000001010 Signature
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 14
Signature by Polynomial Division
Signature by Polynomial Division
X2
X7
X7
+ 1
+ X5
X5
X5
+ X3
+ X3
+ X3
X3
+ X2
+ X2
+ X2
+ X
+ X
+ X + 1
+ 1
X5 + X3 + X + 1Characteristic polynomial
remainder
Input bit stream: 0 1 0 1 0 0 0 1
0 ∙ X0 + 1 ∙ X1 + 0 ∙ X2 + 1 ∙ X3 + 0 ∙ X4 + 0 ∙ X5 + 0 ∙ X6 + 1 ∙ X7
Signature: X0 X1 X2 X3 X4 = 1 0 1 1 0
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 15
Multiple-Input Signature Register
(MISR)
Multiple-Input Signature Register
(MISR) Problem with ordinary LFSR response compacter:
Too much hardware if one of these is put on each primary output (PO)
Solution: MISR – compacts all outputs into one LFSR Works because LFSR is linear – obeys
superposition principle Superimpose all responses in one LFSR – final
remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 16
Modular MISR ExampleModular MISR Example
X0 (t + 1)
X1 (t + 1)
X2 (t + 1)
001
010
110
=X0 (t)
X1 (t)
X2 (t)
d0 (t)
d1 (t)
d2 (t)
+
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 17
Aliasing ProbabilityAliasing Probability Aliasing means that faulty signature matches fault-
free signature Aliasing probability ~ 2-n
where n = length of signature register Example 1: n = 4, Aliasing probability = 6.25% Example 2: n = 8, Aliasing probability = 0.39% Example 3: n = 16, Aliasing probability = 0.0015%
Fault-free signature
2n-1 faulty signatures
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 18
BIST ArchitecturesBIST Architectures
Test per scan Test per clock
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 19
Test Per Scan BISTTest Per Scan BIST
Scan register
Scan register
Comb. logic
Scan register
Comb. logic
Scan register
Comb. logic
PG
RA
BISTControl
logic
PI and PO disabled during test
BIST enable
Go/No-go signature
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 20
Test per Clock BISTTest per Clock BIST New fault set tested every clock period Shortest possible pattern length
10 million BIST vectors, 200 MHz test / clock
Test Time = 10,000,000 / 200 x 106 = 0.05 s Shorter fault simulation time than test / scan
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 21
Built-in Logic Block Observer (BILBO)
Built-in Logic Block Observer (BILBO)
Combined functionality of D flip-flop, pattern generator, response analyzer, and scan chain
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 22
BILBO Serial Scan ModeBILBO Serial Scan Mode B1 B2 = “00” Dark lines show enabled data paths
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 23
BILBO LFSR Pattern Generator Mode
BILBO LFSR Pattern Generator Mode
B1 B2 = “01”
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BILBO in DFF (Normal) Mode
BILBO in DFF (Normal) Mode
B1 B2 = “10”
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 25
BILBO in MISR ModeBILBO in MISR Mode
B1 B2 = “11”
Copyright 2005, Agrawal & Bushnell Lecture 14: BIST 26
SummarySummary LFSR pattern generator and MISR response analyzer –
preferred BIST methods BIST has overheads: test controller, extra circuit
delay, primary input MUX, pattern generator, response compacter, DFT to initialize circuit and test the test hardware
BIST benefits: At-speed testing for delay and stuck-at faults Drastic ATE cost reduction Field test capability Faster diagnosis during system test Less effort in the design of testing process Shorter test application times