vlsi record 2012

R.M.D ENGINEERING COLLEGER.S.M NAGAR, KAVARAIPETTAI – 601206

GUMMIDIPOONDI TALUK, THIRUVALLUR DIST.

Certified that this is a bonafide record work done by

……………………………… with Roll/Reg. Number

……………………………………… He /She is a student of

…………………………………………………… in the R.M.D Engineering College,

Kavaraipettai.

Faculty-in-Charge Head of the Department

Date of Examination

Internal Examiner External Examiner

1

INDEXSl.No.

Date ofExperiment

Name of the ExperimentDate of

SubmissionMarks

Page No.

Signatureof Staff

1. Full adder

2. 4 to 1 multiplexer

3. 3 to 8 address decoder

4. 8 bit ripple carry adder

5. 4 bit multiplier

6. 4 bit counter

7. 4 bit PRBS generator

8. Test bench - full adder

9. Test bench - Multiplexer

10. Test bench – 3 to 8 decoder

11. Test bench – 4 bit counter

12. Test bench – PRBS generator

13. Implementation of Full adder

14. Implementation of Multiplexer

15. Implementation of Decoder

16. Implementation of 8 bit adder

17. Implementation of 4 bit multiplier

18. Implementation of 4 bit counter

19. Implementation of PRBS generator

20. Implementation of Accumulator

21. Simulation and Implementation of ALU

22.SPICE simulation of MOS differential amplifier

23. Inverter Layout and Simulation

24.

25.

Signature of theHead of the Dept. & date:

2

Full Adder

Ex. No: 1 Date:

Aim:To simulate Full adder using Verilog HDL using Structural and Dataflow modeling.

Software Required:

Xilinx ISE, ModelSim

Theory:

A combinational circuit that performs the addition of three bits is called a Full adder. The Circuit needs three binary inputs and produces two binary outputs namely sum and carry.

The simplified Boolean expressions for sum and carry are

Sum S = A B CCarry Cout = AB+BC+CA

Program:

// Structural Modelingmodule fuladins1(a, b, c, s, cr); input a; input b; input c; output s; output cr;

xor (s,a,b,c);or (cr,a&b,b&c,c&a);

endmodule

// Data Flow Modelingmodule fulad1(a, b, c, s, cr); input a; input b;

3

input c; output s; output cr;

assign s=a^b^c; assign cr=a&b|b&c|c&a;

endmodule

Output:

Result:

4

Thus Full Adder was designed and simulated in Verilog HDL.4 to 1 Multiplexer

Ex.No:2 Date:

Aim:

To simulate 4 to 1 multiplexer using Verilog HDL using Structural and Dataflow modeling.

Software Required:


Theory:

A digital multiplexer is a combinational circuit that selects binary information from one of many inputs and directs it as a single output based on the selector lines. The 4:1 multiplexer has 4 inputs,2 selector lines and a single output

The simplified Boolean expression for output isY = S0’ S1’A+S0’S1B+S0S1’C+S0S1D

Program:

// Structural Modelingmodule multiplexer (y,i,s);

output y;input [3:0]i; input [1:0]s; wire a,b,c,d,e,f;

not (a,s[0]); not (b,s[1]);and (c,i[0],a,b); and (d,i[1],a,s[1]); and (e,i[2],s[0],b); and (f,i[3],s[0],s[1]);or (y,c,d,e,f);

endmodule

// Dataflow modeling

5

module Mux(d, s, y);input [3:0] d; input [1:0] s; output y; wire a,b,c,e,f,g,h,i;

assign a=~s[0]; assign b=~s[1]; assign c=(d[0]&b&a); assign e=(d[1]&s[0]&a); assign f=(d[2]&b&s[0]); assign g=(d[3]&s[0]&s[1]); assign h=c|e; assign i=g|f; assign y=h|i

endmodule

Output:

Result:

6

Thus a 4:1 multiplexer was designed and simulated using Verilog HDL.3 to 8 Address Decoder

Ex. No: 3 Date:

Aim:To simulate 3:8 address decoder using verilog HDL using structural and dataflow

modeling

Software Required:Xilinx ISE, ModelSim

Theory:A decoder can take the form of a multiple-input, multiple-output logic circuit that

converts coded inputs into coded outputs, where the input and output codes are different. e.g. n-to-2n, binary-coded decimal decoders. Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.

Program:

// Structural modelingmodule decoder(a,b,c,y0,y1,y2,y3,y4,y5,y6,y7); input a,b,c; output y0,y1,y2,y3,y4,y5,y6,y7 ;

not(an,a);not(bn,b);not(cn,c);and(y0,an,bn,cn);and(y1,an,bn,c);and(y2,an,b,cn);and(y3,an,b,c);and(y4,a,bn,cn);and(y5,a,bn,c);and(y6,a,b,cn);and(y7,a,b,c);

endmodule

7

// Dataflow Modeling

module decoder(y,x)output [7:0]y;input [2:0]x;wire a,b,c;

assign a=x[0];assign b=x[1];assign c=x[2];assign y[0]=a&b&c;assign y[1]=a&b&x[2];assign y[2]=a&x[1]&c;assign y[3]=a&x[1]&x[2];assign y[4]=x[0]&b&c;assign y[5]=x[0]&b&x[2];assign y[6]=x[0]&x[1]&c;assign y[7]=x[0]&x[1]&x[2];

endmodule

Output:

Result:

8

Thus a 3:8 decoder was designed and simulated using Verilog HDL.

8 bit Ripple Carry AdderEx.No:4 Date:

Aim:To simulate eight bit ripple carry adder using Verilog HDL using Structural and

Dataflow modeling.


Theory : A combinational circuit that performs the addition of eight bits.

Program:

module carryripple(a,b,cin,s,cout); input [7:0] a; input [7:0] b;

input cin; output [7:0] s; wire [6:0] c;

output cout;fa s0(a[0],b[0],cin,s[0],c[0]);fa s1(a[1],b[1],c[0],s[1],c[1]);fa s2(a[2],b[2],c[1],s[2],c[2]);fa s3(a[3],b[3],c[2],s[3],c[3]);fa s4(a[2],b[2],c[3],s[4],c[4]);fa s5(a[2],b[2],c[4],s[5],c[5]);fa s6(a[2],b[2],c[5],s[6],c[6]);fa s7(a[2],b[2],c[6],s[7],cout);endmodule

9

b[7:0]

a[7:0]

Full adder

Full adder

Full adder

Full adder

Full adder

Full adder

Full adder

Full adder

s[7:0]

cin

cout

module fulad1(a, b, c, s, cr); input a; input b; input c; output s; output cr;


endmodule

OUTPUT:

Result:

10

Thus a ripple carry adder was designed and simulated using Verilog HDL.

4 bit MultiplierEx.No:5 Date:

Aim:To simulate four bit multiplier using Verilog HDL.


Theory : A combinational circuit that performs the multiplication of two four bit numbers to

obtain a eight bit product.

Program:module multiplier(m,q,pp);input [3:0]m;input [3:0]q;output [7:0]pp;wire [8:0]ppr;wire [14:0]cpr;

base b11(m[0],q[0],0,0,pp[0],cpr[0]);base b12(m[1],q[0],0,cpr[0],ppr[0],cpr[1]);base b13(m[2],q[0],0,cpr[1],ppr[1],cpr[2]);base b14(m[3],q[0],0,cpr[2],ppr[2],cpr[3]);base b21(m[0],q[1],ppr[0],0,pp[1],cpr[4]);base b22(m[1],q[1],ppr[1],cpr[4],ppr[3],cpr[5]);base b23(m[2],q[1],ppr[2],cpr[5],ppr[4],cpr[6]);

11

base b24(m[3],q[1],cpr[3],cpr[6],ppr[5],cpr[7]);base b31(m[0],q[2],ppr[3],0,pp[2],cpr[8]);base b32(m[1],q[2],ppr[4],cpr[8],ppr[6],cpr[9]);base b33(m[2],q[2],ppr[5],cpr[9],ppr[7],cpr[10]);base b34(m[3],q[2],cpr[7],cpr[10],ppr[8],cpr[11]);base b41(m[0],q[3],ppr[6],0,pp[3],cpr[12]);base b42(m[1],q[3],ppr[7],cpr[12],pp[4],cpr[13]);base b43(m[2],q[3],ppr[8],cpr[13],pp[5],cpr[14]);base b44(m[3],q[3],cpr[7],cpr[14],pp[6],pp[7]);

endmodule

// Basic cell modulemodule base(mi,qi,ppi,cin,pout,cout);input mi,qi,ppi,cin;output pout,cout;wire in;

and(in,mi,qi);fulladder f1(in,ppi,cin,pout,cout);

endmodule

// Full adder modulemodule fulladder(a, b, c, s, cr); input a; input b; input c; output s; output cr;


endmodule

Output:

Result:

12

Thus a 4 bit multiplier was designed and simulated using Verilog HDL.

4 bit counter

Ex.No:6 Date:

Aim:

To simulate four bit ripple counter using Verilog HDL.

Software Required:


Theory:

A binary ripple counter consists of a series of four complementary flip-flops in which the output is given as a clock for the next higher order flip-flops. The complementary flip flops can be obtained using a T flip-flop.

Program:// counter modulemodule counter11(in, clkm,q);

input in;input clkm;output [3:0]q;

tff t1(in,clkm,q[0]);tff t2(in,q[0],q[1]);tff t3(in,q[1],q[2]);tff t4(in,q[2],q[3]);

endmodule

// T flip-flop module module tff(t,clk,q);

input t,clk;output q;reg q;

initial q=1'b0;always @(negedge clk)

13

Clock input clk Q

T

clk Q

T

clk Q

T

clk Q

T

Q1 Q2 Q3 Q4

beginif(t==1)q=~q;elseq=q;

endendmodule

Output:

Result:

14

Thus a 4 bit counter was designed and simulated using Verilog HDL.

4 bit PRBS generator

Ex.No:7 Date:

Aim:

To simulate four bit Pseudo random binary sequence generator.

Software Required:


Theory:A Pseudo random binary sequence generator is realize with the help of Maximal

length Linear feedback shift register. It is constructed with the help of 4 bit shift register with a linear feedback. The linear feedback is made possible by an Ex-OR gate whose inputs are of maximal length.

Program:module prbs(clk,q);

input clk;output [3:0]q;reg q;reg p;

initial q = 4’b0101;always @(posedge clk)begin p = q[3]^q[2];q[3]=q[2];q[2]=q[1];q[1]=q[0];q[0]=p;end

endmodule

15

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLKCLK

Result:

Thus a pseudo random binary sequence generator was synthesized and simulated using Verilog HDL.

16

Test Bench - Full AdderEx.No:8 Date:

Aim:To create test bench to simulate full adder using behavioral modeling.

Software Required:

ModelSim

Program:

module fa(a,b,c,s,cy); input a,b,c; output s,cy; reg s,cy; always@(a or b or c) begin s=a^b^c; cy=a&b&c; endendmodule

// Test bench modulemodule testbench(); reg [2:0]a; wire s,cy; fa fa1 (a[0],a[1],a[2],s,cy); // Instantiate full adder module initial begin #10 a=3'b000; #10 a=3'b001; #10 a=3'b010; #10 a=3'b011; #10 a=3'b100; #10 a=3'b101; #10 a=3'b110; #10 a=3'b111; end endmodule

17

Result:

Thus test bench for full adder is created and simulated

18

Test Bench -MultiplexerEx.No:9 Date:

Aim:To create test bench to simulate 4:1 multiplexer using behavioral modeling.

Software Required:

ModelSim

Program:

module multi ( d, s, y);input [3:0] d;input [1:0] s;output y;reg y;

always @ (s or d)case (s)2'b00: y = d[0];2'b01: y = d[1];2'b10: y = d[2];2'b11: y = d[3];endcase

endmodule

// Test bench module

module testbench;reg [3:0]d;reg [1:0]s;wire y;

multi m1(d, s, y); // Instantiate multiplexer module initial

begin #10 d = 4’b0011; s = 2’b00;

#10 d = 4’b1100; s = 2’b01;#10 d = 4’b1110; s = 2’b10;#10 d = 4’b1001; s = 2’b11;

endendmodule

19

Result:

Thus test bench for 4:1 multiplexer is created and simulated.

20

Test Bench - 3 to 8 address decoderEx.No:10 Date:

Aim:To create test bench for 3 to 8 address decoder using behavioral modeling.

Software Required:

ModelSim

Program:

module adddecode (s,d);input [2:0] s;output[7:0] d;

always @ (s)case (s)3’b000: d= 8’h01;3’b001: d= 8’h02;3’b010: d= 8’h04;3’b011: d= 8’h08;3’b100: d= 8’h10;3’b101: d= 8’h20;3’b110: d= 8’h40;3’b111: d= 8’h80;endcase

endmodule

module test_adddecode;reg [2:0] s;wire[7:0] d;

adddecode decode_tb (s,d);initialbegin#10 s= 3’b000;#10 s= 3’b001;#10 s= 3’b010;#10 s= 3’b011;#10 s= 3’b100;#10 s= 3’b101;#10 s= 3’b110;#10 s= 3’b111;end

endmodule

21

Result:Thus test bench for 3 to 8 address decoder was created and simulated.

22

Test Bench - 4 Bit CounterEx.No:11 Date:

Aim:To create test bench to simulate four bit counter using behavioral modeling.

Software Required:

ModelSim

Program:// counter module

module countr (clk, q);input clk;output q;reg [3:0] q;

initial q = 4'b0000;always @ (negedge clk)

if (q == 4'b1111)q= 4'b0000;elseq = q +1;

endmodule

// Test Bench modulemodule testcountr;

reg clk;wire [3:0] q;

countr c1 (clk,q);initial clk = 1'b0;always#5clk = ~clk;

endmodule

23

Result:Thus test bench for four bit counter is created and simulated.

24

Test Bench - PRBS generatorEx.No:12 Date:

Aim:To create test bench to simulate 4 bit PRBS generator.

Software Required:

ModelSim

Program:// counter module

module prbs(clk,q);input clk;output q;reg [3:0]q;reg p;

initial q = 4’b0101;always @(posedge clk)begin p = q[3]^q[2];q[3]=q[2];q[2]=q[1];q[1]=q[0];q[0]=p;end

endmodule

// Test Bench modulemodule testprbs;

reg clk;wire [3:0] q;prbs p1 (clk,q);

initial clk = 1'b0;always#5clk = ~clk;

endmodule

25

Result:Thus test bench for four bit counter is created and simulated.

26

Implementation of Full AdderEx.No:13 Date:

Aim:To synthesize and implement full adder circuit using Verilog HDL in the FPGA.

Software Required:Xilinx ISE

Hardware Required:1. FPGA kit.

Specifications:Family : Spartans 3Device : XC3S400Package : TQ144

2. General purpose I/O kit

Program:

module fulasd11(a, b, c, s, cr); input a; input b; input c; output s; output cr;

reg s,cr;always @(a or b or c)

begins=a^b^c;cr=a&b|b&c|c&a;end

endmodule

Pin Details:

Pin Connector Pin numberInput FRC1 74 76 77 79 78 82 80 83Output FRC2 84 85 86 87 89 90 92 96CLK - 52

Result:

Thus a full adder was synthesized and implemented using Verilog HDL.

27

Implementation of MultiplexerEx.No:14 Date:

Aim:To synthesize and implement 4:1 multiplexer circuit using Verilog HDL in the FPGA.





Program:

module multiplexer( x,y,s );input [3:0]x;input [1:0]s;output y;reg y;

always @(d or s)begincase(s)2’b00: y=x[0];2’b01: y=x[1];2’b10: y=x[2];2’b11: y=x[3];endcaseend

endmodule

Pin Details:


Result:

Thus a 4:1 multiplexer was synthesized and implemented using Verilog HDL.

28

Implementation of DecoderEx.No:15 Date:

Aim:To synthesize and implement 3:8 decoder using Verilog HDL in the FPGA.





Program:

module decoder(a,y);input [2:0]a;output [7:0]y;reg y;

always @(a)case(a)3'b000:y=8'h01;3'b001:y=8'h02;3'b010:y=8'h04;3'b011:y=8'h08;3'b100:y=8'h10;3'b101:y=8'h20;3'b110:y=8'h40;3'b111:y=8'h80;endcase

endmodule

Pin Details:


Result:

Thus a 3:8 decoder was synthesized and implemented using Verilog HDL.

29

Implementation of 8 Bit AdderEx.No:16 Date:

Aim:To synthesize and implement eight bit adder using Verilog HDL in the FPGA.





Program:

module eightbitadder(a,s);input [7:0]a;output [7:0]s;reg s;reg [7:0]b;

initial b=8'b00000000;always @(a or b)s=a+b;

endmodule

Pin Details:


Result:

Thus a eight bit adder was synthesized and implemented using Verilog HDL.

30

Implementation of 4 bit MultiplierEx.No:17 Date:

Aim:To synthesize and implement four bit multiplier using Verilog HDL in the FPGA.





Program:

module multiplier(a,b,p);input [3:0]a;input [3:0]b;output [7:0]p;reg p;

always @(a or b)p=a*b;

endmodule

Pin Details:


Result:

Thus a four bit multiplier was synthesized and implemented using Verilog HDL.

31

Implementation of 4 bit CounterEx.No:18 Date:

Aim:

To synthesize and implement four bits counter using Verilog HDL in the FPGA.

Software Required:

Xilinx ISE

Hardware Required:

1. FPGA kit.Specifications:Family : Spartans 3Device : XC3S400Package : TQ144


Program:

module countfpga1(clk, q);input clk;output [3:0]q;reg q;reg z;reg [19:0]c;

initial beginq=4'b0000;c=20'h00000;z=1’b0;endalways @(posedge clk)if(c==20'hfffff)beginc=20'h00000;z=~z;endelse c=c+1;always @(posedge z)if(q==4'b1111)q=4'b0000;elseq=q+1;

endmodule

32

Pin Details:


Result:Thus a four bit counter was synthesized and implemented using Verilog HDL.

33

Implementation of Pseudo Random Binary Sequence Generator

Ex.No:19 Date:

Aim:To synthesize and implement four bits pseudo random sequence generator using

Verilog HDL in the FPGA.

Software Required:Xilinx ISE, IMPACT




Circuit Diagram:

Program:module prbs(clk,q);

input clk;output [3:0]q;reg q;reg [19:0]c;reg p;reg ck;

initial beginck=1'b0;q=4'b0111;c=20'h00000;endalways @(posedge clk)if(c==20'hfffff)begin

34

D Q

CLK

D Q

CLK

D Q

CLK

D Q

CLKCLK

c=20'h00000;ck=~ck;endelse c=c+1;always @(posedge ck)begin p = q[3]^q[2];q[3]=q[2];q[2]=q[1];q[1]=q[0];q[0]=p;end

endmodule

Pin Details:

Pin Connector Pin numberInput FRC1 74 76 77 79 78 82 80 83Output FRC2 84 85 86 87 89 90 92 96CLK - 52 - - - - - - -

Result:

Thus a pseudo random binary sequence generator was synthesized and implemented using Verilog HDL.

35

Implementation of Accumulator

Ex.No:20 Date:

Aim:

To synthesize, simulate and implement accumulator using Verilog HDL in the FPGA.

Software Required:

Xilinx ISE, iMPACT

Hardware Required:

1. FPGA kit.Specifications:Family : Spartans 3Device : XC3S400Package : TQ144


Block diagram:

Program:module accumulator(a,q);

input [3:0]a;output reg [3:0]q;

initial q=4'b0000;always@(a)q=q+a;

endmodule

Pin Details:Pin Connector Pin numberInput FRC1 74 76 77 79 78 82 80 83Output FRC2 84 85 86 87 89 90 92 96CLK - 52

Result:

36

AccumulatorArithmetic Logic Unit

Result

Input

Thus a accumulator was synthesized and implemented using Verilog HDL.Simulation and Implementation of Arithmetic Logic Unit

Ex.No:21 Date:

Aim:To synthesize, simulate and implement Arithmetic Logic Unit using Verilog HDL in

the FPGA.

Software Required:Xilinx ISE, iMPACT




Control Logic:

OPCODE – decode logic

37

module opcod (op, os, bs,cs);input [2:0]op;output reg [2:0]os; output reg bs; output reg [1:0] cs;

always @ (op)beginos[0] = ~op[0] &op[2];os[1] = (op[0] &~op[1]&op[2])|( ~op[0]&op[1]&op[2]);os[2]= op[0]&op[1]&op[2];bs=op[1]&~op[2];cs[0]=~op[0]&op[1]&~op[2]; cs[1]=op[0]&~op[2];end

endmodule

38

Arithmetic Logic Unit

Program:module alu (a,b,cin,op,result, cout);

input a,b,cin;input [2:0]op;output result, cout;reg result;reg cout;reg clocal;reg blocal;reg [2:0]os; reg bs; reg [1:0] cs;

always @ (op)beginos[0] = ~op[0] &op[2];os[1] = (op[0] &~op[1]&op[2])|( ~op[0]&op[1]&op[2]);os[2]= op[0]&op[1]&op[2];bs=op[1]&~op[2];cs[0]=~op[0]&op[1]&~op[2]; cs[1]=op[0]&~op[2];endalways @(op or a or b or cin)case (cs)

39

2'b00:clocal=1'b0;2'b01:clocal = 1'b1;2'b10:clocal=cin;endcasealways @ (op or a or b or cin)case (bs)1'b0:blocal=b;1'b1:blocal= ~b;Endcasealways @ (op or a or b or cin)case (os)3'b000: begin result = a^blocal^clocal; cout = a&blocal |blocal&clocal|a&clocal;end3'b001:result = a& blocal;3'b010:result= a|blocal;3'b011: result = a^blocal;3'b100:result= ~a;endcase

endmodule

40

Pin Details:


41

Result:

Thus a arithmetic logic unit was synthesized, simulated and implemented using Verilog HDL.

Spice Simulation of MOS Differential Amplifier

Ex.No:22 Date:

Aim: To simulate MOS differential amplifier in schematic entry and SPICE program using

PSPICE.

Software Required: OrCAD Capture ,AD student

Schematic Entry:

// Transient analysis

42

V 1

F R E Q = 1 0 KV A M P L = . 1V O F F = 0

R 2

1 M E G

M 2

M b re a k N

V 41 2 V

0

V 31 2 V

00

M 1

M b re a k N

0

R 1

1 M E G

V 2

F R E Q = 1 0 KV A M P L = . 1 1V O F F = 0

R 3

4 0 0

0

43

// Frequency Analysis

R 3

4 0 0

R 1

1 M E G

0 V

V 31 2 V

0 V

M 2

M b re a k N

V+V 5

. 1 V a c0 V d c

0

-7 2 3 . 5 m V0

V 6. 1 V a c0 V d c

M 1

M b re a k N0 V V-

0

R 2

1 M E G

0

V 41 2 V

1 2 . 0 0 V

0 V

0

Program:

44

// Transient AnalysisMOS differential amplifierR1 1 2 9KR2 1 5 9KR3 4 7 4KV1 1 0 DC 12V2 0 7 DC 12V3 3 0 SIN 0 0.1 10K 0 1E-4 0V4 6 0 SIN 0 0.11 10K 0 1E-4 180M1 2 3 4 4 NMOD W=1u L=1uM2 5 6 4 4 NMOD w = 1u L=1u.Model NMOD NMOS (Kp=2 Vto=.7 Rg=0 Rds=1MEG Rb=0 Rs=5 Rd=5 CBD=5PF CBS=2pf CGSO=1pf CGDO=1pf CGBO=1pf).Tran (0.1m 1m).plot Tran v(2) v(5).PROBE.end

// Frequency AnalysisMOS differential amplifierR1 1 2 9KR2 1 5 9KR3 4 7 4KV1 1 0 DC 12V2 0 7 DC 12

45

V3 3 0 AC 0.1 V4 6 0 AC -0.1M1 2 3 4 4 NMOD W=1u L=1uM2 5 6 4 4 NMOD w = 1u L=1u.Model NMOD NMOS (Kp=2 Vto=.7 Rg=0 Rds=1MEG Rb=0 Rs=5 Rd=5 CBD=5PF CBS=2pf CGSO=1pf CGDO=1pf CGBO=1pf).AC dec 10K 10 10MEG.plot ac vm(2) vm(5).PROBE.end

46

Result:

Thus MOS differential Amplifier is designed and simulated by giving schematic and program input using PSPICE.

Inverter Layout and Simulation

Ex.No:23 Date:

Step I- Layout The basic transistor circuit of inverter is given in figure below

Inverter Circuit

Select coms0.25.rul foundry file from file menu. Click “new” and it with name “Inverter.msk” Begin to draw your layout with Microwind layout editor. You have already drawn NMOS layout and draw PMOS layout. (You can draw them similarly or there is a shortcut for MOS generator in the palette menu) Keep the dimensions as follows:

nMOS L = 0.25µm W = 0.5µmpMOS L = 0.25µm W = 1.25µm

Width of pMOS should be kept 2.5 time more than nMOS to have matching delays. Run DRC by selecting: >Analysis>Design Rule Checker If your layout is correct, then no messages will appear. If there are some errors, then

the warning messages will appear near the errors. Please modify your layout until no error messages appear.

Your layout should look like figure 1: Save your layout.

Step II - Add properties to input signals for simulation

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Click on the clock icon and then click on the input of the inverter in the layout then double click the clock of layout. A clock window appears & make sure the properties on the windows is below: Low-level 0.0V High Level 2.5V

Time low 1.95 Rise time 0.05 Time high 1.95 Fall time 0.05 ns

Push “Assign” Similarly assign the output node name “Out” Also assign the Vdd+ and Vss- to the PMOS and NMOS respectively (Make sure that

n-well is also assigned Vdd) Finally save your layout.

Step III- Simulation Click on “Run simulation” You will see the desired output of the inverter. The output waveform is shown in the given figure 2:

Figure 1: Inverter Layout

Figure 2: Inverter Output

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Result:

Thus layout of CMOS inverter is designed and simulated.

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vlsi record 2012

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