vlsi presentation on alu
TRANSCRIPT
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EEE 416
V L S I
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Design and Analysis of Arithmetic Logic Unit (ALU)
Submitted To:Dr. Ishfaqur Raza
Submitted by:Tawhid ReazwanMashfiqul IslamAsifur Rahman
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FunctionsAdditionSubtractionMultiplicationComparison
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Logic Functions
• Functions for Addition , multiplication , subtraction operations:
P1=A0S0’ + S1S0’B0’ + A0B0S1’S0 Q1=S0’ (S1’B0 + S1) P2=A1S0’ + S1S0’B1’ + A1B0S1’S0 Q2=S0’ (S1’B1+S1) + A0B2S1’S0 P3=A2S0’ + S1S0’B2’ + (A2B0+A1B1) S1’S0 Q3=S0’ (S1’B2+S1) + A0B2S1’S0 P4= A3S0’ + S1S0’B3’ + (A3B0+A2B1) S1’S0 Q4=S0’ (S1’B3+S1) + A0B3S1’S0
• Functions for Comparator operation: Pc1= (A0 + B0’)S1S0 Qc1=S1S0 Pc2= (A1 + B1’)S1S0 Qc2=S1S0 Pc1= (A2 + B2’)S1S0 Qc1=S1S0 Pc1= (A3 + B3’)S1S0 Qc1=S1S0
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Schematic diagram
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PLAN
•Logic gate design •Adder design•ALU construction•Spice extraction•Verification•Parameter determination
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Parameters:
•Rise Time
•Fall Time
•PCO
•Frequency
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So.S1
Operation
00 Addition
01 Multiplication
10 Subtraction
11 Comparison
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Design in Magic
•Basic Element•Conversion to a single Element
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2 input NAND
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3 input NAND
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4 input NAND
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2 input NOR
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3 input NOR
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Change in plan
•Using Inverter•Using usual logic gate•Mirror of Logic Diagram
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2 input AND
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3 input AND
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4 input AND
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2 input OR
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3 input OR
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NOT
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EXOR
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1 bit ADDER
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4 bit ADDER
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ALU
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Errors
•Error in magic labeling•Error in spice extraction•Error in spice file•Error in Hspice simulation
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Advantages
•Less number of gates•Less number of transistors•0.2mm *0.3mm(approximately)•Simplicity in magic design
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Conclusion
•After doing this project we have learnt how to construct and design an ALU. We tried a lot. Unfortunately we are not able to get the final output.