Viterbi Decoder Viterbi Decoder ProjectProject

Alon weinberg, Dan Alon weinberg, Dan ElranElran

Supervisors:Supervisors:

Emilia Burlak, Elisha Emilia Burlak, Elisha UlmerUlmer

GeneralGeneral

In this project we will implement the In this project we will implement the Viterbi Digital channel decoding Viterbi Digital channel decoding algorithm both in hardware and in algorithm both in hardware and in software on a Qualcomm Israel software on a Qualcomm Israel based platform, in order to learn based platform, in order to learn about digital communication about digital communication channels, the algorithm itself, the channels, the algorithm itself, the board and the working interface board and the working interface (SW/HW)(SW/HW)

Project GoalsProject Goals Studying the Viterbi algorithm and the convolutional code Studying the Viterbi algorithm and the convolutional code Viterbi decoder implementationViterbi decoder implementation Studying the board on which the implementation will take placeStudying the board on which the implementation will take place Studying the TI DSP on boardStudying the TI DSP on board Studying the arbiter and busses (synch. And async.) on board Studying the arbiter and busses (synch. And async.) on board PCI bus and interface (study and implementation)PCI bus and interface (study and implementation) H\W – Software interface (DSP – FPGAs)H\W – Software interface (DSP – FPGAs) H\W-software work loadH\W-software work load RAM model configurationRAM model configuration RAM interface module implementationRAM interface module implementation Working in high frequencies (theory+implementation)Working in high frequencies (theory+implementation) Good VHDL and C DSP programming knowledge and abilitiesGood VHDL and C DSP programming knowledge and abilities

The board (FMC)The board (FMC)

P LX-P C I - B ridge

FP G Axcv2000

FP G Axcv200

DSP

A rb ite rcon tro l C P LD

FP G Axcv300

P C I 16 b it , 33m hz

32 b

it

32 bit

32 bit 166m hz

Board usage Board usage We will implement on the DSP the software We will implement on the DSP the software

part which will contain the Chainback part which will contain the Chainback initiation module and interface to the initiation module and interface to the hardware. On the FPGA we will implement hardware. On the FPGA we will implement the hardware part, which includes the ACS the hardware part, which includes the ACS and branch metric blocks as well as and branch metric blocks as well as interface from the FPGA to the DSP.interface from the FPGA to the DSP.

There will be a Dual Port Ram on the FPGA There will be a Dual Port Ram on the FPGA in order to pass data between HW and SW. in order to pass data between HW and SW. In general the software will control the HW In general the software will control the HW By control registers.By control registers.

The board (FMC)The board (FMC)

Board bus ratesBoard bus rates

DSP works at 160 MHzDSP works at 160 MHz BUT BUT

Arbiter works at 40 MHz (Bottleneck) Arbiter works at 40 MHz (Bottleneck) Periferial BUS (PCI)Periferial BUS (PCI) Local BusLocal Bus PLX and DSP can master both busesPLX and DSP can master both buses Asynched I/O FIFOs connected to Asynched I/O FIFOs connected to

FPGAsFPGAs

Viterbi Decoding AlgorithmViterbi Decoding Algorithm

The Viterbi decoding algorithm is a state of the art algorithm used to decode convolutional binary codes (viewd as a trellis tree) used in communication standards (like Qualcomm’s CDMA standard).

The Viterbi decoder operates by finding the most likely decoding sequence for an input code symbol stream.

A Viterbi based A Viterbi based communication channelcommunication channel

Convolutional codes Convolutional codes

Convolutional codes add Convolutional codes add correlation to the input data correlation to the input data sequence by using delay elements sequence by using delay elements and modulo adders. Binary and modulo adders. Binary convolutional encoders can be convolutional encoders can be implemented with a feed forward implemented with a feed forward shift register and exclusive or shift register and exclusive or (XOR) gates.(XOR) gates.

Encoding methodEncoding method

Convolutional codes Convolutional codes (cont.)(cont.)

Input bits enter the shift register one bit Input bits enter the shift register one bit at a time. The outputs of the generator at a time. The outputs of the generator functions become the encoded output functions become the encoded output symbols. Each of the generator functions symbols. Each of the generator functions produce an output symbol for each input produce an output symbol for each input bit. The number of delay elements in the bit. The number of delay elements in the SHR define the state of the encoder and SHR define the state of the encoder and the constraint length. An encoder the constraint length. An encoder containing N memory elements has 2^N containing N memory elements has 2^N possible states and a K=N+1 constraint possible states and a K=N+1 constraint length.length.

Convolutional code, Trellis Convolutional code, Trellis tree and Viterbi algorithmtree and Viterbi algorithm

General Viterbi Decoder + General Viterbi Decoder + error check (feedback)error check (feedback)

in

B ranchM etric

C a lcu la tion

A C S (includ ingca lcu la tion o fqua lity b its)

E rror C ount

C TR L

C hain B ack

O U T

R A M

re-decode

N oiseG enera tor

Viterbi DecodingViterbi Decoding

The Viterbi decoder finds the most The Viterbi decoder finds the most likely path through the encoder likely path through the encoder Trellis. The 3 main steps in the Trellis. The 3 main steps in the process are :process are :

- Branch metric generationBranch metric generation- State metric generationState metric generation- ChainbackChainback

Implementation Implementation considerationsconsiderations

Fully parallel- N Trellis states are Fully parallel- N Trellis states are processed in parallel and each cycle a processed in parallel and each cycle a whole Trellis column is ready. This whole Trellis column is ready. This way we can also calculate the most way we can also calculate the most likely state during the process and likely state during the process and only output the decision bit. Easy for only output the decision bit. Easy for H/W implementation, fast. Takes a lot H/W implementation, fast. Takes a lot of FPGA space and resources of FPGA space and resources (exponential with K). Not commonly (exponential with K). Not commonly used.used.

Parallel ACS (k=1/2)Parallel ACS (k=1/2)

Implementation Implementation considerations (cont.)considerations (cont.)

Fully serial- each cycle one state is Fully serial- each cycle one state is ready. N cycles to process one whole ready. N cycles to process one whole Trellis column. More difficult H/W Trellis column. More difficult H/W implementation, N times slower. Takes a implementation, N times slower. Takes a little FPGA space without any correlation little FPGA space without any correlation to K (fixed amount of space taken).to K (fixed amount of space taken).

Partially parallel-serial- m<N states Partially parallel-serial- m<N states processed each cycle. Choose m by processed each cycle. Choose m by space and speed considerations (bigger space and speed considerations (bigger m: faster, more space).m: faster, more space).

Serial ACS Serial ACS

Implementation Implementation considerations (cont.)considerations (cont.)

Since the chip is used in a mobile cellular Since the chip is used in a mobile cellular phone, it should be very small, but still fast phone, it should be very small, but still fast enough in order to prevent delays in the enough in order to prevent delays in the data stream (the conversation). data stream (the conversation).

We chose the fully serial implementation, We chose the fully serial implementation, due to H/W bottleneck (board bus and SW due to H/W bottleneck (board bus and SW working rates).working rates).

Today most of the implementations are Today most of the implementations are partially serial-parallel, with a small m (2- partially serial-parallel, with a small m (2- 4).4).

Software implementationSoftware implementation

The software will have two major The software will have two major roles:roles:

- The Chainback blockThe Chainback block Receives the state metrics Receives the state metrics

calculated calculated in H/W and chains back in H/W and chains back the Trellis to the Trellis to find the most likely path.find the most likely path.

- General control of the whole process General control of the whole process (control the H/W through the control (control the H/W through the control registers).registers).

Software implementation Software implementation (cont.)(cont.)

The software will run on the DSP, The software will run on the DSP, over the VX Works operating over the VX Works operating systems (which is the real time systems (which is the real time operating systems used on the operating systems used on the CPU card).CPU card).

The code for the DSP will be The code for the DSP will be written in the C language.written in the C language.