Part A PresentationPart A Presentation

Implementation of DSP Algorithm on SoC

Student : Einat TevelStudent : Einat TevelSupervisor : Isaschar WalterSupervisor : Isaschar WalterAccompanying engineer : Emilia BurlakAccompanying engineer : Emilia Burlak

The project is conducted withThe project is conducted withcooperation of Rafael. cooperation of Rafael.

winter 2003/2004winter 2003/2004

Project Goals - ReviewProject Goals - Review Studying and investigating the architecture Studying and investigating the architecture

of System on Programmable Chip (SoC).of System on Programmable Chip (SoC). Deciding on the Software/Hardware Deciding on the Software/Hardware

partition to be implemented.partition to be implemented. Implementing a signal processing algorithm Implementing a signal processing algorithm

on the chosen platform.on the chosen platform.First Semester:First Semester:• Full understanding of the elements Full understanding of the elements

and studied environments.and studied environments.• Writing and Running examples on Writing and Running examples on

the evaluation board.the evaluation board.

Project ScheduleProject ScheduleSecond Part of First Second Part of First

SemesterSemester Studying the PowerPC processor.Studying the PowerPC processor.

Studying the EDK software for Studying the EDK software for developing SoC. developing SoC.

Studying the SoC design process.Studying the SoC design process.

Get familiar with the Xilinx’s Get familiar with the Xilinx’s evaluation board.evaluation board.

Writing and Running examples on the Writing and Running examples on the evaluationevaluation

board.board.

System ViewSystem View

PowerPC 405 Core

I-Cache

D-Cache

CoreConnect Processor Local Bus (PLB)

User Logic

External Memory

High Speed Peripherals

CoreConnect On-Chip Peripheral Bus (OPB)

Low Speed

Peripherals

PLB-OPB Bridge

FPGA Block RAM

FPGA Block RAM

Implementation ToolsImplementation Tools

• EDK - Embedded Development KitEDK - Embedded Development Kit• Provides a set of design tools and a wide selection of Provides a set of design tools and a wide selection of

standard peripherals required to build embedded standard peripherals required to build embedded processor systems.processor systems.

• XPS (Xilinx Platform Studio) – Provides an integrated XPS (Xilinx Platform Studio) – Provides an integrated environment for creating the software and hardware environment for creating the software and hardware specification flows.specification flows.

• Standard peripherals (GPIO, SDRAM, Clock Modules, Standard peripherals (GPIO, SDRAM, Clock Modules, Ethernet).Ethernet).

• GNU based software tools (C compiler, assembler, linker GNU based software tools (C compiler, assembler, linker and debugger) .and debugger) .

• Virtex-II Pro FF1152 Development BoardVirtex-II Pro FF1152 Development Board• Enables implementation of embedded processor based Enables implementation of embedded processor based

applications usingapplications using IP cores and customized modules.IP cores and customized modules.• Virtex II Pro FPGA (XC2VP30).Virtex II Pro FPGA (XC2VP30).• Two Integrated PowerPC Processors.Two Integrated PowerPC Processors.• Two memory blocks of 8Mx32 SDRAM memory each.Two memory blocks of 8Mx32 SDRAM memory each.

Virtex-II Pro FF1152 Virtex-II Pro FF1152 Development BoardDevelopment Board

CoreConnect CoreConnect ArchitectureArchitecture

Elements of the CoreConnect architecture:• PLB (Processor Local Bus): high

performance synchronous bus designed for connection of processors to high-performance peripherals devices.

• OPB (On-chip Peripheral Bus): general-purpose synchronous bus designed for connection of on-chip peripheral devices.

User CoresUser Cores

• Objective: Add a User Core to an Objective: Add a User Core to an embedded system, which implements embedded system, which implements a user-logic written in vhdl.a user-logic written in vhdl.

• The User core is to be attached to an The User core is to be attached to an embedded processor bus, such as embedded processor bus, such as OPBOPB or or PLBPLB..

• There are several configurations that There are several configurations that can be used to connect user cores and can be used to connect user cores and user logic to an embedded subsystem.user logic to an embedded subsystem.

Connecting User CoresConnecting User Cores IPIF (IP Interface) – a portable, pre-

designed bus interface, that takes care of the bus interface signals, bus protocol and other interface issues.

The IPIF presents an interface to the user logic called the IP InterConnect (IPIC).

User logic is a logic that has been designed with an IPIC interface to make use of the IPIF bus attachment and other services.

User logic that is designed with an IPIC has the advantage that it is portable and can be easily reused on different processor buses by changing the IPIF to which it is attached.

IPIF SchemeIPIF Scheme

User Core Reference User Core Reference DesignDesign

simplifies the task of attaching the IPIF to user logic.

The user core reference design is a VHDL file that instantiates the IPIF and provides most of the VHDL code required to create a user core.

The reference design provides a place to instantiate the user logic, which can be VHDL or a black box created from verilog, schematic, etc.

User Core Reference Design User Core Reference Design SchemeScheme

IPIF ExampleIPIF Example

Components - HardwareComponents - Hardware• PPC 405PPC 405• Plb2Opb BridgePlb2Opb Bridge• OPBOPB

• Uartlite : RS232Uartlite : RS232• GPIO: LEDsGPIO: LEDs• GPIO: Push ButtonsGPIO: Push Buttons• GPIO: DIPsGPIO: DIPs• SDRAM (8M*32)SDRAM (8M*32)

• PLBPLB• User CoreUser Core• BramBram

• System DCMSystem DCM• System RESETSystem RESET

User LogicUser Logic Receives 1 of 4 Receives 1 of 4

addresses addresses (“00”,”01”,”10”,”11”).(“00”,”01”,”10”,”11”).

Each address Each address correspond to a LED.correspond to a LED.

The appropriate LEDThe appropriate LED is is turned on/off according turned on/off according to the LSB of the data.to the LSB of the data.

The data returned is the The data returned is the data received + const, data received + const, when const is when const is determined by each determined by each address.address.(“00”: c=0,”01”: c=1, (“00”: c=0,”01”: c=1,

“ “10”: c=2, “11”:c=3)10”: c=2, “11”:c=3)

Bus2IP_Addr

Bus2IP_ClkBus2IP_CS

Bus2IP_Data

Bus2IP_RdCE

Bus2IP_Reset

Bus2IP_WrCE

IP2Bus_Data

LED

User

Logic

1 bit

4 bit

32 bit

User Logic – VHDL User Logic – VHDL (sample)(sample)

addr <= Bus2IP_Addr(28 to 29);addr <= Bus2IP_Addr(28 to 29);……if Bus2IP_CS = '1' and Bus2IP_WrCE = '1‘ then if Bus2IP_CS = '1' and Bus2IP_WrCE = '1‘ then data <= Bus2IP_Data(24 to 31);data <= Bus2IP_Data(24 to 31); case addr iscase addr is when "00" => led0 <= Bus2IP_Data(31); when "00" => led0 <= Bus2IP_Data(31); when "01" => led1 <= Bus2IP_Data(31); when "01" => led1 <= Bus2IP_Data(31); when "10" => led2 <= Bus2IP_Data(31); when "10" => led2 <= Bus2IP_Data(31); when "11" => led3 <= Bus2IP_Data(31); when "11" => led3 <= Bus2IP_Data(31); when others => null;when others => null; end case;end case;end if;end if;……..

Software – mainSoftware – main int main(){int main(){ Xuint32 Data=0, Res=0;Xuint32 Data=0, Res=0; Xio_Address addr;Xio_Address addr; unsigned int usec_time=50000;unsigned int usec_time=50000; xil_print(“***MY OPB-PLB USER LOGIC***”);xil_print(“***MY OPB-PLB USER LOGIC***”); check_sdram(); //calling check_sdram functioncheck_sdram(); //calling check_sdram function check_leds(); //calling check_leds functioncheck_leds(); //calling check_leds function addr=(Xio_Address)XPAR_PLB_USER_CORE_0_BASEADDR;addr=(Xio_Address)XPAR_PLB_USER_CORE_0_BASEADDR; while(1){while(1){ Xio_Out32(addr, Data);Xio_Out32(addr, Data); usleep(1);usleep(1); Res=XIo_In32(addr);Res=XIo_In32(addr); xil_printf(“Res=%d\n\r”, Res);xil_printf(“Res=%d\n\r”, Res); usleep(usec_time);usleep(usec_time); }}}}

Software – Memory Software – Memory Check FunctionCheck Function

void check_sdram(){void check_sdram(){…… temp=sdram_location;temp=sdram_location; // writing to all the memory addresses// writing to all the memory addresses for(loop_count=0;loop_count<mem_size;loop_count++){for(loop_count=0;loop_count<mem_size;loop_count++){

*sdram_location = loop_count;*sdram_location = loop_count; sdram_location++;sdram_location++;

}} sdram_location=temp;sdram_location=temp; // reading from all the memory address and comparing to expacted// reading from all the memory address and comparing to expacted for(loop_count=0;loop_count<mem_size;loop_count++){for(loop_count=0;loop_count<mem_size;loop_count++){

sdram_data_read = *sdram_location;sdram_data_read = *sdram_location;if(sdram_data_read!=loop_count) // failure – printing and exitingif(sdram_data_read!=loop_count) // failure – printing and exitingelse sdram_location++else sdram_location++

}} xil_printf("SDRAM Test Passed\n\r");xil_printf("SDRAM Test Passed\n\r");}}

Software – LEDs Check Software – LEDs Check FunctionFunction

void check_leds(){void check_leds(){ … …

XGpio_mSetDataDirection(XPAR_LEDS_4BIT_BASEXGpio_mSetDataDirection(XPAR_LEDS_4BIT_BASEADDR, 0x00);ADDR, 0x00);

for (count=0; count < 16; count++) {for (count=0; count < 16; count++) {

XGpio_mSetDataReg(XPAR_LEDS_4BIT_BASEADDXGpio_mSetDataReg(XPAR_LEDS_4BIT_BASEADDR, ~count);R, ~count);

usleep(100000);usleep(100000);xil_printf("Leds Count=%d\n\r",count);xil_printf("Leds Count=%d\n\r",count);

}} xil_printf("LEDS Test Passed\n\r");xil_printf("LEDS Test Passed\n\r");}}

OutputOutput

CommentsComments

The VHDL code was tested using The VHDL code was tested using ModelSim.ModelSim.

Environment Testing – Using LEDs.Environment Testing – Using LEDs. The Evaluation Board is new, The Evaluation Board is new,

therefore required adjustments in therefore required adjustments in the UCF file.the UCF file.

Other Debug tools, such as Chip-Other Debug tools, such as Chip-Scope, where not used.Scope, where not used.

Other ExamplesOther Examples

Running Xilinx’s examples:Running Xilinx’s examples: Basic Components (GPIO).Basic Components (GPIO). Additional Memory.Additional Memory. 2 PowerPCs.2 PowerPCs. IPIF example of LEDs Brightness.IPIF example of LEDs Brightness.

User Logic:User Logic: On OPBOn OPB On PLBOn PLB

Goals – Second PartGoals – Second Part

Implementing a signal processing Implementing a signal processing algorithm based on a FIR/IIR algorithm based on a FIR/IIR Filter with Programmable Filter with Programmable coefficients.coefficients.• Simulating and checking the code of Simulating and checking the code of

the algorithm in hardware and the algorithm in hardware and software. software.

• Running the algorithm on the board.Running the algorithm on the board.

Project schedule Project schedule second semester second semester

11st st week:week: • Defining the algorithm to be implemented.Defining the algorithm to be implemented.

22ndnd-3-3rdrd week: week: • Design of the algorithm – block scheme.Design of the algorithm – block scheme.

44th th week:week: • Dividing the workload Software/Hardware Dividing the workload Software/Hardware

and Estimating the FPGA’s volume. and Estimating the FPGA’s volume.

55thth-6-6th th week:week: • Detailed design of each block from the Detailed design of each block from the

scheme.scheme.

Project schedule Project schedule second semester second semester

(cont)(cont)

77thth-9-9thth week: week:• Hardware implementation Hardware implementation • Software implementation.Software implementation.

1010thth-end:-end: • SimulationSimulation• SynthesisSynthesis• Checking the algorithm using the Checking the algorithm using the

evaluation board. evaluation board.

Thank YouThank You