vhdl templates 2009

8/21/2019 VHDL Templates 2009

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SMR: 2065

Advanced Training Course on FPGA Design and VHDL for HardwareSimulation and Synthesis

26 October 2009 - 20 November 2009Trieste - Italy

___________________________________________________________________

VHDLSyntax Templates

andSynthesis Constructs

Prepared and Edited by:

ICTP Multidisciplinary LaboratoryMLAB

ICTP Multidisciplinary Laboratory, MLAB, Trieste, Italy 1/19


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Table

of

Contents

SyntaxTemplates

I. Module Structure

A. Library 2

B. Entity 2

C. Architecture 3

D. Component 4

II. Data Objects

A. Signal 5

B. Constant 5

C. Variable 6

III. Concurrent Statements

A. Boolean Equations 7

B. when-elseCond. Signal Assignment 7

C. with-select-whenCond. Signal Assignment 7

IV. Sequential Statements

A. Process 8

B. if-then-elseConditional Statement 8

C. case-whenConditional Statement 9

D. for-loop Statement 9E. while-loopStatement 9

V. DataTypes 10

VI. ConversionFunctions 11

VII. Operators 11

SynthesisConstructs

I. Accumulator 12

II. Adder 12

III. SimpleComparator 12

IV. Up/DownCounter 13

V. BinarytoGreyConverter 13

VI. LinearFeedbackShiftRegister 14

VII. 3to8Decoder 14

VIII. 8to3Encoder 15

IX. DTypeFlipFlop 15

X. DebouncingCircuit 16

XI. 4to

1Multiplexer

16

XII. PISOShiftRegister 17

XIII. SIPOShiftRegister 17

XIV. TriStateBuffer(2Examples) 17

XV. FiniteStateMachine 28


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SyntaxTemplates

I.

Module

Structure

A. Library

Library:A collection of VHDL design units, typically used to hold reusable components and type declarations.

Package:A design unit often used to gather related component, type, constant, and subprogram declarations. Packages are compiled to

libraries.

Syntax:

library ;use . . [ all| ] ;

Example:library I EEE;use I EEE. st d_l ogi c_1164. al l ;use I EEE. numer i c_st d. al l ;

B. Entity

Entity: An abstraction of a system, board, chip, component, or logic gate. An entity, or design entity, is defined by an entity declarationand

architecture body.

Entity Declaration: A design unit that defines a design entitys interface.

Mode:Associated with ports declared in an entity declaration. A mode defines the direction of signal communication for an entity, and whether

a signal is readable, writable, or both.

In:used for signals (ports) that are inputs-only to an entity.

Out: used for signals that are outputs-only and for which the values are not required internal to an entity.

Buffer: used for signals that are outputs, but for which the values are required internal to the given entity.

Inout: used for signals that are truly bidirectional.


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Syntax:

entity i sport (

: ;

) ;end ;

Example:

entity or _ent i t y i sport(

i nput _1: i n st d_l ogi c;i nput _2: i n st d_l ogi c;out put : out st d_l ogi c

) ;end or _ent i t y;

C. Architecture

Architecture Body:A design unit that describes the behavior or structure of a design entity. An entity declaration is paired with an architecture

body to form a complete design entity.

Syntax:

architecture of is

{ | | | | }

begin

{ ||| }

end ;

Example:

architecture or _ent i t y_ar ch of or _ent i t y is

signal inp1: st d_l ogi c;

begin

i np1


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D. Component

Component:A design entity instantiated in another design entity. Components are used to create hierarchy and are essentials in structural

descriptionsof a design entity.

Component Declaration:A template that defines the interface of a component. At the time of synthesis, a component must be bound to a specific

entity declaration and architecture body pair.

Syntax:

component i sport (- - port declarations as done

in ent i t ydeclarations) ;end component;

Example:

component or _ent i t y i sport(i nput _1: i n st d_l ogi c;i nput _2: i n st d_l ogi c;out put : out st d_l ogi c

) ;end component;

Component Instantiation:

Syntax:

: port map(

=> ,

) ;

Example:

or _ent _1: or _ent i t yport map(

i nput _1 => i nput _1_si g,

i nput _2 => i nput _2_si g,out put => out put _si g) ;


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II.DataObjects

A. Signal

Signalsare the most commonly used data object in synthesis designs. Signals have projected output waveforms. They are typically used to store

internal values or to connect components.

Signal Declaration:

Syntax:

signal : ;

Examples:

signal por t _ i : s td_ l ogi c;signal bus_si gnal : st d_l ogi c_vect or ( 15 downt o 0) ;signal count : i nt eger r ange 0 t o 31;

Signal Assignmentsare scheduled, not immediate; they update projected output waveforms.

Syntax:


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Constant Declaration:

Syntax:

constant : : = ;

Examples:

constant st at e_1 : std_logic_vector : = "01" ;constant st at e_2 : std_logic_vector : = "10" ;constant addr _max: integer : = 1024;

C. Variable

Variables can be used in processes and subprograms, that is, in sequential areas only. The scope of a variable is the process or subprogram.Variables are most commonly used as the indices of loops o for the calculation of intermediate values, or immediate assignment. To use

the value of a variable outside of the process or subprogram in which it was declared, the value of the variable must be assigned to a

signal.

Variable Declaration:

Syntax:

variable : ;

Examples:

variable count _v: integer range 0 t o 15;variable dat a_v: std_logic_vector( 7 downt o 0) ;variable condi t i on_v: boolean;

Variable Assignmentsare immediate, not scheduled.Syntax:

: =

Example:

bool ean_v : = t r ue;t emp_v( 3 downto 0) : = sl _vect or _si gnal ( 7 downto 4 ) ;


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III.ConcurrentStatements

A. Boolean Equations (the basis of most of VHDL codes is the logical interactions between signals).

Syntax:

[not] [[and |or |nor |nand |xor |xnor | ][ ]

];

Example:

X


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IV.SequentialStatements

A. Process

Processes are essentials in behavioral descriptionsof a design entity. They facilitate clock-edge specification as well as synchronization among

signal assignments. Processes are most commonly used when a signal assignment is dependent on changes in another. The dependency therein

should be reflected in the process sensitivity list.

Syntax:

[: ]process ( )

{ ||| }

begin{ }

end process;

Example:

out put _pr ocess: process( f l ag_si gnal )

beginif f l ag_si gnal = ' 1' then

out put _vect or


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C. case-when Conditional Statement

Syntax:

case is{ when => ; }when => ;

end case;

Example:

case state iswhen 00" => i nt eger_si gnal i nt eger_si gnal i nt eger_s i gnal


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V.DataTypes

A. Enumeration Types

Values are user-defined; commonly used to define states for a state machine.

Syntax:

type is ( ) ;

Examples:

type s t at e_t ype is ( s t0, st 1, st 2) ;

B. std_logic & std_logic_vector

The std_logicdata type is the most frequently used type in VHDL. It is part of the std_logic_1164 package in the IEEE libraryand is used to represents regular two-valuelogical values (as '0' and '1') as well as other common logic values like high impedance ('Z').

Further to this data type is the std_logic_vector, which represents busses in VHDL. This data type acts like an array of std_logic 'bits' in order represent such a collection

STD_LOGIC - - ' U' , ' X' , ' 0' , ' 1' , ' Z' , ' W' , ' L' , ' H' , ' - 'STD_LOGIC_VECTOR - - Natur al Range of STD_LOGI C

C. boolean

BOOLEAN - - Tr ue or Fal se

D. bit & bit_vector

BIT - - ' 0' , ' 1BIT_VECTOR - - Ar r ay of bi t s

E. ranged types

There are a couple of ways to represent numbers in VHDL. One is to use the binary/hexadecimal representation afforded by the std_logic_vector orbit_vector. While this isuseful when representing physical signals, integers are easier to use. As such an integer type and two subtypes have been defined in VHDL, but they are not implemented inwires. They are translated to busses. Thus, to limit the physical wires that are implemented by the design, and hence make the implementation of the design more efficient, its

advisable to limit integers to specified ranges.

INTEGER - - 32 or 64 bi t sNATURAL - - I nt egers >= 0POSITIVE - - I nt eger s > 0


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VIConversionFunctions

The VHDL language allows the usage of conversion functions. These conversion functions are generally used to convert from one type to another.

There are multiple conversion functions provided in different libraries. This is why it is important to reference the correct library in which theconversion function is available.

VIIOperatorsDefinedintheVHDLLanguage

+ Addi t i on

- Subt r act i on* Mul t i pl i cat i on/ Di vi de

Mod Modul us** Power Oper at or ( i . e. 2**8 r et ur ns 256)

The f ol l owi ng operat or s ei t her concat enat e sever al bi t s i nt o a bus or r epl i cat e a bi t or combi nat i on of bi t s mul t i pl et i mes.

a & b & c Concat enat e a, b and c i nto a bus

The f ol l owi ng l ogi cal operat or s ar e used i n condi t i onal TRUE/ FALSE st at ements such as an i f st at ement i n or der t ospeci f y the condi t i on f or t he oper at i on.

NOT Not TrueAND (NAND) Both I nput s TrueOR (NOR) Ei t her I nput Tr ue

XOR (XNOR) Onl y one I nput True= I nputs Equal/ = I nput s Not Equal< Less- t han Gr eat er - t han>= Gr eater- t han or Equal


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Synthesis

Constructs

Accumulator wi th synchronous Reset and Chip Enable

process (, )begin

if =' 1' and ' event thenif =' 1' then

' 0' ) ;elsif =' 1' then


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Up/Down Counter with Load, Chip Enable and asynchronous Reset

process (, )begin

if =' 1' then ' 0' ) ;elsif =' 1' and ' event then

if =' 1' thenif =' 1' then


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8bit Linear Feedback Shift Register (LFSR)

process( , )begin

if ( = ' 1' ) then ' 0' ) ;elsif ( ' event and =' 1' ) then

if =' 1' then( 7 downto 1)


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8-to-3 Encoder

process( , , )begin

if ( = ' 1' ) then


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Debouncing circuit

Pr ovi des a one- shot pul se f r om a non- cl ock i nput , wi t h r esetD_I N: in STD_LOGIC;RESET: in STD_LOGIC;c l ock: in STD_LOGIC;Q_OUT: out STD_LOGIC) ;

**I nser t t he f ol l owi ng bet ween t he ' ar chi t ect ur e' and ' begi n' keywor ds**signal Q1, Q2, Q3 : st d_l ogi c;

**I nser t t he f ol l owi ng af t er t he ' begi n' keywor d**process( cl ock, RESET)begin

if ( RESET = ' 1' ) thenQ1


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Parallel In Serial Out Shif t Register

process ( , )begin

if = ' 1' then


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Finite State Machine

Moore State Machine A state machine in which outputs change synchronously with respect to the clock.

Mealy State MachineA state machine with outputs that may change asynchronously with respect to the clock.

Exampl e usi ng enumerat ed t ypes:

I nser t t he f ol l owi ng i n t he ar chi t ect ur e bef ore the begi n keywor d ( use descr i pt i ve names f or t he st at es) :

type st at e_t ype is ( st 1_, st 2_, . . . ) ;signal cur r ent _st at e, next _st at e : st at e_t ype;

Decl ar e i nt er nal si gnal s f or al l out put s of t he st at e machi ne:

signal _i : std_logic; - - exampl e out put si gnalI nser t t he f ol l owi ng i n t he ar chi t ect ur e af t er t he begi n keywor d:

SYNC_PROC: process ( CLOCK, RESET)begin

if ( =' 1' ) thencur r ent _s t at e


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NEXT_STATE_DECODE: process ( st at e, , , . . . )begin

- - decl ar e def aul t st at e f or next _st at e t o avoi d l at chesnext _st ate

if = ' 1' thennext _st at e

if = ' 1' thennext _st at e next _st at e

next _st at e

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