cpre 583 reconfigurable computing lecture 1: wed 8/26/2009 (course overview, vhdl overview 1)
DESCRIPTION
CPRE 583 Reconfigurable Computing Lecture 1: Wed 8/26/2009 (Course Overview, VHDL Overview 1). Instructor: Dr. Phillip Jones ([email protected]) Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA. http://class.ece.iastate.edu/cpre583/. Class Introduction. - PowerPoint PPT PresentationTRANSCRIPT
1 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
CPRE 583Reconfigurable ComputingLecture 1: Wed 8/26/2009
(Course Overview, VHDL Overview 1)
Instructor: Dr. Phillip Jones([email protected])
Reconfigurable Computing LaboratoryIowa State University
Ames, Iowa, USA
http://class.ece.iastate.edu/cpre583/
2 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Class Introduction• Class Survey (by next class, [email protected])
– Background (year in school, VHDL/Verilog, EE/CPRE background, ISU login ID)
– What would you like to get from this class
• Syllabus
• Course Expectations– Reinforce research fundamentals– Asking the right question
• VHDL handbook (source Synplicity)– http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)
• VHDL online tutorials– http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html– http://www.vhdl-online.de/tutorial/
3 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
• Basic objectives and topics covered in this class.
• VDHL is NOT a programming language. It is a means to describe hardware.
What you should learn
4 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
• Basic components of an FPGA (Chapter 1)
• Overview of ways in which reconfigurable computing can be integrated into a system (Chapter 2)
• Examples of reconfigurable systems (Chapter3)
• Managing the reconfiguration of systems (Chapter 4)
5 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
A
B
X
opcode {+, -, AND, OR}
Behavior VHDL: ALUcompnt ALU (A,B,opcode,X) case opcode when => opPlus X <= A + B; when => opSub X <= A – B; when => opAND X <= A and B; when => opOR X <= A or B; end case;end component;
ALU
Structural VHDL: ALUcomponent ALU (A,B,opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X);end component;
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
6 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
A
B
X
opcode {+, -, AND, OR}
A
B
X
addAB
subAB
andAB
orAB
4:1Mux
opcode {+, -, AND, OR}
2Xadd
Xsub
Xand
Xor
ALU
ALUStructural VHDL: ALUcomponent ALU (A,B,opcode, X) addAB(A,B,Xadd); subAB(A,B,Xsub); andAB(A,B,Xand); orAB(A,B,Xor); 4:1mux(opcode, Xadd,Xor, Xand,Xor,X);end component;
7 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
Abstraction that allows– Reasoning about computation
• Correctness• Extraction of parallelism
– Transformations for optimization– Guarantee Properties
FPGA
Mem
ory
CPU
8 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
Abstraction that allows– Reasoning about computation
• Correctness• Extraction of parallelism
– Transformations for optimization– Guarantee Properties
Mem
ory
Function1
Function2
Function4
Function3
9 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
Abstraction that allows– Reasoning about computation
• Correctness• Extraction of parallelism
– Transformations for optimization– Guarantee Properties
Mem
ory
Function5
Function1
Memory
Function2
Function3
Function4
Memory
Memory
Memory
10 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topicsAgenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
• Streaming Applications
• Data Parallel Applications
• Fix/Floating Point Computations
• Performance Trade-offs
• Fault Tolerance
11 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
AB
addABX A
BxorAB
X AB
andABX A
BorAB
X
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0001
0 00 11 0 1 1
A B X0111
2-input Look Up Tables (LUTs)FPGA
LUT LUT LUT LUT
LUT LUT LUT LUT
LUT LUT LUT LUT
LUT LUT LUT LUT
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
X <= A+B; X <= A xor B; X <= A and B; X <= A or B;
12 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
FPGA
LUT addAB LUT LUT
LUT xorABLUT LUT
LUTandAB LUT LUT
LUT orAB LUT LUT
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
AB
addABX A
BxorAB
X AB
andABX A
BorAB
X
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0110
0 00 11 0 1 1
A B X0001
0 00 11 0 1 1
A B X0111
2-input Look Up Tables (LUTs)
X <= A+B; X <= A xor B; X <= A and B; X <= A or B;
13 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Main topics
Lectures on interesting uses of FPGAs. Ideally covering topics that the class would like to learn more about.
Please give suggestions as the semester progresses.
Agenda
1. Overview (2.5 Weeks) a. Reconfigurable HW b. VHDL
2. Computation Models (2.5 Weeks)
3. Applications / Concerns of FPGAs (4 Weeks)
4. Mapping logic to FPGAs (3 Weeks)
5. Case Studies (1 Week)
14 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
15 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)
ML507Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
16 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
17 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC SerialUART Echo.vhd
18 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC SerialUART
Echo.vhd(Modify to
capitalize only (a-z))
19 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Echo.vhdEthernet(UDP/IP)
20 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PCEcho.vhd
(Modify to count strings (e.g. corn!))
Ethernet(UDP/IP)
21 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Echo.vhdEthernet(UDP/IP)
22 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PCEcho.vhd
(Edge detection)Ethernet(UDP/IP)
23 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
24 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
25 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
FPGA
PC Display.cEthernet(UDP/IP)
Power PC
User Defined Instruction
Monitor VGA
26 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problems (MPs)Agenda
0. Platform Introduction
1. Network String Matching
2. Image: Edge Detection
3. Image: PPC coprocessor
4. Final Projects(~6 weeks)
• Choose your own topic
• Groups of 2-3 (maybe 4 for a large enough project)
• Encouraged to take on aggressive projects
27 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Review Syllabus
• Objects
• Expectations
• Grading breakdown
• MP grading policy: (more flexible for Distance Students)– Up to 5% added for early completion (Fri Midnight)– -5% after Fri Midnight– -10% additional after Monday Midnight– -10% additional after Tue Midnight– After Wed Midnight will make a note.
28 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What is Reconfigurable Computing?
• Ask wiki: http://en.wikipedia.org/wiki/Reconfigurable_computing
• Computing on a medium that is not fixed• Examples:
– rDPA (course grain reconfiguration)– FPGA (fine grain reconfiguration)– General Purpose Processor (not really)
underlining hardware typical executes a relatively small fixed instruction set.
29 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are rDPAs?
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
30 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are rDPAs?
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
31 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are rDPAs?
• rDPA: reconfigurable Data Path Array• Function Units with programmable interconnects
ALU ALU ALU
ALU ALU ALU
ALU ALU ALU
Example
32 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are FPGAs?
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Configurable Logic Block
33 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are FPGAs?
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
CLB CLB CLB CLB
Configurable Logic Block
34 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
What are FPGAs?
• FPGA: Field Programmable Gate Array• Sea of general purpose logic gates
CLB CLB
CLB
CLB
CLB CLB CLB CLB
Configurable Logic Block
35 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB CLB
CLB CLB
36 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
00000001
11101111
ABCD Z
37 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
00000001
11101111
ABCD Z
00
01
ANDZA
BCD
38 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
00000001
11101111
ABCD Z
01
11
ORZA
BCD
39 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
4 input Look Up Table
X000X001
X110X111
ABCD Z
01
11
2:1Mux
CD
B
Z
40 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
41 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
DFF
PIP Programmable Interconnection Point
42 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some FPGA Details
CLB
CLB CLB
LUTABCD
Z
DFF
PIP Programmable Interconnection Point
43 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
FPGA Usage Models
FastPrototyping
PartialReconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
•Experimental ISA
•Experimental Micro Architectures
• Image Processing
• Computational Biology
CPU + Specialized HW - Sparc-V8 Leon
• Remote Update
• Fault Tolerance
• Run-time adaptation• Run-time Customization
44 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Development Platform Overview
• ML507 Evaluation Platform User Guide (pgs. 14-16)– http://www.xilinx.com/support/documentation/boards_and_kits/
ug347.pdf
45 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Machine Problem 0 (MP0) Short Overview
• Officially assigned Fri (8/28), Due Friday (9/4). – Note: 1 week
• Purpose: Make sure you can run the tools. Very light VHDL coding.
• Primary Tasks:– Run the echo circuit without modifications– Run the echo circuit with a modification to convert lower
case ASCII characters to upper case.
• Distance Students: Test using NX for remotely access xilinx.ece.iastate.edu. You can download the NX client from:– For Windows: http://www.nomachine.com/download-client-windows.php– For Linux: http://www.nomachine.com/download-client-linux.php– For MAC OS: http://www.nomachine.com/download-client-macosx.php– For Solaris: http://www.nomachine.com/download-client-solaris.php
46 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
VHDL basics
• VHDL: (V)HSIC (H)ardware (D)escription (L)anguage– VHSIC: (V)ery (H)igh (S)peed (I)ntegrated (C)ircuit
• It is NOT a programming language!!!
• It is a Hardware Description Language (HDL)
• Conceptually VERY different form C,C++
• Some links to VHDL tutorials– http://www.seas.upenn.edu/~ese201/vhdl/vhdl_primer.html– http://www.vhdl-online.de/tutorial/– http://hapssupportnet.synplicity.com/download/VHDL-Handbook.pdf (quick ref)
47 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
• C is inherently sequential (serial), one statement executed at a time
• VHDL is inherently concurrent (parallel), many statements execute (simulate) at a time
48 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
49 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 1Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
50 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 1
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
51 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
52 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
“Simulates in parallel ever delta time step”
53 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 1B = 1C = 1X = 1Y = 1Z = 1Ans = 1
“Simulates in parallel ever delta time step”
Snap shot after input change
54 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
55 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
Different
56 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
Snap shot after input change
57 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 2
“Simulates in parallel ever delta time step”
58 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Some Key Differences from C
C example VHDL example
A = B + CX = Y + ZAns = A + X
Initially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
Current Values:A = 2B = 1C = 1X = 2Y = 1Z = 1Ans = 4
“Simulates in parallel ever delta time step”
59 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
60 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(1)
X(1)
Ans(1)
61 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(2)
62 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + CX <= Y + ZAns <= A + X
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(4)
63 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Corresponding circuit (More realistic)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(1)
X(1)
Ans(1)2ns
2ns
2ns
64 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(2)
Corresponding circuit (More realistic)
2ns
2ns
2ns
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
65 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
VHDL exampleInitially: A,B,C,X,Y,Z,Ans =1
“Simulates in parallel ever delta time step”
+
+
B(1)
C(1)
Y(1)
Z(1)
+
A(2)
X(2)
Ans(4)
Corresponding circuit (More realistic)
2ns
2ns
2ns
A <= B + C after 2nsX <= Y + Z after 2nsAns <= A + X after 2ns
66 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Typical Structure of a VHDL FileLIBRARY ieee;
ENTITY test_circuit IS PORT(B,C,Y,Z,Ans);END test_circuit;
ARCHITECTURE structure OF test_circuit IS signal A : std_logic_vector(7 downto 0); signal X : std_logic_vector(7 downto 0);
BEGIN
A <= B or C;
END
Include Libraries
Define component name andInput/output ports
Declare internalsignals, components
Implement components functionality
67 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Next Lecture
• Basic components of an FPGA• VHDL overview cont.
68 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Questions/Comments/Concerns
69 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Fast Prototyping Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
70 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Highly Parallel ApplicationsFast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
71 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
System on Chip (SoC) Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
72 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Full Reconfiguration Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)
73 - ECpE 583 (Reconfigurable Computing): Course overview, VHDL Overview 1 Iowa State University (Ames)
Partial Reconfiguration Fast
PrototypingPartial
Reconfiguration
FullReconfiguration
ParallelApplications
System onChip (SoC)