vhdl lecture 1

7/27/2019 Vhdl Lecture 1

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EE3801 Advanced Logic Circuits 1

Lecture 10 :

Introduction to VHDL

(Part 1)


Session Overview Digital Systems What is VHDL

Why VHDL? (Advantages, Disadvantages)

General Structure of VHDL Entity (Declaration /

Architecture)

PORT statement

IEEE Standard 1164

Entity Architectures


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Digital Systems

Digital Processing

Input from Real WorldSwitches , TTL. RS-232

Anal og (sound, v ideo ,)

A/D (Dis cret e Levels )Synchronizer (Discrete Time)

Data PathsRegisters,

ALU,Memory(muscle)

Control PathFSMs(brain)

Output to the Real WorldSwitches , TTL. RS-232

Anal og (sound, v ideo ,)


Implementation of Digital Systems

We have Several Alternatives:

1. Start with gates: AND, OR, NAND, NOR, NOT, etc.

Implemented with SSI (requires the most wiring).

2. Use logic prototyping (Registers, Counters, Shift Registers, Multiplexors,

Selectors, etc.

implemented with MSI (requires less wiring).

3. Progress to PALs, PLDs, CPLDs, FPGAs, ASICs, Custom VLSI chips.

These blocks require the least wiring. Designing them with gates is not very productive and error prone

We need a higher level language such as VHDL or Verilog to

specify the programming of PALs, CPLDs, and FPGAs.


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HDL-based design flow

For ASICs, verification and fitting phases areusually much longer, as a fraction of overall

project time.


VHDL Developed in the mid-1980s under DoD

sponsorship

Mandated for federally-sponsored VLSI designs

Used for design description, simulation, and

synthesis

Synthesis became practical in the early 90s and

use of VHDL (and Verilog) has taken off since

then

Only a subset of the language can be

synthesized


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VHDL

VHSIC Hardware Description Language A double acronym

Language to express digital systems

Structural

Behavioral

Timing

Rich and powerful language

Basic standard environment

Supports both Hardware and Softwareconcepts


VHDL Advantages: Documentation

Shorter design cycle

Improved design quality

Vendor and technology independence

Lower design cost

Design management

Disadvantages:

A change of culture Away from Schematic-based Design

towards Language-based Design

Cost of getting started Selecting and paying for tools


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What Can be Synthesized by VHDL

Combinational Functions Multiplexors, Selectors, Encoders, Decoders,

Comparators, Parity Generators,

Adders, Subtractors, ALUs,

Multipliers

Miscellaneous logic

Control Logic

FSM

Synchronizers


Things to Remember

VHDL is a programming language.

Many good and bad programs have been (will be) written.

Functionality is important BUT not enough!

Style is important.

Clarity is important.

Synthesis is hard.

Fitter programs take clues from your VHDL code.

Decomposition of a large design into smaller,

understandable sub-parts is essential.


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VHDL Entity and Architecture

Concept System is a collection of modules. Architecture: detailed description of the

internal structure or behavior of a module.

Entity: a wrapper for the architecture

that exposes only its external interfaces,

hiding the internal details.


Design Entity

(Declaration/Architecture)

Mux.2 x 1

y

a

b

sel

ENTITY muxISPORT ( a, b, sel :IN std_logic;

y :OUT std_logic);END mux;

ARCHITECTUREBehavioral OF mux IS

BEGINy


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Synthesis Result


Terminologies VHDL is case Insensitive

Comments are represented by --

Each statement is terminated with a semicolon ;

Each component is described in two parts:

Entity Declaration (Interface to the outside world)

Entity Architecture (Under the hood)

There is an enumeration for inputs defined in IEEEstandard package


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Port

Each I/O signal in an entity declaration is called a

PORT (Analogous to a pin in schematic) withfollowing attributes:

Name

Mode : Direction of data flow IN

OUT

BUFFER

INOUT

Type : Data type on this port. boolean

bit

bit_vector

std_logic


Port


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IEEE Standard 1164

IEEE 1164 provides a standard data type (std_logic)

which can take NINE different values: U un initialized

X unknown

0 logic zero

1 logic one

Z high impedance

W weak unknown

L weak logic zero

H weak logic one

- dont care

To use this standard data type:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;


Entity Declaration Example

eqcomp4

4

4a

b

equals


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Entity Architecture

An Architecture describes the content of an entity.

VHDL allows various styles of architecture:

Behavioral Description

Dataflow Description

Structural Descriptions


Architecture (Behavioral)

ARCHITECTURE behavioral OF eqcomp4 IS

BEGIN

comp : PROCESS (a,b)BEGIN

IF a =bTHENequals


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Architecture (Behavioral)

Behavioral architecture deals with high level set of

statements rather than the structure ornetlist.

PROCESS ( sensitivity list) Statement

When any of the signals in the list change value the processis executed

Statements are executedsequentially within a process

All signals are updated at the end of the process


Architecture (Dataflow)


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Architecture (Dataflow )

Dataflow architecture specifies how data is

transferred from signal to signal and input to outputwithout use of sequential statements.

Note that there is no PROCESS( ) statement.

Concurrent signal assignment.


VHDLHierarchy


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Architecture (Structural)


Architecture (Structural)

Structural designs are hierarchical

Note COMPONENT (When an entity is used insideof another entity)

Each PORT MAP instantiates a component.

Note use of SIGNAL to interconnect components


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Summary

Digital Systems What is VHDL

Why VHDL? (Advantages, Disadvantages)

General Structure of VHDL Entity (Declaration /

Architecture)

PORT statement

IEEE Standard 1164

Entity Architectures

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