vhdl : case study

VHDL : case studyVHDL : case studyFrequency MeterFrequency Meter

P. BakowskiP. Bakowski

[email protected]@ieee.org

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General specificationsGeneral specifications

The general structure of the frequency meter has The general structure of the frequency meter has

three inputsthree inputs: :

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three inputs: three inputs:

clk_capclk_cap signal that carries the signal that carries the measured frequencymeasured frequency

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clk_capclk_cap signal that carries the measured frequencysignal that carries the measured frequency

clk_seqclk_seq signal that imposes the signal that imposes the operational operational

sequencesequence of the meterof the meter

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clk_capclk_cap signal that carries the measured frequency signal that carries the measured frequency

and and

clk_seqclk_seq signal that imposes the operational signal that imposes the operational

sequence of the metersequence of the meter

gogo signal that activates the sequencersignal that activates the sequencer

activeactive

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clk_capclk_cap signal that carries the measured frequency signal that carries the measured frequency

and and

clk_seqclk_seq signal that imposes the operational signal that imposes the operational

sequence of the metersequence of the meter

gogo signalsignal

An two An two output signalsoutput signals to two to two 77--segment displayssegment displays

driven by the output decoder of the frequency meter.driven by the output decoder of the frequency meter.

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ua_gua_g

gogo

da_gda_g

clk_capclk_cap

clk_seqclk_seq

aa

bb

ccddee

ggff

aa

bb

ccddee

ggff

unitsunits

tenstens

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ua_gua_g

gogo

da_gda_g

clk_capclk_cap

clk_seqclk_seq

aa

bb

ccddee

ggff

aa

bb

ccddee

ggff

unitsunits

tenstens

sequencersequencer

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ua_gua_g

gogo

da_gda_g

clk_capclk_cap

clk_seqclk_seq

aa

bb

ccddee

ggff

aa

bb

ccddee

ggff

unitsunits

tenstens

sequencersequencer

countercounter

countcount

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ua_gua_g

gogo

da_gda_g

clk_capclk_cap

clk_seqclk_seq

aa

bb

ccddee

ggff

aa

bb

ccddee

ggff

unitsunits

tenstens

sequencersequencer

countercounter

countcount

display latch

display latch

dispdisp

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SequencerSequencergogo

clk_seqclk_seq sequencersequencer

countcount

dispdisp

librarylibrary IEEE; IEEE;

useuse IEEE.std_logic_1164.all; IEEE.std_logic_1164.all;

useuse IEEE.numeric_std.all;IEEE.numeric_std.all;

entityentity sequencer sequencer isis

portport(clk_seq,go: (clk_seq,go: inin std_logic; std_logic;

count,disp: count,disp: outout std_logic; std_logic;

endend sequencer;sequencer;

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Sequencer Sequencer –– abstract statesabstract statesarchitecturearchitecture fsm fsm ofof sequencer sequencer isis

beginbegin

processprocess(clk_seq) (clk_seq)

typetype tetat tetat isis (stop,ecount,edisp); (stop,ecount,edisp);

variablevariable vetat: tetat:= stop; vetat: tetat:= stop;

beginbegin

casecase vetat vetat isis

whenwhen stop => count<=‘1’;disp<=‘0’; vetat:= ecount; stop => count<=‘1’;disp<=‘0’; vetat:= ecount;

whenwhen ecount => count<=‘0’;disp<=‘1’; vetat:= edisp; ecount => count<=‘0’;disp<=‘1’; vetat:= edisp;

whenwhen edispedisp => count<=‘1’;disp<=‘0’; vetat:= ecount; => count<=‘1’;disp<=‘0’; vetat:= ecount;

end caseend case; ;

end processend process; ;

end fsmend fsm;;

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beginbegin




beginbegin





end caseend case; ;


end fsmend fsm;;

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beginbegin

processprocess((clk_seqclk_seq) ) ---- problem: detects problem: detects both edgesboth edges ? ?



beginbegin





end caseend case; ;


end fsmend fsm;;

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beginbegin

processprocess((clk_seqclk_seq) )



beginbegin

ifif rising_edgerising_edge(clk_seq) (clk_seq) then then


……

end caseend case; ;

end ifend if; ;


end fsmend fsm;;

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beginbegin

processprocess((clk_seq, goclk_seq, go) ) ---- we need state control we need state control



beginbegin

ifif rising_edgerising_edge(clk_seq) (clk_seq) then then


……

end caseend case; ;

end ifend if; ;


end fsmend fsm;;

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beginbegin

processprocess((clk_seqclk_seq) ) ---- we need state control we need state control



beginbegin

ifif rising_edge(clk_seq) rising_edge(clk_seq) then then

if if go=0go=0 thenthen vetat:=stop; count<=‘0’;disp<=‘0’; vetat:=stop; count<=‘0’;disp<=‘0’; elseelse


……

end caseend case; ;

end ifend if; ;

end ifend if; ;

end processend process; ; end fsmend fsm;;

go=1go=1

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Sequencer Sequencer –– abstract statesabstract states

go=1go=1

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go=1go=1 rising_edgerising_edge(clk_seq)(clk_seq)

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dispdisp countcount

go=1go=1 rising_edgerising_edge(clk_seq)(clk_seq)

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Sequencer => counter (+)Sequencer => counter (+)architecturearchitecture countcount ofof sequencer sequencer is is

begin begin


typetype tetat tetat is is unsignedunsigned(0 to 1); (0 to 1);

variable variable vetat:tetat:="00"; vetat:tetat:="00";

begin begin

ifif rising_edge(clk_seq) rising_edge(clk_seq) thenthen

if go=‘0’ then vetat :="00"; count<=‘0’;disp<=‘0’; if go=‘0’ then vetat :="00"; count<=‘0’;disp<=‘0’;

elseelse vetat:=vetat+1; vetat:=vetat+1;

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Sequencer => counter (+)Sequencer => counter (+)architecturearchitecture countcount ofof sequencer sequencer is is

begin begin


typetype tetat tetat is is unsignedunsigned(0 to 1); (0 to 1);

variable variable vetat:tetat:="00"; vetat:tetat:="00";

begin begin

ifif rising_edge(clk_seq) rising_edge(clk_seq) thenthen

if go=‘0’ then vetat :="00"; count<=‘0’;disp<=‘0’; if go=‘0’ then vetat :="00"; count<=‘0’;disp<=‘0’;

elseelse vetat:=vetat+1; vetat:=vetat+1;


whenwhen "00" => .. "00" => ..

when otherswhen others => .. => ..

end caseend case;;

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BCD100 counterBCD100 counter

gogo


clk_capclk_cap countercounter

countcount onesones

tenstens

44--bit BCD codesbit BCD codes

countcount

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BCD100 counterBCD100 counter

clk_capclk_cap countercounter

countcount onesones

tenstens

librarylibrary IEEE; IEEE;

use use IEEE.std_logic_1164.all; IEEE.std_logic_1164.all;

useuse IEEE.numeric_std.all;IEEE.numeric_std.all;

entityentity BCDcounter_100 BCDcounter_100 isis

portport(count,clk_cap: (count,clk_cap: inin std_logic; std_logic;

ones,tens: ones,tens: outout unsigned(3 unsigned(3 downtodownto 0)); 0));

endend BCDcounter_100;BCDcounter_100;

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BCD100 counter BCD100 counter -- algorithmalgorithmarchitecturearchitecture algorithm algorithm of of BCDcounter_100 BCDcounter_100 isis

begin begin

processprocess(count,clk_cap) (count,clk_cap)

variablevariable uni,diz: unsigned(3 uni,diz: unsigned(3 downtodownto 0); 0);

begin begin

if if rising_edgerising_edge(count) (count) thenthen

uni:="0000"; diz :=x"0"; uni:="0000"; diz :=x"0";

start and initialisestart and initialise

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BCD100 counter BCD100 counter -- algorithmalgorithmarchitecturearchitecture algorithm algorithm ofof BCDcounter_100 BCDcounter_100 isis

begin begin



begin begin

if if rising_edge(count) rising_edge(count) thenthen

uni:="0000"; diz :=x"0"; uni:="0000"; diz :=x"0";

elsifelsif (count='1' (count='1' andand rising_edgerising_edge(clk_cap)) (clk_cap)) thenthen

counting the impulsescounting the impulses

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begin begin



begin begin


uni:="0000"; diz :=x"0"; uni:="0000"; diz :=x"0";

elsifelsif (count='1' (count='1' andand rising_edge(clk_cap)) rising_edge(clk_cap)) thenthen

ifif (uni=9) (uni=9) thenthen

uni :="0000"; uni :="0000";

ifif(diz=9) (diz=9) thenthen diz :=x"0"; diz :=x"0"; elseelse diz := diz + 1; diz := diz + 1; end ifend if; ;

elseelse uni := uni+1; uni := uni+1; end ifend if; ; end ifend if; ;

ones <= uni; tens <= diz; ones <= uni; tens <= diz;

end processend process; ; end algorithmend algorithm;;

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begin begin



begin begin


uni:="0000"; diz :=x"0"; uni:="0000"; diz :=x"0";

elsifelsif (count='1' (count='1' andand rising_edge(clk_cap)) rising_edge(clk_cap)) thenthen

ifif (uni=9) (uni=9) thenthen

uni :="0000"; uni :="0000";

ifif(diz=9) (diz=9) thenthen diz :=x"0"; diz :=x"0"; elseelse diz := diz + 1; diz := diz + 1; end ifend if; ;

elseelse uni := uni+1; uni := uni+1; end ifend if; ; end ifend if; ;

ones <= uni; tens <= diz; ones <= uni; tens <= diz; ---- output signals output signals


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BCD100 counter BCD100 counter -- algorithmalgorithm

rising_edge(count)rising_edge(count)

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BCD100 counter BCD100 counter -- structurestructure

bcdbcd

coutcout

clkclk

countcount

44--bit BCD codebit BCD code

onesones

BCD BCD

countercounter

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bcdbcd

coutcout

clkclk

countcount


bcdbcd

coutcout

clkclk

countcount


onesones tenstens

BCD BCD

countercounterBCD BCD

countercounter

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bcdbcd

coutcout

clkclk

countcount


bcdbcd

coutcoutcountcount


onesones tenstens

BCD BCD

countercounterBCD BCD

countercounter

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BCD counterBCD counter

entityentity BCDcounter BCDcounter isis

portport(count,clk: (count,clk: inin std_logic; std_logic;

bcd: bcd: outout unsigned(3 unsigned(3 downtodownto 0); 0);

cout: cout: outout std_logic); std_logic);

endend BCDcounter;BCDcounter;

bcdbcd

coutcout

clkclk

countcount

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BCD counter BCD counter -- architecturearchitecture

architecturearchitecture algorithm algorithm of of BCDcounter BCDcounter isis

begin begin

processprocess(count,clk) (count,clk)

variablevariable vbcd: unsigned(3 vbcd: unsigned(3 downtodownto 0); 0);

begin begin

ifif (rising_edge(count)) (rising_edge(count)) thenthen

vbcd :="0000"; vbcd :="0000";

elsifelsif(count='1' (count='1' andand rising_edge(clk)) rising_edge(clk)) thenthen

if if (vbcd=9) (vbcd=9) thenthen vbcd :="0000"; cout <='1'; vbcd :="0000"; cout <='1';

elseelse vbcd := vbcd+1; cout <='0'; vbcd := vbcd+1; cout <='0'; end ifend if; ;

end ifend if; ;

bcd <= vbcd; bcd <= vbcd;


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BCD counter BCD counter -- architecturearchitecture

vbcd :="0000"; cout <='1'vbcd :="0000"; cout <='1'

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architecturearchitecture structural structural ofof BCDcounter_100 BCDcounter_100 is is

componentcomponent BCDcounter BCDcounter isis

portport(count,clk: (count,clk: inin std_logic; std_logic;

bcd: bcd: outout unsigned(3 unsigned(3 downtodownto 0); 0);

cout: cout: outout std_logic); std_logic);

end componentend component; ;

signalsignal carry, carryout: std_logic; carry, carryout: std_logic;

beginbegin

bcd1: BCDcounter bcd1: BCDcounter

port mapport map(count,clk_cap,ones,(count,clk_cap,ones,carrycarry); );

bcd2: BCDcounter bcd2: BCDcounter

port mapport map(count,(count,carrycarry,tens,carryout); ,tens,carryout);

endend structural;structural;

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BCD latch and decoderBCD latch and decoder

segseg

latch & decode

latch & decodedispdisp aa

bb

ccddee

ggff

7 bits7 bits

entityentity latch_decoder latch_decoder isis

portport(disp: (disp: inin std_logic; std_logic;

dcb: dcb: in in unsigned(3 unsigned(3 downtodownto 0); 0);

seg: seg: outout unsigned(6 unsigned(6 downtodownto 0)); 0));

endend latch_decoder;latch_decoder;

dcbdcb

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dispdisp

dcbdcb

segseg

latch & decode

latch & decode

7 bits7 bits

architecturearchitecture algorithm algorithm ofof latch_decoder latch_decoder is is

begin begin

processprocess(disp) (disp)

variablevariable vdcb: integer vdcb: integer rangerange 0 0 toto 9; 9;

begin begin

vdcb := vdcb := to_integerto_integer(dcb); (dcb);

vector to integer conversionvector to integer conversion

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dispdisp

dcbdcb

segseg

latch & decode

latch & decode

7 bits7 bits

architecturearchitecture algorithm algorithm ofof latch_decoder latch_decoder is is

begin begin

processprocess(disp) (disp)

variablevariable vdcb: integer vdcb: integer rangerange 0 0 toto 9; 9;

begin begin

vdcb := to_integer(dcb); vdcb := to_integer(dcb);

ifif rising_edgerising_edge(disp) (disp) thenthen

casecase vdcb vdcb isis ––-- abcdefg abcdefg

whenwhen 0 => seg <= "1111110"; 0 => seg <= "1111110";

whenwhen 1 => seg <= "0000110";1 => seg <= "0000110";

whenwhen 9 => seg <= "1011111"; 9 => seg <= "1011111";

end caseend case; ; end ifend if; ;

end processend process; ; end algorithmend algorithm;;latch decodedlatch decoded

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latchlatch

decoderdecoder

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Frequency meter Frequency meter -- the systemthe system

ua_gua_g

gogo

da_gda_g

clk_capclk_cap


countercounter

scountscount

display latch

display latch

sdispsdisp

component built from two component built from two

components components –– bcdcounter bcdcounter

two components two components

–– latch_decoderlatch_decoder

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architecturearchitecture structural structural ofof frequencemetre frequencemetre is is

componentcomponent sequenceur sequenceur isis

portport(clk_seq,go:in std_logic;count,disp:(clk_seq,go:in std_logic;count,disp:outout std_logic); std_logic);


componentcomponent bcdcounter_100 bcdcounter_100 isis

portport(count,clk_cap: (count,clk_cap: inin std_logic; std_logic;

ones,tens: ones,tens: outout unsigned(3 unsigned(3 downtodownto 0)); 0));


componentcomponent latch_decoder latch_decoder is is

portport(disp: (disp: inin std_logic; dcb: std_logic; dcb: inin unsigned(3 unsigned(3 downtodownto 0); 0);

seg: seg: outout unsigned(6 unsigned(6 downtodownto 0)); 0));

end componentend component;;

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signalsignal scount, sdisp: std_logic; scount, sdisp: std_logic;

signalsignal unites,dizaines: unsigned(3 unites,dizaines: unsigned(3 downtodownto 0); 0);

begin begin

iseqiseq: sequenceur : sequenceur port mapport map(clk_seq,go,con);(clk_seq,go,con);

ua_gua_g

gogo

da_gda_g

clk_capclk_cap


scountscount

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begin begin

iseqiseq: sequenceur : sequenceur port mapport map(clk_seq,go, scount, sdisp); (clk_seq,go, scount, sdisp);

icount100icount100: bcdcounter_100 : bcdcounter_100

port mapport map(scount ,clk_cap,unites,dizaines);(scount ,clk_cap,unites,dizaines);

ua_gua_ggogo

da_gda_g

clk_capclk_cap


countercounter

scountscount

unites unites

dizainesdizaines

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iseqiseq: sequenceur : sequenceur port mapport map(clk_seq,go, scount, sdisp); (clk_seq,go, scount, sdisp);


port mapport map(scount ,clk_cap,unites,dizaines); (scount ,clk_cap,unites,dizaines);

ilatchdec1ilatchdec1: latch_decoder : latch_decoder port mapport map(sdisp ,unites,ua_g); (sdisp ,unites,ua_g);

ilatchdec2ilatchdec2: latch_decoder : latch_decoder port mapport map(sdisp ,dizaines,da_g);(sdisp ,dizaines,da_g);

ua_gua_g

gogo

da_gda_g

clk_capclk_cap


countercounter

scountscount

display latch

display latch

sdispsdisp

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signalsignal scout, sdisp: std_logic; scout, sdisp: std_logic;

signalsignal unites,dizaines: unsigned(3 unites,dizaines: unsigned(3 downtodownto 0); 0);

beginbegin

iseqiseq: sequenceur : sequenceur port mapport map(clk_seq,go, scout, sdisp);(clk_seq,go, scout, sdisp);


port mapport map(scount ,clk_cap,unites,dizaines);(scount ,clk_cap,unites,dizaines);

ilatchdec1ilatchdec1: latch_decoder : latch_decoder port mapport map(sdisp ,unites,ua_g);(sdisp ,unites,ua_g);

ilatchdec2ilatchdec2: latch_decoder : latch_decoder port mapport map(sdisp ,dizaines,da_g);(sdisp ,dizaines,da_g);

endend structural;structural;

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SummarySummary

Case study of frequency meter with different kinds of Case study of frequency meter with different kinds of

circuits (components)circuits (components)

sequential logic componentssequential logic components

combinatory logic componentscombinatory logic components

with functional and structural description styleswith functional and structural description styles

vhdl : case study

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