vhdl basics1

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VHDL BASICS

ByT V S RAM

Email: [email protected]

[email protected]

mailto:[email protected]

mailto:[email protected]



VHDL BASICS

VHDL(VHSIC) It is very high speed integratedcircuit hardware descriptive language.

What for it is used?

Used to model digital system.What are its characterstics?

It is case- in sensitive, means Ram,RAM rAM allequal it VHDL.

-- is used for comments.

language is similar to ADA,

If you know C++ or PASCAL it is easy.



VHDL Basics

what it is ?

It is a hardware description language that can be

used to model a digital system at many levels of abstraction language, ranging from algorithm

level to gate level.



VHDL BASICS

What It has?

It has an amalgamation of

.sequential language.concurrent language

.net-list language

.timing specifications.waveform generation language



VHDL HISTORY

What is its History?

DOD of USA had started in 1981.

They thought that it could act asmedium for information

Exchange between chip foundries andCAD tool operations.

Because of Defence it was keptclassified till 1985.



VHDL HISTORY

Then lot of private industry participatedfor development of this language

In 1985 DOD had granted permission tohand over to spec to IEEE.

IEEE released the number as IEEE

1076 /A. standard in dec 1987.IEEE revised in 1993.



VHDL IS CUNNING

Advantage of this language is

Same language is used for analysis andsynthesis

But, Be careful, some are only simulatableand not synthesisable.

Pl, Note

At the present moment, what can besynthesizable is very vague, and much aretool Dependable.



VHDL IS CUNNING

Still IEEE is worming on a synthesisablesubset of VHDL which will be supplied

by all the Synthesis vendors.



VHDL CAPABILITIES

It is a language, hence it can be used as anexchange medium between chip vendors andCAD tool users.

Means, chip vendors can provide VHDLdescriptions of their components to systemdesigners. CAD tool users can use them tocapture the behavior of the design at a high

level of abstraction for function simulation.

.



VHDL CAPABILITIES

It supports hierarchy,

A Digital system can be modelled as a set of

interconnected components, eachcomponents in turn can be modelled as someof interconnection subcomponents.

Simillar to other languages this also supports

flexible design methrodologies top-downbottom - up or mixed.



VHDL CAPABILITIES

It is a Language hence it can also beused as a common medium between

different CAD and CAE tools. Eg:.Schematic capture program may beused to generate a VHDL descriptionfor the design, which can be used as aninput to a simulation program.

It supports hierarchy,



VHDL CAPABILITIES

A Digital system can be modeled as a set ofinterconnected components, eachcomponents in turn can be modeled as someof interconnection sub-components.

Similar to other languages this also supportsflexible design methodologies top-down

bottom - up or mixed.The language is not technology specific



VHDL CAPABILITIES

but is capable of supporting technologyspecific feature, supports various handwaretechnology. Eg: You may define new logictypes and new components. You can alsomodel technology dependent components.

By being technology independent the same

model can be synthesized in to differentvendor libraries.



VHDL CAPABILITIES

Supports both synchronous andasynchronous timing models.

You can use, FSMs, state tables, algorithm

descriptions, Boolean, wave form entry, etc,Nowadays the new tools like VISUAL HDL

are available using them even flowchart,block level, also can be used as design entry.

It is similar to English language.



VHDL SUPPORTS

.structural,

.data-flow,

.behavior

A combination of all the three alsopossible.

Wide range of abstraction levels fromabstract behavior description to veryprecise gate level.

But, below transistor level not possible.



VHDL SUPPORTS

It has elements, that make large scaledesign modeling easier.

HOW?

Using this you can create

components, functions, procedures,

and packages, test benches,

you can model Propagation delay, Min-max delay, setup and hold time etc.,



VHDL SUPPORTS

One can use generics, and attributeswhich are useful in describing

paramaterised model.



digital systemeg:

micro processor

int lines,

control bus

add bus

data bus

aludevice

entity

external view

acculator

deviceentity

memorydevice

entity

inthandlingdeviceentity

architecutre

2

architecture1

only 1architecture

only 1architecture

architecture2

architecture3

architecture

1



VHDL Terminology

Digital system can be as simple as logic

gate to complex system.

Hardware abstraction of this system calledentity ( component) .

An entity X when used in entity Y becomes

a component for the entity Y.



VHDL Terminology

VHDL provides five different types of

primary constructs, called design units

1. Entity declaration2. Architecture body

3. Configuration Delcaration

4. Package declaration

5. Package body



VHDL Terminology

Entity E1 Entity E2

Entity E3

E3_A1 E3_A2 E3_A3

M1:...

E2_A1 E2_A2

E1_A3E1_A2E1_A1

BX:... CX:...

B I N D

I N G



Once an entity is modeled,it needs to be

analyzed and finally it has to be simulated.

Then we can say a component is created.So Next step is analyzer and simulator

analyzer reads in one or more design units

contained in a single file and compiles theminto a design library after validating syntax

VHDL Analyzer



VHDL Analyzer

and performing some static semantic

checks. This design library is your library,

means your project library.design library is a place in the host

environment where compiled design units

are stored.



VHDL Simulator

The simulator simulates

entity

we know that each “entity” is represented by an “entity-architecture” pair or by a

configuration, by reading in its compiled

description from the design library and thenperforming the following steps.



VHDL Simulator

Elaboration

initialization

simulation



Entity

Entity declaration specifies the name of the

design ( component) being modeled and the

set of interface ports.Ports are signals through which entity

communicates with the other models in its

external environment.



Entity Example

x1

A1

sum

carry

A

B

-- start of entity

entity HALF_ADDER is

-- port declaration starts

port(A,B:inBIT;SUM,CARRY:out BIT);

--port declaration ends

end HALF_ADDER;

--end of entity declaration



VHDL Architecture Body

What does architecture does?

It describes the internal details of an entity.

How it does?

Using any of the following modeling styles:

A set of interconnected components ( to

represent structure)



VHDL Architecture Body

A set of concurrent assignment statements(

to represent dataflow)

A set of sequential assignments ( torepresent behavior)

As any combination of the above three.



VHDL Structural style

Here entity is described as a set of

interconnected component. Example for

Half_adder is



VHDL Structural style example

architecture HA_STRUCTURE of HALF_ADDER is

component xor2

port (in1,in2: in Bit; o1:out BIT);

end component;

component AND2

port (X,Y: in Bit; Z:out BIT);

end component;begin

u1: xor2 portmap(HAPPY1,HAPPY2,ALLHAPPY);

U2: and2 portmap ( sad1,sad2,allsad);

end HA_Structure;




HA_STRUCTURE is the name of the architecture.

HALF_ADDER is an entity

BEGIN and END are key words used to say start

and end of the architecture.

The two components xor2,and2 are declared in the

declarative part of the architecture body.

Between Begin and End is the statement part.




Where these xor2, and and2 exists?

They may be predefined components in a

library or, if they do not exist, they maylater be bound to other components in alibrary.

The declared components are instantiated in

the statement part of the architecture bodyusing component instantiation statements.




U1, u2 are components labels for the

components.

Signals in the port map of a componentinstantiation and the port signals in the port

map of a component instantiation and the

port signals in the component declarationare associated by position (called positional

association.




The structural representation for the

HALF_ADDER does not say anything

about its functionality. Separate entitymodels would be described for the

compoenents xor2 and and2, each having its

own entity declaration and architecture

body.



VHDL Data Flow style

Here the flow of data through the entity is

expressed primarily using concurrent signal

assignment statements. The structure of theentity is not explicitly specified in this

modeling style, but it can be implicitly

deduced. Look at this example.




architecture HA_CONCURRENT of

HALF_ADDER is

beginsum <= A xor B after 8 ns;-- concurrent stat

Carry <= A and B after 4 ns ;-- concurrent

stat end HA_CONCURRENT;




The data flow model for the HALF_ADDER is

described using two concurrent signal assignment

statements.

In a signal assignment statement, the symbol <=

implies an assignment of a value to a signal. The

value of the expression on the right hand side of

the statement is computed and is assigned to thesignal on the left hand side, called target signal.




Remember, a concurrent signal assignment

statement is executed only when any signal used

in the expression on the right hand side has an

event on it that is, the value for the signal changes.

Concurrent signal assignment statements are

concurrent statements, the ordering of these

statements in an architecture body is not important




“After” clauses needed to incorporate the delay.

Here both signal assignments statements execute

concurrently.

Means, here we have two signals

Signal A or B, which are input port signals of our

Half_Adder, It has an event, say at time T,




the right hand side expressions of both

signal assignment statements are evaluated

Signal SUM is scheduled to get the newvalue after 8 ns.

while signal CARRY is scheduled to get the

new value after 4 ns. CARRY will get its

new value,and when simulation time

advances to (T+8)ns, SUM will get its new

value.




The after clause may be used to generate a

clock signal

clk <= not CLK after 10ns;this statement creates a periodic waveform

on the signal CLK with a time period of 20

ns,

CLK

10 20 30 40 50 60 70



VHDL Behavioral style

This modeling is in contrast to earlier

modelings.

The behavioral style modeling specifies thebehavior of an entity as a set of statements

that are executed sequentially in the

specified order. This set of sequential

statements, which are specified inside a

process statement, do not explicitly specify




A process statement also has a declarative part(before keyword begin) and statement part (between the keyword begin and end process). Thestatements appearing within the statement part aresequential statements and are executedsequentially. The list of signals specified withinthe parentheses after the keyword processconstitutes a sensitivity list, and the process

statement is invoked whenever there is an event onany




signal in this list. In the previous example when

an event occurs on signals A, B, or Enable, the

statements appearing within the process statement

are executed sequentially.

Variables declared in the processes have their

scope limited to that process. Variables can also

be declared in sub programs. It is possible to use case or loop statements within

a process.



VHDL process

We can use case, loop etc within process.

Normally they are similar as C or pascal.

An explicit wait statement can also be usedto suspend a process. It can be used to wait

for a certain amount of time, until a certain

condition becomes true, or until an event

occurs on one or more signals.



Eg: process

begin

clk <= „0‟;wait for 20 ns;

clk <= „1‟;wait for 12 ns;

end process;

0 20 32 52 64 84 96

clk



VHDL process

This process does not sensitivity list pl. observe

the code.

Because explicit wait statements are present inside

the process. It is important to remember that a

process never terminates. It is always either being

executed or in suspended state. All processes are

executed once during the initialization phase of simulation until they get suspended.



VHDL process

A process with no sensitivity list and no

explicit wait statement will never suspend

itself.Eg: of DFF.

Entity DFF IS

Port (Q:out BIT; D,clk: in BIT);End DFF;



VHDL process

Architecture DFF_beh of DFF is

Begin

Process ( D,clk)

Begin

If clk = '1' then

Q <= D;

End if; End process;

End Dff_beh;



VHDL process

This process executes whever there is an even

on signal D or CLK. If the value of CLK is '1' ,

the value of D is assigned to Q. If CLK is '0',then no assignment to Q takes place. Thus, as

long as CLK is '1' any change on D will appear

on Q. Once clk becomes '0', the value in Q is

retained.



VHDL Mixed style modeling

Within architecture All three can be mixed.

Ie.,

we can use component instantiation(structure)

concurrent signal assignments(dataflow)

process statements ( behavior).



VHDL FULL ADDER MIXEDEntity FA isPort ( a,b,cin:in bit; sum,cout:out bit);End FAArchitecture FA_mixed of FA isComponent xor2

Port(p1,p2:in bit; pz :out BIT);End component;Signal s1:bit;

BeginX1:xor2 portmap (A,B,S1); -- - structureProcess ( A,B,CIN) -- - behavior Variable t1,t2,t3:bit;Begin

T1 := A and B;T2 := B and cin;T3 := a and cin;

Cout <= t1 or t2 or t3;End process;Sum <= s1 xor cin; -- -- dataflowEnd FA;



EXAMPLE FOR MIXED

MODELINGx1

A

B

x1CIN

SUM

BEHAVIOR

CARRY

This FA is done with one component instantiation

one process statement ,

one concurrent signal assignment.Note all these statements are concurrent statements.

Therefore their order of appearance within the architecture

body is not important.



This is done using one component instantiation

one process statement and ond concurrent

signal assignment. Note all these statementsare concurrent statements. Therefore their order

of appearance within the architecture body is not

important.



VHDL configuration

declaration

As discussed earlier, an entity can consists

of any no of architectures but, while

compilation only one architecture should bethere. This can be dictated by configuration

file .

So, a configuration is used to select one of

the possiblly many architecture bodies that

an entity may, have, and to bind coponents,



VHDL configuration

declaration

Used to represent structure in that architecture

body, to entities represented by an entity-

architecture pair or by a configuration which

reside in a design library,

eg:



VHDL configuration

declarationLibrary cmos_lib,my_lib; -- - library clause both library visible in configurationConfiguration Ha_binding of half_adder is - -configuration name Ha_binding and specifies

For ha_structure -- specifies that the architecture body it has two components-- threfore two configuration. X1 repesents entity architecture pair,

For x1:xor2 -- - xor gate and dataflow architecture which resides com_lib-- - design library.

Use entity cmos_lib.xor_gate(dataflow);End for;For A1:and2 -- similarly for and2 also.

Use configuration My_lib,and_config;End for;

End for;

End Ha_binding;



Package declaration

A package declaration is used to store a set of commondeclarations such as components,types, procedures, andfunctions. These declarations can then be imported into other design units using a "use" clause.

Package ex_traffic_light is ---- name of package it has type,component, function

see that int2bit_Vec does not appear in thepackage

-- only interface appears,Type color is (red,green,yello);

Component D_myFFPort (D,CK: in bit; Q :out BIT); End component;

Constant pin2pin_delay :time := 125ns;Function int2bit_vec ( int_value:integer)

Return bit_vector;

End ex_traffic_light;



Package declaration

Used to store the definitions of functions and procedures thatwere declared in the corresponding package declaration, andalso the complete constant declarations for any declarationsof any deferred constants that appear in the packagedeclaration.Package body is always associated with package declaration.Package declaration can have at most one package bodyassociated with it. Contrast this with an architecture body andan entity declaration, where multiple architecture bodies maybe associated wit a single entity declaration



Package declaration

Package body exam_pack is - - name of the package is same aspackage declarations

Function int2bit_vec ( int_value:integer)Return bit_vector is

Begin - -behavior of function described here.

End int2bit_vec;End exam_pack;

THANK YOU ALL



THANK YOU ALL

SIRS You Need Not Read Heavy Books

Just refer them

Just Practice,

It makes you Perfect

Wish you

all the Best.

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