Chapter-1 Introduction

1.1 IntroductionVGA stands for Video Graphics Array, Video Graphics Array (VGA) refers specifically

to the display hardware first introduced with the IBM PS/2 line of computers in 1987.

In this design we consider a basic 8 colour display of 640 by 480 resolution using CRT

(cathode ray tube) interface.

1.2 CRT workingFollowing figure shows basic diagram of monochrome CRT

FIG 1. CATHODE RAY TUBE In CRT these are deflection coils which make the electron beam to move in vertical and

horizontal direction. In this project by VHDL we have to design this vertical and

horizontal counters to control the direction of electron beam and mafe it on – of when we

want to display. Image on next page shows how an electron beam scans full screen to

display objects.

1

1.3 Display of objects on CRT Screen

FIG.2 ELECTRON BEAM MOVEMENT

The monitor's internal oscillators and amplifiers generate sawtooth waveforms to control the

two deflection coils. For example, the electron beam moves from the left edge to the right

edge as the voltage applied to the horizontal deflection coil gradually increases. After

reaching the right edge, the beam returns rapidly to the left edge (i.e., retraces) when the

voltage changes to 0. Two external synchronization signals, hsync and vsync, control

generation of the sawtooth waveforms. These signals are digital signals.

The basic operation of a colour CRT is similar except that it has three electron beams, which

are projected to the red, green, and blue phosphor dots on the screen. The three dots are

combined to form a pixel. We can adjust the voltage levels of the three video input signals to

obtain the desired pixel colour

TABLE 1 bit vga colour combination

REG GREEN BLUE COLOUR

0 0 0 BLACK

0 0 1 BLUE

0 1 0 GREEN

2

0 1 1 CYAN

1 0 0 RED

1 0 1 MEGANTA

1 1 0 YALLOW

1 1 1 WHITE

.

This scanning of electron beam is done upto 30 or 60 times in a second to make display in a

continuous manner

1.4 Applications of VGA

Vga is most important component of desktop monitors, simple T.Vs and other displays.

These can be used to from static to moving objects.

1.5 Objective of the Project

Main objective of the project is as:

1. To understand the working of vga

2. To design and implement a simple VGA in VHDL and to observe its output on

minitor using Spartan 3 FPGA kit.

3. To enhance design skills in vhdl.

1.6 Organization of project work

Chapter 2 discusses a brief about a internal description of vga, FPGA and tools used. In

chapter 3 we ll show the present work , its simulations and RTLs, giving detailed description

of our work. Then Chapter 4 discusses the Conclusions and future scope of this project.

3

Chapter-2 Literature Review

Basic schematic for vga controller is as in figure.

FIG 3. SIMPLE BLOCK DIAGRM OF VGA

Here the work of synchronization circuit is to direct the electron beam to a particular position

on the screen. The pixel generation circuit decides at which pixel we have to display data and

this cumulative data goes to the input of vga port.

2.1 VGA synchronization

The video synchronization circuit generates the hsync signal, which specifies the required

Time to traverse (scan) a row, and the vsync signal, which specifies the required time to

traverse (scan) the entire screen. Subsequent discussions are based on a 640-by-480 VGA

screen with a 25-MHz pixel rate, which means that 25M pixels are processed in a second.

Note that this resolution is also known as the VGA mode.

The screen of a CRT monitor usually includes a small black border. The middle rectangle is

the visible portion. Note that the coordinate of the vertical axis increases downward. The

coordinates of the top-left and bottom-right corners are (0,0) and (639,479), respectively

4

2.1.2 Horizontal Synchronization

.

Fig.4- HORIZONTAL SYNCHRONIZATION SOURCE: FPGA PROTOTYPING

BY VHDL EXAMPLES

Xilinx SpartanTM-3 Version

Pong P. Chu

Cleveland State University

In the above figure

5

1. Display: region where the pixels are actually displayed on the screen. The length of

this region is 640 pixels.

2. Retrace: region in which the electron beams return to the left edge. The video signal

should be disabled (i.e., black), and the length of this region is 96 pixels.

3. Right border: region that forms the right border of the display region. It is also know

as the front porch (i.e., porch before retrace). The video signal should be disabled, and

the length of this region is 16 pixels.

4. Left border: region that forms the left border of the display region. It is also know as

the backporch (i.e., porch after retrace). The video signal should be disabled, and the

length of this region is 48 pixels.

The hsync signal can be obtained by a special mod-800 counter and a decoding circuit.. We

intentionally start the counting from the beginning of the display region. This allows us to use

the counter output as the horizontal (x-axis) coordinate. This output constitutes the pixel-x

signal. The hsync signal goes low when the counter’s output is between 656 and 751.

2.1.2 Vertical synchronization

During the vertical scan, the electron beams move gradually from top to bottom and then

return to the top. This corresponds to the time required to refresh the entire screen. The

format of the vsync signal is similar to that of the hsync signal, as shown in Figure 12.5. The

time unit of the movement is represented in terms of horizontal scan lines. A period of the

vsync signal is 525 lines and can be divided into four regions:

1. Display: region where the horizontal lines are actually displayed on the screen. The

length of this region is 480 lines.

2. Retrace: region that the electron beams return to the top of the screen. The video

signal should be disabled, and the length of this region is 2 lines.

3. Bottom border: region that forms the bottom border of the display region. It is also

know as the frontporch (i.e., porch before retrace). The video signal should be disabled, and

the length of this region is 10 lines.

4. Top border: region that forms the top border of the display region. It is also know as

the backporch (i,e, porch after retrace). The video signal should be disabled, and the length

of this region is 33 lines.

6

2.1.3 Timing calculation of VGA synchronization signals

As mentioned earlier, we assume that the pixel rate is 25 MHz. It is determined by three

parameters:

1. p: the number of pixels in a horizontal scan line. For 640-by-480 resolution, it is

pixels line

p = 800 pixels

2. l: the number of lines in a screen (i.e., a vertical scan). For 640-by-480 resolution, it

is lines

1 = 525 -lines

3. s: the number of screens per second. For flickering-free operation, we can set it to 60

screens per second.

Therefore pixels processed per second are:

p*l*s = 800*525*60 = 25M

Therefore 25000 pixels are processed per second.

2.1.4 Character display

The pixel generation circuit generates the 3-bit rgb signal for the VGA port. The external

control and data signals specify the content of the screen, and the pixel-x and pixel-y signals

from the vga-sync circuit provide the current coordinates of the pixel. For our discussion

purposes, we divided this circuit into three broad categories:

1. Bit-mapped scheme

2. Tile-mapped scheme

3. Object-mapped scheme

Our interest is in tile mapped scheme, in which characters are displayed in form of tiles of

16*8 matrixes.

Characters in required form of matrix are stored in form of block ROM and its required

characters are selected via pixel generation circuit.

7

In our project we are implementing a small 16 character memory, which are displayrd on

the screen.

In our design x(2) to x(0) are used to select column of tile and row is selected by

decoding y- pixel.

2.1.5 Character generation

Characters are generated in form of 8*16 matrix tile16 columns are denoted by y pixels

and 8 columns by x pixels. Following figure shows how tile memory is accessed

Fig. Generation of character A

In similar fashion all characters can be generated.

The character patterns are stored in a ROM and each pattern requires 24 * 8 bits. The

pattern memory is known as font ROM. The original font set consists of 256 patterns,

including digits, upper- and lowercase letters, punctuation symbols, and many special-

8

purpose graphic symbols. To implement only the first half [i.e., 128 characters] 2^(7 *

24 * 8) ROM bits are needed. It is usually configured as a 2^(11-by-8) ROM.

2.2 Tools used

Main tools used in this project are:

1. Xilinx ise software packages

2. Model Sim as Simulator

3. Spartan-3 fga kit

Xilinx 9.2 is freely available on Xilinx website and can be downloaded from there.

This tool compiles the vhdl code and verifies it. It also helps in implementation of circuit by

generating bit stream to be burnt on the fpga. It also creates RTL of the circuit giving the road

view of the circuit. It generates necessary files to be burnt on the fpga.

It also comes with integrated simulator to verify code simulations.

Model Sim is students version simulator freely available on “mentor graphics” website. It

gives output in form of continuous clock and inputscan be forced to change their value in run

time environment.

Spartan-3 is fpga kit, which has on it provisions of

1. Fast , asynchronous SRAM

2. 4-digit , seven segment led display

3. Switches and leds

4. VGA port

5. PS/2 Mouse and keyboard port.

6. RS-232 port

7. JTAG programming and debugging ports

This makes it suitable for vast kind of operations and testing of FPGAS

2.3 About FPGAS

9

FPGAs are programmable semiconductor devices that are based around a matrix of

Configurable Logic Blocks (CLBs) connected through programmable interconnects. As

opposed to Application Specific Integrated Circuits (ASICs), where the device is custom built

for the particular design, FPGAs can be programmed to the desired application or

functionality requirements. Although One-Time Programmable (OTP) FPGAs are available,

the dominant type is SRAM-based which can be reprogrammed as the design evolves.

FPGAs allow designers to change their designs very late in the design cycle– even after the

end product has been manufactured and deployed in the field. In addition, FPGAs allow for

field upgrades to be completed remotely, eliminating the costs associated with re-designing

or manually updating electronic systems.

FPGA Applications

Due to their programmable nature, FPGAs are an ideal fit for many different markets.

Aerospace & Defense - Radiation-tolerant FPGAs along with intellectual property for

image processing, waveform generation, and partial reconfiguration for SDRs.

ASIC Prototyping - ASIC prototyping with FPGAs enables fast and accurate SoC

system modeling and verification of embedded software

Audio - Xilinx FPGAs and targeted design platforms enable higher degrees of

flexibility, faster time-to-market, and lower overall non-recurring engineering costs

(NRE) for a wide range of audio, communications, and multimedia applications.

Automotive - Automotive silicon and IP solutions for gateway and driver assistance

systems, comfort, convenience, and in-vehicle infotainment. - Learn how Xilinx

FPGA's enable Automotive Systems

Broadcast - Adapt to changing requirements faster and lengthen product life cycles

with Broadcast Targeted Design Platforms and solutions for high-end professional

broadcast systems.

Consumer Electronics - Cost-effective solutions enabling next generation, full-

featured consumer applications, such as converged handsets, digital flat panel

displays, information appliances, home networking, and residential set top boxes.

10

Data Center - Designed for high-bandwidth, low-latency servers, networking, and

storage applications to bring higher value into cloud deployments.

High Performance Computing and Data Storage - Solutions for Network Attached

Storage (NAS), Storage Area Network (SAN), servers, and storage appliances.

Industrial - Xilinx FPGAs and targeted design platforms for Industrial, Scientific and

Medical (ISM) enable higher degrees of flexibility, faster time-to-market, and lower

overall non-recurring engineering costs (NRE) for a wide range of applications such

as industrial imaging and surveillance, industrial automation, and medical imaging

equipment.

Medical - For diagnostic, monitoring, and therapy applications, the Virtex FPGA and

Spartan® FPGA families can be used to meet a range of processing, display, and I/O

interface requirements.

Security - Xilinx offers solutions that meet the evolving needs of security

applications, from access control to surveillance and safety systems.

Video & Image Processing - Xilinx FPGAs and targeted design platforms enable

higher degrees of flexibility, faster time-to-market, and lower overall non-recurring

engineering costs (NRE) for a wide range of video and imaging applications.

Wired Communications - End-to-end solutions for the Reprogrammable Networking

Linecard Packet Processing, Framer/MAC, serial backplanes, and more

Wireless Communications - RF, base band, connectivity, transport and networking

solutions for wireless equipment, addressing standards such as WCDMA, HSDPA,

WiMAX and others

11

Chapter-3 Present work

At present complete code for vga synchronization has been complete, font rom is

complete and and a test circuit is prepared to check it on fpga kit

3.1. Synchronization circuit

Rtl of Synchronization circuit

Fig 5. Overview of synchronization circuit

This figure gives various input and output connections of synchronizations circuit which

generates outputs for current coordinate of pixel x and pixel y, and other necessary signals,

necessary to display video on screen Here we are generating two circuits one for horizontal

scan and other for vertical scan. The internal diagram gives complete overview.

12

Fig.6 Internal diagram of synchronization circuit

13

Simulation of synchronization circuit is as:

Fig7. Simulations of synchronization circuit

These simulations shows synchronization signals that are uses to run vga screen

3.2. Pixel generation circuit

To display data on screen we simply make the colour bit on where we want to display data on

the screen. This circuit decodes pixel x and pixel y and decides where to display data or not.

Here decision is taken with help of font Rom

Font Rom RTL is as on next page. This rom gives output data in form of 8 bit data, which is

placed on consecutive 8 pixels in line x i.e horizontal axis.

14

Fig8. Font rom circuit diagram

Next is pixel generation circuit representation

Fig9 Pixel generation circuit overview

15

Fig.10. Internal of pixel generation circuit

3.3 Text generation circuit

This circuit generates final text to be displayed on the screen. All the component ie pixel

generation circuit, synchronization circuit are joined together structurally to generate final

circuit and necessary signals are generated. In the simulations show how rbg signal changes

when necessary x and x coordinates are there.

The RTL on the next page shows various inter connections between various circuit

components which as per design generates necessary signals. This was the required block

diagram.

16

Fig.11 RTL of final vga circuit

17

Fig.12 Necessary simulations of text generation circuit showing chande in values of rbg when

required x and y pixels are there on the screen.

3.4 Bit file generation

All this work is done via Xilinx software and model sim simulator.After generating bit file

we can burn it on fpga using an usb to rs232 port. And can verify output.

But unfortunately we were not able to generate bit file because of certain mapping and

routing problems, which we were unable to resolve, and can’t implement the last step. His

may be due to inefficient programming skills.

18

19

Chapter-4 Future Scope and Conclusions

After completing the project to present stage we conclude that being strictly typed language

and hard rules of implementation good practice is needed to do higher level programming and

implementation in vhdl. This makes persons skilled in vhdl and digital system design quiet

valuable to industry.

Regarding our project

By further consultation with experts will remove these problems and can test it on fpga kit.

Warnings and information being displayed on screen are on last page.

Regarding further modification in project,if successfully implemented we can:

1. By introducing animation we can design certain simple games like pong game,

Snakes,etc.

2. Code can be written to interface keyboard, mouse and vga screen.

On Fpga kits various designs of transmitters, receivers, etc can be done.

Apart from this power analysis and timing analysis of vhdl codes on fpga kits make quiet

useful for testing and analysis.

20

References:

1. FPGA PROTOTYPING, BY VHDL EXAMPLES Xilinx SpartanTM-3 Version

Pong P. Chu Cleveland State University, ch.12 and ch.13

2. Xilinx Spartan 3 user guide

3. http://www.xilinx.com/training/fpga/fpga-field-programmable-gate-array.htm

Tools are available on

1. http://www.mentor.com/company/higher_ed/modelsim-student-edition

2. http://www.xilinx.com/support/download/index.html/content/xilinx/en/

downloadNav/design-tools.html

21

APPENDIX-1

COMPLETE CODE LISTING

1. FOR TEST CIRCUIT

entity test is Port ( clk,reset : in STD_LOGIC; h_sync,v_sync : out STD_LOGIC; rgb : out STD_LOGIC_VECTOR (02 downto 0));end test;

architecture Behavioral of test iscomponent vga_sync is Port ( clk : in STD_LOGIC; reset : in STD_LOGIC; x,y : out STD_LOGIC_VECTOR (09 downto 0);

h_sync,v_sync,video_on : out std_logic);end component;component ch_gen is Port ( clk : in STD_LOGIC; video_on : in STD_LOGIC; p_x, p_y : in STD_LOGIC_VECTOR (09 downto 0); rgb : out STD_LOGIC_VECTOR (02 downto 0));end component;signal pixel_x,pixel_y: std_logic_vector(9 downto 0) ;signal video_on: std_logic ;signal rgb_reg : std_logic_vector(2 downto 0):="000" ;

beginsync:vga_sync port map(clk=>clk,reset=>reset,x=>pixel_x,y=>pixel_y,h_sync=>h_sync,v_sync=>v_sync,video_on=>video_on);font:ch_gen port map(clk,video_on,pixel_x,pixel_y,rgb_reg);process(clk)beginif (clk' event and clk='1')then rgb<=rgb_reg;end if;end process; end Behavioral;

2. For synchronization circuit

entity vga_sync is Port ( clk,reset : in STD_LOGIC; x,y: out STD_LOGIC_vector(9 downto 0);

video_on,h_sync,v_sync: out std_logic); end vga_sync;architecture counter of vga_sync issignal mod2,mod2_next,p_tick,h_end : std_logic ;

22

signal count,count_next,count1,count1_next: integer range 0 to 999;beginprocess(clk,reset)beginif(reset='1') thenmod2<='0';count<=0;count1<=0;elsif(clk' event and clk='1') then mod2<=mod2_next;count<=count_next;count1<=count1_next;end if;end process;process(mod2)beginmod2_next<=mod2;p_tick<='0';if(mod2='1') thenmod2_next<='0';p_tick<='1';elsemod2_next<='1';p_tick<='0';end if;end process;-- mod 800process(count,p_tick)begincount_next<=count;if(p_tick='1') thenif(count=799) thencount_next<=0;h_end<='1';else count_next<=count+1;h_end<='0';end if;end if;end process;-- mod-525process(p_tick,h_end,count1)begincount1_next<=count1;if(p_tick='1' and h_end='1') thenif(count1=524) thencount1_next<=0;elsecount1_next<=count1+1;end if;end if;end process;x <= conv_std_logic_vector(count,10); y <= conv_std_logic_vector(count1,10); h_sync<='1' when(count>=656) and (count<=751)

23

else '0';v_sync<='1' when(count1>=490) and (count1<=491) else '0';

video_on<='1' when(count<640) and (count1<480) else '0'; end counter;

3. For character generation circuit

entity ch_gen is Port ( clk : in STD_LOGIC; video_on : in STD_LOGIC; p_x, p_y : in STD_LOGIC_VECTOR (09 downto 0); rgb : out STD_LOGIC_VECTOR (02 downto 0));end ch_gen;

architecture char_gen of ch_gen iscomponent font_rom isport (clk : in std_logic;addr : in std_logic_vector(7 downto 0);data : out std_logic_vector(7 downto 0));end COMPONENT;component mux8_1 is Port ( s : in STD_LOGIC_VECTOR (02 downto 0); x : in STD_LOGIC_VECTOR (07 downto 0); y : out STD_LOGIC);end component;signal rom_addr :std_logic_vector(7 downto 0);signal char_addr :std_logic_vector(3 downto 0);signal row_addr :std_logic_vector(3 downto 0);signal bit_addr :std_logic_vector(2 downto 0);signal font_word :std_logic_vector(7 downto 0);signal font_bit,text_on :std_logic ;beginfont_unit: font_rom port map(clk=>clk, addr=>rom_addr , data=>font_word);char_addr<= p_y(5 downto 4) & p_x(4 downto 3);rom_addr<= char_addr & row_addr;row_addr<= p_y(3 downto 0);bit_addr<= p_x(2 downto 0);m1:mux8_1 port map(bit_addr,font_word,font_bit);

text_on<= font_bit when p_x(9 downto 5)="01001" and

p_y(9 downto 6)="0111" else '0';

process(video_on, font_bit, text_on)beginif(video_on='0') thenrgb<="000";

24

elseif (text_on = '1') thenrgb<="010";elsergb<="000";end if;end if;end process;end char_gen;

4. Font rom file

entity font_rom isport (clk : in std_logic;addr : in std_logic_vector(7 downto 0);data : out std_logic_vector(7 downto 0));end font_rom;

architecture arch of font_rom issignal addr_reg : integer range 0 to 255;type rom_type is array (0 to 255) of std_logic_vector(7 downto 0);constant rom: rom_type:=( --zero - 0 h

"00000000", -- 0 "00000000", -- 1 "01111100", -- 2 ***** "11000110", -- 3 ** ** "11000110", -- 4 ** ** "11001110", -- 5 ** *** "11011110", -- 6 ** **** "11110110", -- 7 **** ** "11100110", -- 8 *** ** "11000110", -- 9 ** ** "11000110", -- a ** ** "01111100", -- b ***** "00000000", -- c "00000000", -- d "00000000", -- e "00000000", -- f-- one - 1 h "00000000", -- 10 "00000000", -- 11 "00011000", -- 12 "00111000", -- 13 "01111000", -- 14 ** "00011000", -- 15 *** "00011000", -- 16 **** "00011000", -- 17 ** "00011000", -- 18 ** "00011000", -- 19 ** "00011000", -- 1a **

25

"01111110", -- 1b ** "00000000", -- 1c ** "00000000", -- 1d ****** "00000000", -- 1e "00000000", -- 1f-- two - 2h "00000000", -- 20 "00000000", -- 21 "01111100", -- 22 ***** "11000110", -- 23 ** ** "00000110", -- 24 ** "00001100", -- 25 ** "00011000", -- 26 ** "00110000", -- 27 ** "01100000", -- 28 ** "11000000", -- 29 ** "11000110", -- 2a ** ** "11111110", -- 2b ******* "00000000", -- 2c "00000000", -- 2d "00000000", -- 2e "00000000", -- 2f

---------------------------------------------------------------- c - E h "00000000", -- e0 "00000000", -- e1 "00111100", -- e2 **** "01100110", -- e3 ** ** "11000010", -- e4 ** * "11000000", -- e5 ** "11000000", -- e6 ** "11000000", -- e7 ** "11000000", -- e8 ** "11000010", -- e9 ** * "01100110", -- ea ** ** "00111100", -- eb **** "00000000", -- ec "00000000", -- ed "00000000", -- ee "00000000", -- ef

-- blank - F h"00000000", -- f0

"00000000", -- f1 "00000000", -- f2 "00000000", -- f3 "00000000", -- f4 "00000000", -- f5 "00000000", -- f6 "00000000", -- f7 "00000000", -- f8 "00000000", -- f9 "00000000", -- fa "00000000", -- fb

26

"00000000", -- fc "00000000", -- fd "00000000", -- fe "00000000" -- ff); beginprocess(clk)begin if(clk' event and clk= '1') then

addr_reg <= conv_integer(unsigned(addr)) ;end if;end process;data <= rom(addr_reg);

end arch;

5. Mux circuitentity mux8_1 is Port ( s : in STD_LOGIC_VECTOR (02 downto 0); x : in STD_LOGIC_VECTOR (07 downto 0); y : out STD_LOGIC);end mux8_1;

architecture Behavioral of mux8_1 is

beginprocess(s,x)beginif (s="111") theny<=x(0); elsif(s="110") theny<=x(1);elsif(s="101") theny<=x(2);elsif(s="100") theny<=x(3);elsif(s="011") theny<=x(4);elsif(s="010") theny<=x(5);elsif(s="001") theny<=x(6);elsif(s="000") theny<=x(7);end if;end process;end Behavioral;

27