very large scale integration ii - vlsi ii synthesis using rtl compiler hayri u ğur uyanik
DESCRIPTION
Very Large Scale Integration II - VLSI II Synthesis Using RTL Compiler Hayri U ğur UYANIK ITU VLSI Laboratories Istanbul Technical University. Synthesis Using RTL Compiler. CNT_16 Module: 16 bit up counter with asynchronous active-low reset `timescale 1ns/1ps - PowerPoint PPT PresentationTRANSCRIPT
04/19/23
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www.vlsi.itu.edu.tr
Very Large Scale Integration II - VLSI II
Synthesis Using RTL Compiler
Hayri Uğur UYANIK
ITU VLSI Laboratories
Istanbul Technical University
04/19/23
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www.vlsi.itu.edu.tr
Synthesis Using RTL CompilerCNT_16 Module: 16 bit up counter with asynchronous active-low reset
`timescale 1ns/1ps
module CNT_16(CLK, RSTB, OUT);
input CLK, RSTB;output [15:0] OUT;
reg [15:0] OUT;
always@(posedge CLK or negedge RSTB) beginif(!RSTB) begin
OUT <= 0;endelse begin
OUT <= OUT + 1;end
end
endmodule
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Synthesis Using RTL CompilerCMP_16 Module: Comparator which compares the 16 bit input with 50.
`timescale 1ns/1ps
module CMP_16(IN, OUT);
input [15:0] IN;output OUT;
reg OUT;
always@(IN) beginif(IN <= 50) begin
OUT = 0;endelse begin
OUT = 1;end
end
endmodule
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Synthesis Using RTL CompilerTOP Module: The top module which connects both. The resulting design makes OUT=1 after 50 clock cycles.
`timescale 1ns/1ps
module TOP(CLK, RSTB, OUT);
input CLK, RSTB;output OUT;
wire [15:0] OUT_16;
CMP_16 U1(OUT_16, OUT);CNT_16 U2(CLK, RSTB, OUT_16);
endmodule
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Synthesis Using RTL Compiler
Make a new folder
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Synthesis Using RTL Compiler
Copy all Verilog files to newly created folder
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Synthesis Using RTL Compiler
rc –gui
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Synthesis Using RTL Compiler
RTL Compiler windows
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Synthesis Using RTL Compiler
set_attribute lib_search_path /work/kits/ams/3.70/liberty/c35_3.3V
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Synthesis Using RTL Compiler
set_attribute library {c35_CORELIB.lib}
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Synthesis Using RTL Compiler
read_hdl CNT_16.v
read_hdl CMP_16.v
read_hdl TOP.v
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Synthesis Using RTL Compiler
elaborate TOP
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Synthesis Using RTL Compiler
Sub Blocks
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Synthesis Using RTL Compiler
Technology independent D type Flip Flop
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Synthesis Using RTL Compiler
Technology independent adder
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Synthesis Using RTL Compiler
define_clock -period 100000 -fall 80 -rise 80 -name clkin /designs/TOP/ports_in/CLK
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Synthesis Using RTL Compiler
set_attribute slew {100 100 200 200} [find -clock clkin]
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Synthesis Using RTL Compiler
external_delay -input 1000 -clock [find -clock clkin] -edge_rise [find /des* -port ports_in/*]
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Synthesis Using RTL Compiler
external_delay -output 1000 -clock [find -clock clkin] –edge_rise /designs/TOP/ports_out/*
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Synthesis Using RTL Compiler
synthesize -to_mapped
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Synthesis Using RTL Compiler
Technology dependent D type Flip Flop
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Synthesis Using RTL Compiler
Technology dependent adder
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Synthesis Using RTL Compiler
write –mapped > TOP_syn.v
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Synthesis Using RTL Compiler
write_sdc > TOP.sdc
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Synthesis Using RTL Compiler
report_timing >timing_report.txt
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Synthesis Using RTL Compiler
report_area >area_report.txt
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Synthesis Using RTL Compiler
bgx_shell
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Synthesis Using RTL Compiler
BuildGates
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Synthesis Using RTL Compiler
source /work/kits/ams/3.70/buildgates/c35_3.3V/read_libs.tcl
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Synthesis Using RTL Compiler
read_verilog -st TOP_syn.v
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Synthesis Using RTL Compilerwrite_sdf -prec 3 -edges check_edge -splitsetuphold -splitrecrem -remashold -force_calculation TOP.sdf
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Synthesis Using RTL CompilerNew Testbench:
`timescale 1ns/1ps`include "/work/kits/ams/3.70/verilog/c35b4/c35_CORELIB.v"`include "/work/kits/ams/3.70/verilog/udp.v“module TEST_TOP;
reg CLK, RSTB;wire OUT;
initial $sdf_annotate("TOP.sdf",U1);initial begin
RSTB = 0;CLK = 0;#30 RSTB = 1;#100000 $finish;
end
always #50 CLK = ~CLK;
TOP U1(CLK, RSTB, OUT);
endmodule
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Synthesis Using RTL Compiler
Add
`timescale 1ns/1ps
to TOP_syn.v and simulate
OUT rises 1.225ns after the rising edge of CLK