verilog module new

8/13/2019 Verilog Module New

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Jim Duckworth, WPI Verilog Module1

Verilog

Verilog for Synthesis


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Verilog background


1983: Gateway Design Automation released Verilog HDL

Verilog and simulator

1985: Verilog enhanced version Verilog-XL

1987: Verilog-XL becoming more popular (same year

VHDL released as IEEE standard)

1989: Cadence bought Gateway

1995: Verilog adopted by IEEE as standard 1364

Verilog HDL, Verilog 1995

2001: First major revision (cleanup and enhancements) Standard 1364-2001 (or Verilog 2001)


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Books


Starters Guide to Verilog 2001 by Ciletti, 2004, PrenticeHall 0-13-141556-5

Fundamentals of Digital Logic with Verilog Design by

Brown and Vranesic, 2003, McGraw-Hill, 0-07-282878-7 Modeling, Synthesis, and Rapid Prototyping with the

Verilog HDL, by Ciletti, 1999, Prentice-Hall, 0-13-

977398-3 Advanced Digital Design with the Verilog HDL, byCiletti, 2003, Prentice-Hall, 0-13-089161-4

HDL Chip Design by Smith, 1996, Doone Publications,0-9651934-8

Verilog Digital Design by Arnold, 1999, Prentice Hall,0-13-639253-9


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Create Verilog Module



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Module Created


No separate entity and arch

just module

Ports can be input, output, or

inout Note: Verilog 2001 has

alternative port style: (input a, b, sel, output y);


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Add assign statement


Similar to VHDL conditional signal assignment continuous assignment

Same hardware produced as with VHDL


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Verilog - general comments


VHDL is like ADA and Pascal in style Strongly typed more robust than Verilog

In Verilog it is easier to make mistakes

Watch for signals of different widths No default required for case statement, etc

Verilog is more like the c language

Verilog IS case sensitive

White space is OK

Statements terminated with semicolon (;)

Verilog statements between module and endmodule

Comments // single line and /* and */


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Verilog


Four-value logic system

0 logic zero, or false condition

1 logic 1, or true condition

x, X unknown logic value

z, Z - high-impedance state

Number formats

b, Bbinary

d, D decimal (default)

h, H hexadecimal

o, O octal 16H789A 16-bit number in hex format

1b0 1-bit


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Verilog types


Constants parameter DIME = 10;

parameter width = 32, nickel = 5;

parameter quarter = 8b0010_0101;

Nets wire clock, reset_n;

wire[7:0] a_bus;

Registers reg clock, reset_n;

reg[7:0] a_bus;

Integer only for use as general purpose variables in loops integer n;


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Operators


Bitwise ~ negat i on Ver i l og VHDL

& and y = a & b; y = a AND b;

| i ncl usi ve or y = a | b; y = A OR b;

^ excl usi ve or y = a b; y = a XOR b;

y = ~( a & b) ; y = A NAND b;

y = ~ a; y = NOT a;

Reduction (no direct equivalent in VHDL) Accept single bus and return single bit result

& and y = & a_bus;

~& nand

| or y = | a_bus; ^ excl usi ve or


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Operators (contd)


Relational (return 1 for true, 0 for false) < l ess t han, gr eat er t han >=

Equality == l ogi cal equal i t y

!= l ogi cal i nequal i t y

Logical Comparison Operators ! l ogi cal negat i on

&& l ogi cal and

|| l ogi cal or

Arithemetic Operators + -

*


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Operators (contd)


Shift >> ar i t hmet i c)

Conditional Only in Verilog - selects one of pair expressions ? :

Logical expression before ? is evaluated

If true, the expression before : is assigned to output

If false, expression after : is assigned to output

Y = (A > B) ? 1 : 0

Y = (A == B) ? A + B : A B


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Tri-state example


Using conditional operator in continuous assignment


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Concurrent statements


VHDL

Process

Signal assignments

Verilog

always statement

Continuous assignment - assign


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Sequential Statements


VHDL

reside in process statement

Verilog

reside in an always statement

ifstatements

case statements

Note: usebegin and endto block sequential statements


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Verilog wire and register data objects


Wire net, connects two signals together

wire clk, en;

wire [15:0] a_bus;

Reg register, holds its value from one proceduralassignment statement to the next

Does not imply a physical register depends on use

reg [7:0] b_bus;


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Index and Slice


VHDL

Use to and downto to specify slice

Concatenation & c_bus(3 downto 0)


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Decoder


2 to 4 decoder with enable

Combinational logic using always statement with sensitivity list

similar to VHDLprocess for cyclic behavior

(@) event control operator begin .. endblock statement

note reg for y


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Decoder (contd)


Combinational logic using always statement with

sensitivity list

similar to VHDLprocess for cyclic behavior

(@) event control operator

begin .. endblock statement

Statements execute sequentially

ifstatement case statement

Note: case expression can concatenate signals ({,})

Sensitivity list

(a orb orc)

Verilog 2001 allows comma-separated list (a, b, c)


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Flip-flops in Verilog


Always inferred using edge-triggered always statement


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Flip-flops in Verilog (with async)


Add async signals to sensitivity list


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Counters in Verilog


Just extension of D type

This example has async clear


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Counters in Verilog (contd)


With terminal count


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State Machine


SM1 4 states

Two always statements


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State Machine hardware


four flip-flops (can be changed through synthesis options)

Combinational logic for next state and outputs


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Blocking and non-blocking assignment


To ensure correct synthesis and simulation results:

Combinational logic

Use blocking assignment = statements in alwaysblock

Sequential logic

Use non blocking assignment


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Top-Down Design Hierarchy


Instantiate module (counter example with decoder)modul e decoder ( count , seven_seg) ;

i nput [ 3: 0] count ;

out put [ 6: 0] seven_seg;

/ / i nst ant i at e decoder modul e i n count er

/ / usi ng posi t i on of por t s

decoder d1 ( count _val , seven_seg_val ) ;

/ / or usi ng f or mal and act ual names

decoder d1 ( . count ( count _val ) , . seven_seg( seven_seg_val ) ) ;

d i l l


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Decoder Tutorial Example


C T Fi f W f


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Create Test Fixture from Waveform


T Fi f W f


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Test Fixture from Waveform


T t Fi t f W f ( ti d)


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Test Fixture from Waveform (continued)


Si l ti R lt


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Simulation Results


Si l ti N t


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Simulation Notes


Initialblock declares a single-pass behavior Executes once when simulator is activated

Delay control operator (#) and delay value - #10

Timescale compiler directive

timescale /

`timescale 10ns/1ns

Inputs are declared as reg values retains value untilupdated

Outputs are just monitored as wires

Generating clocks


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Generating clocks


Generating repetitive signalsi ni t i al begi n

cl k = 0;

endal ways begi n

#5 cl k = ~cl k;

end

Oral ways begi n

#5 cl k = 0;#5 cl k = 1;

end

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