vcc 6-led driver and gpio controller vcc · support gpio input/output mode gpio input mode,...

AW9106B Nov 2017 V1.1

www.awinic.com.cn 1 Copyright © 2014 SHANGHAI AWINIC TECHNOLOGY CO., LTD

6-LED Driver and GPIO Controller

FEATURES

6-channel LED constant-current driver, each channel can be used for GPIO

OUTx support 2 intelligent breathing mode: BLINK and SMART-FADE, breathing time is adjustable

Support 256 steps linearity dimming, IMAX is 37mA

Support GPIO input/output mode

GPIO input mode, internal 8μs debounce

Standard I2C interface

I2C interface and GPIO can operate at 1.8V

Support shutdown function, low level effective

Simple Voltage Range VCC: 2.5V~5.5V

TQFN 3mmX3mmX0.75mm-20L Package

APPLICATIONS

Mobile Phones/ Portable Media Player

Home Appliances

GENERAL DESCRIPTION

AW9106B is a 6-channel LED controller with I2C interface. Each channel can be used for GPIO. LED dimming combined with extended GPIO function, which can give full play to the application value of single chip. AW9106B configures the current level to realize 256 steps linear dimming with I2C interface. The

default IMAX current is 37mA. When OUTx works in a GPIO input mode, AW9106B detected input state to occur interrupt with internal 8μs debounce. AW9106B supports two intelligent breathing modes: BLINK mode and SMART-FADE mode. BLINK mode allows LED automatic to flash periodically according the setting time parameter. AW9106B is available in TQFN3X3-20L package.

The operating voltage range is 2.5V~5.5V.

TYPICAL APPLICATION CIRCUIT

VCC

GND

OUT0

VCCMCU

SCL

SDA

4.7kohm(x2)

INTN

MCU

VCC

OUT1

OUT2

AW9106B

OUT3

OUT4

OUT5

RGB LED

NCGND

RGB LED

SHDN

AD1

AD0

VBAT

VBAT

1μF

Figure 1 AW9106B Typical Application Circuit

All trademarks are the property of their respective owners.

AW9106B Nov 2017 V1.1


1 PIN CONFIGURATION AND TOP MARK

SDA

VCC

GND

INTN

SHDN

GND

NC

NC

OUT5

OUT4

SC

L

AD

0

NC

NC

AD

1

OU

T0

OU

T1

OU

T2

OU

T3

N

C

12

11

13

14

15

109876

5

4

3

2

1

16

17

18

19

20

9106BXXXX

9106B-AW9106BTQRXXXX-Manufactory Trace No.

AW9106B TOP VIEW AW9106B MARKING

2 PIN DEFINITION

NO NAME DESCRIPTION

1 SDA Serial Data I/O for I2C Interface

2 VCC Power Supply

3 GND Power Ground

4 INTN Interrupt Output, Low Active

5 SHDN Shutdown Pin, Low Active

6 AD1 I2C Address Pin

7 OUT0 Defaults to GPIO, LED driver configurable, support intelligence breathing mode. The default state after power on according to the level of AD1/AD0 PIN






13 NC NC

14 NC NC

15 GND Power Ground

16 NC NC

17 NC NC

18 NC NC

19 AD0 I2C Address Pin

20 SCL Serial Clock Input for I2C Interface

AW9106B Nov 2017 V1.1


3 FUNCTIONAL BLOCK DIAGRAM

VCC

AD1

SCL

SDA

INTN

OUT0

AW9106B

OUT1

OUT2

OUT3

OUT4

OUT5

CURRENT SOURCE

LED DRIVE AND GPIO

PORT

BLINK

SMART-FADE

DIMx Register

I2C I/F

GPIO CTLRegister

Cfg Register

InterruptLogic

LP Filter

POR OSC

AD0

GND

Figure 2 FUNCTIONAL BLOCK DIAGRAM

4 TYPICAL APPLICATION CIRCUITS

VCC

GND

OUT0

VCCMCU

SCL

SDA

4.7kohm(x2)

INTN

MCU

VCC

OUT1

OUT2

AW9106B

OUT3

OUT4

OUT5

RGB LED

NCGND

RGB LED

SHDN

AD1

AD0

VBAT

VBAT

1μF

Note: When the anode of LED is connected to VBAT, AD1/AD0 of the chip should be connected to VBAT to

ensure the default electricity state of GPIO is high or high resistance and the LED will be off. The default

electricity state of GPIO is decided by AD1/AD0 level.

AW9106B Nov 2017 V1.1


5 ORDERING INFORMATION

Part Number Temperature Package Marking MSL Level ROHS Delivery Form

AW9106BTQR -40℃～85℃ 3mm×3mm

×0.75mm AW9106B MSL3

ROHS

+HF

6000 units/

Tape and Reel

AW9106B

Shipping R：Tape & Reel

Package type TQ：Thin QFN

6 ABSOLUTE MAXIMUM RATINGS(NOTE 1)

Parameter Range

Supply Voltage range VCC -0.3V to 6 V

SCL,SDA,AD0,AD1,INTN,SHDN,OUT0-5 PINS voltage range -0.3V to VCC

Max power dissipation (PDmax,package@ TA=25℃) 3.2 W

Package thermal resistance θJA 31℃/W

Maximum Junction temperature TJmax 125℃

Storage temperature range -65℃ to 150℃

Lead temperature (Sodering 10 Seconds) 260℃

ESD(NOTE2)

HBM(All Pins) ±4000V

Latch-up

Test Condition：JEDEC STANDARD NO.78A FEBURARY 2006 +IT：＋450mA

-IT：-450mA

NOTE1: Conditions out of those ranges listed in "absolute maximum ratings" may cause permanent

damages to the device. In spite of the limits above, functional operation conditions of the device should

within the ranges listed in "recommended operating conditions". Exposure to absolute-maximum-rated

conditions for prolonged periods may affect device reliability.

NOTE2: The human body model is a 100pF capacitor discharged through a 1.5kΩ resistor into each pin.

Test method: MIL-STD-883G Method 3015.7

AW9106B Nov 2017 V1.1


7 ELECTRICAL CHARACTERISTICS

Vcc=3.8V, TA=25℃ for typical values (unless otherwise noted)

PARAMETER TEST CONDITION MIN TYPE MAX UNIT

Power supply voltage and current

VCC Input voltage TA=-40℃~85℃ 2.5 5.5 V

VPOR Power on reset voltage TA=-40℃~85℃ 1.8 2.3 V

ISHUTDOWN Current in Shutdown mode SHDN=0V,VIO=0V 0.1 2 μA

SHDN=0V,VIO=1.8V 8.5

ISTANDBY Current in Standby mode SHDN=1.8V,VIO=1.8V 80 μA

IACTIVE

Current in GPIO mode

GPMD_A=0x03, GPMD_B=0x0F,

GPIO_CFG_A=0x03, GPIO_CFG_B=0x0F,

AD1=AD2=1.8V

80 μA

GPMD_A=0x03, GPMD_B=0x0F,

GPIO_CFG_A=0x00, GPIO_CFG_B=0x00,

GPIO_OUTPUT_A=0x03,

GPIO_OUTPUT_B=0x0F,

13 uA

Current in LED mode GPMD_A=0x00, GPMD_B=0x00

ISEL=3, DIMx=0xFF 1.7 mA

Digital output

VOH Output high level(OUT0~5)

VCC=2.5V,ISOURCE=10mA VCC-170 mV

VCC=3.6V,ISOURCE=20mA VCC-250 mV

VCC=5V,ISOURCE=20mA VCC-200 mV

VOL

Output low level(OUT0~5)

VCC=2.5V,ISINK=20mA 90 mV


VCC=5V,ISINK=20mA 60 mV

Output low level

(SDA,INTN)



VCC=5V,ISINK=6mA 75 mV

Digital input

VIH Logic high level

(SCL,SDA,SHDN,AD0,AD1,OUT0~5) 1.4 V

VIL Logic low level

(SCL,SDA,SHDN,AD0,AD1,OUT0~5) 0.4 V

IIH,IIL Input current

(SCL,SDA,AD0,AD1,OUT0~5) VI=VCC or GND -0.2 +0.2 μA

R_SHDN Resistant of shutdown pin 100k Ω

CI Input capacitor

(SCL,SDA,SHDN,AD0,AD1,OUT0~5) VI=VCC or GND 3 pF

tSP_SHDN Low burr pulse width SHDN=VCC 10 μs

LED driver

ILED Current Source ISEL=0,DIMx=FFH 37 mA

Vdrop1 Low-6(OUT0~5)output voltage drop IOUT=21mA,ISEL=01,DIMx=C0H 60 200 mV

AW9106B Nov 2017 V1.1


8 I2C INTERFACE TIMING

Parameter Symbol MIN TYP MAX UNIT

Interface Clock frequency fSCL 400 kHz

(Repeat-start) Start condition hold time tHD:STA 0.6 μS

Low level width of SCL tLOW 1.3 μS

High level width of SCL tHIGH 0.6 μS

(Repeat-start) Start condition setup time tSU:STA 0.6 μS

Data hold time tHD:DAT 0 μS

Data setup time tSU:DAT 0.1 μS

Rising time of SDA and SCL tR 0.3 μS

Falling time of SDA and SCL tF 0.3 μS

Stop condition setup time tSU:STO 0.6 μS

Time between start and stop condition tBUF 1.3

Maximum width noise input filter out(burr) tSP 0 50 nS

Capacitor of the bus Cb 400 pF

SDA

SCL

tBUF tLOW

tHD:STA tHD:DAT

tR tHIGH tF

tSU:DAT

tSP

tSU:STO

VIH

VIL

StopStop Start Start

VIH

VIL

tSU:STA

AW9106B Nov 2017 V1.1


9 FUNCTIONAL DESCRIPTION

AW9106B is a 6 channel co-anode current breathing led driver. There is 256 current levels configurable via

register CTL.ISEL. The maximum driver current IMAX is 37mA.

The led drivers and GPIO can switch to another one with configuring register GPMD_A/GPMD_B. The default

status of OUT0~OUT5 are used for GPIO function.

AW9106B supports two types of intelligent breathing modes: BLINK and SMART-FADE. In BLINK mode,

AW9106B completes "fade-on" and "fade off" breathing periodically. In SMART-FADE mode, AW9106B runs

"fade-on" and "fade off" independently with register GPIO_OUTPUT_A/GPIO_OUTPUT_B configuration.

9.1 SHUTDOWN AND RESET

AW9106B enters shutdown mode when SHDN is low level. When SHDN is pulled up from shutdown state,

AW9106B enters standby mode and will be reset to the default state.

AW9106B offers 3 kinds of reset function：

Power on reset -- 5ms after power on, the chip is reset to the default state.

Hardware reset – keep SHDN low level over 20 μs, reset all internal circuit.

Software reset -- write 00H to register 7FH, reset all internal circuit.

When AW9106B is reset, the default state of OUTx pin is GPIO.

9.2 LED DIMMING FUNCTION

AW9106B led driver uses co-anode current source. In default status, the maximum driving current IMAX is 37mA.

After power on, OUTx(x=0~5) used for GPIO. AW9106B can switch OUTx to led driver mode with configuring

GPMD_A and GPMD_B, shown in table 4&5.

AW9106B configures four dimming range by ISEL[1:0], 0~IMAX(default), 0~(3/4)IMAX, 0~(2/4)IMAX or 0~(1/4)IMAX,

which means 256 steps dimming range: 0~37mA(default),0~27.75mA, 0~18.5mA or 0~9.25mA. ISEL[1:0]

configuration is refer to table 3.

The dimming level of each channel is configured by DIMx(x=0~5) register. 8-bits DIMx can be configured to

256 levels, from 00H to FFH.

DIMx bit

Dimming level

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 OFF

0 0 0 0 0 0 0 1 1/255×IMAX

0 0 0 0 0 0 1 0 2/255×IMAX

…… ……

1 1 1 1 1 1 0 1 253/255×IMAX

1 1 1 1 1 1 1 0 254/255×IMAX

1 1 1 1 1 1 1 1 255/255×IMAX

AW9106B Nov 2017 V1.1


9.3 GPIO FUNCTION

When AW9106B is used in GPIO, the direction of OUTx is configured by GPIO_CFG_A/GPIO_CFG_B

(table14, 15). When OUTx is configured to output, write GPIO_OUTPUT_A or GPIO_OUTPUT_B register

(table12, 13) driver high or low level.

The following table shows OUTx default output driving value after power on.

AD1 AD0 OUT5 OUT4 OUT3 OUT2 OUT1 OUT0

GND GND 0 0 0 0 0 0

GND VCC Hi-Z Hi-Z 1 1 1 1

VCC GND 0 0 0 0 0 0

VCC VCC Hi-Z Hi-Z 1 1 1 1

When OUTx is configured to input mode, the logic level of OUTx can be acquired with reading GPIO_INPUT_A

or GPIO_INPUT_B register (table 10, 11). AW9106B can support 1.8V level logic.

OUT0~OUT3 are default to PUSH-PULL driver. OUT4~OUT9 are default to OPEN-DRAIN driver and can be

configured as PUSH-PULL driver with GPOMD (table 3).

9.4 INTERRUPT FUNCTION

When OUTx is used for GPIO input, AW9106B detects the input state and produces interrupt request. Low

level of INTN is active. INTN should be connected to pull-up resistor.

AW9106B has built-in debounce filter. The input state with 8μs low-pass filter will be steady. The interrupt

request will not be produced when input state changes in 8μs.

In default status, GPIO interrupt is enabled (GPIO_INTN_A or GPIO_INTN_B setting, table16,17). Only enable

interrupt function and configured to GPIO input mode, the interrupt will be produced on INTN.

Clear the interrupt by reading register GPIO_INPUT_A, GPIO_INPUT_B register. The interrupt of

OUT4~OUT5 only be cleared by read GPIO_INPUT_A register. The interrupt of OUT0~OUT3 only be cleared

by read GPIO_INPUT_B register. The interrupts status can't be cleared by the other group.

When AW9106B produces the interrupt request, the interrupt request will be reserved until reading

GPIO_INPUT_A or GPIO_INPUT_B GPIO. The interrupt will be not cleared even if AW9106B switches to

GPIO output, or disable GPIO interrupt function.

I2C BUS

OUT4~OUT5

INTN

8μs remove jitterRemove interrupt timing

Read GPIO_INPUT_A Register

9.5 BLINK BREATHING MODE

OUTx of AW9106B supports BLINK breathing mode. In this mode, AW9106B will complete periodic blink effect

automatically until exit the BLINK mode or close breathing function.

AW9106B Nov 2017 V1.1


1. Configure OUTx to led driver mode. According to application situation, set register EN_BRE to enable

breathing mode. Set GPIO_CFG_A/B (Table 14,15,pay attention to the switch of GPIO and breathing

function) to open BLINK function.

2. Configure the timing parameter for BLINK breathing effects:

Blink delay——DLY_TMR(Table 9). When enable the BLINK mode, led starts blink after DLY_TMR

time.

Fade-on process——FDON_TMR(Table 7). The time of fade-on effect has 6 kinds of choice

(0ms~5040ms). The fade-on has 64 step dimming level and led turns on gradually from dark.

Full on process——FLON_TMR(Table 8). Full on state has 8 kinds of choice(0ms~20160ms). the

led driving current of this period is decided by ISEL[1:0].

Fade-off process——FDOFF_TMR(Table 7). The time of fade-off effect has 6 kinds of choice

(0ms~5040ms). The fade-off has 64 step dimming level and led turns off gradually from bright.

Full off process——FLOFF_TMR(Table 8). Full off state has 8 kinds of choice(0ms~20160ms). The

led driving current is 0 in this period.

3. After setting blinking parameter, enable GO control bit and the led in BLINK mode starts blink periodically

and automatically.

DLY_BRE of 6 channel, the parameter of BLINK mode, is independent configuration, which can make led be

opened in turn. The fade-on/ fade-off/ full-on/ full-off parameter are same and can be modified at any time. The

new configuration will be adjusted in the next breathing period.

AW9106B exits BLINK mode by disable GPIO_CFG_A/B corresponding bit or disable EN_BRE setting. The

difference is AW9106B will exit BLINK immediately by disable EN_BRE, but we must wait it complete breathing

period by another one.

FLOFF_TMRFDON_TMR FLON_TMR FDOFF_TMR

1 cycle repeat cycleImax

DLY0_TMR

DLY1_TMR

DLY2_TMR

DLY3_TMR

DLY4_TMR

DLY5_TMR

GO

9.6 SMART-FADE MODE

The SMART-FADE mode of AW9106B is semi-automatic breathing, which will simplify 64 steps fade-on and

fade-off interface operation into 1bit writing operation: Writing ’1’ means fade-on process and remaining all

bright; Writing ’0’ means fade-off process and remaining all dark.

Configure SMART-FADE mode:

AW9106B Nov 2017 V1.1


1. Set EN_BRE register and open breathing mode according to the application;

2. Set GPIO_CFG_A/B (View table 14,15, pay attention to the switch of GPIO and breathing function),

SMART-FADE mode is default;

3. Set GPIO_OUTPUT_A/B bit to complete fade-on or fade-off (View table 12,13, pay attention to the switch

of GPIO and breathing function).

The time of fade-on and fade-out in SMART-FADE mode is controlled by FDON_TMR and FDOFF_TMR.

AW9106B exits SMART-FADE mode by disable EN_BRE.

EN_BREsetFDON_TMR

setFDOFF_TMR

writeGPIO_OUTPUT_A

01H

writeGPIO_OUTPUT_A

00H

OUT4 driving current

I2C interface operation

FDON_TMR FDOFF_TMR

All dark

All bright

Configurate OUTx into LED driver

AW9106B Nov 2017 V1.1


10 I2C INTERFACE

AW9106B supports the I²C serial bus and data transmission protocol in fast mode at 400 KHz. AW9106B

operates as a slave on the I²C bus. Connections to the bus are made via the open-drain I/O pins SCL and

SDA. The pull-up resistor can be selected in the range of 1k~10kΩ and the typical value is 4.7kΩ. AW9106B

can support different high level (1.8V~3.3V) of this I2C interface.

10.1 Start and Stop Condition

I2C start: SDA changes form high level to low level when SCL is high level.

I2C stop: SDA changes form low level to high level when SCL is high level.

SCL

SDA

S/Sr

S: start conditionSr：repeat start condition

P：stop condition

10.2 Data Transmission

After the start condition, I2C bus sent an address of slave. AW9106B wait to receive slave address When

receiving start condition. If the address from I2C bus is same as the address of AW9106B, the slave pull SDA

to acknowledge.

10.3 Data Validity

When SCL is in high level, SDA must remain one level stationary .Except start condition and stop condition,

SDA level can change just in low level of SCL.

AW9106B Nov 2017 V1.1


SCL

SDA

Data line stableData effective

Data allowed to change

10.4 Acknowledge

ACK means the successful transfer of I2C bus data. After master sends 8bits data, SDA must be released;

SDA is pulled to GND by slave device when slave acknowledges.

When master reads, slave device sends 8bit data, releases the SDA and waits for ACK from master. If ACK is

sent and I2C stop is not sent by master, slave device sends the next data. If ACK is not sent by master, slave

device stops to send data and waits for I2C stop.

1 2 8 9

Data Output Sender

Data Output Receiver

HostSend Clock

Start Condition

No Answer（NACK）

Answer（ACK）

Answer Clock

10.5 Address

AW9106B supply two address pins AD1,AD0. This allows single I2C bus can use four AW9106B at the same

time. The high five bit of slave address is “10110”, the bit2 is AD1, and the bit1 is AD0. The bit0(LSB) is writing

and reading flag bit, which define the next operation writing or reading. ‘1’ is read and ‘0’ is write.

AD0AD101101

（The value of AD1 and AD0 is same as AD1 and AD0 PIN）

R/W

AW9106B Nov 2017 V1.1


10.6 Writing Operation

One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock

(SCL). Consequently, throughout the clock’s high period, the data should remain stable. Any changes on the

SDA line during the high state of the SCL and in the middle of a transaction, aborts the current transaction.

New data should be sent during the low SCL state. This protocol permits a single data line to transfer both

command/control information and data using the synchronous serial clock.

Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and

a Stop Condition to terminate the transaction. Every byte written to the SDA bus must be 8 bits long and is

transferred with the most significant bit firstly. After each byte, an Acknowledge signal must follow.

In a write process, the following steps should be followed: 1) Master device generates START condition. The “START” signal is generated by lowering the SDA signal

while the SCL signal is high.

2) Master device sends slave address (7-bit) and the data direction bit (w = 0).

3) Slave device sends acknowledge signal if the slave address is correct.

4) Master sends control register address (8-bit)

5) Slave sends acknowledge signal

6) Master sends 8Bit data to be written to the addressed register


8) Master generates STOP condition to indicate write cycle end

1 0 1 1 0 AD1 AD0 0 A MSB LSB A A MSB LSB

Register address

7bits slave

address

Start condition

AW9110B answer

AW9110B answer

Register data

AW9110B answer

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

Stop conditionIt is reply clock from 8

th clock rising edge to 9th cloCk falling edge；AW9110B pull-down SDA to answer, the host must release SDA, if not ,the leakage of electric will appear in this period.

10.7 Reading Operation

In a read cycle, the following steps should be followed:

1) Master device generates START condition

2) Master device sends slave address (7-bit) and the data direction bit (w = 0).


4) Master sends control register address (8-bit)


6) Master generates STOP condition followed with START condition or REPEAT START condition

7) Master device sends slave address (7-bit) and the data direction bit (r = 1).

AW9106B Nov 2017 V1.1



9) Slave sends 8Bit data from addressed register.

10) Master sends acknowledge signal

11) If the master device sends acknowledge signal, the slave device will increase the control register address

by one, then send the next data from the new addressed register. If master sends no acknowledge signal,

the slave device stop to send data and wait for STOP condition.

12) If the master device generates STOP condition, the read cycle is ended.

1 0 1 1 0 AD1 AD0 0 A MSB LSB A

NA MSB LSB

Register address

7bits slave address

Start condition

AW9110B answer

Reading data

Host do not answer

Stop condition

1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9

SDA

SCL

1 2 3 4 5 6 7 8 9

1 0 1 1 0 AD1 AD0 1 A

7bits slave address

AW9110B answer

AW9110B answer

Repeat start condition

Host is the data receiver this time;AW9110B is the sender .

S

11 REGISTER DESCRIPTION

11.1 REGISTER OVERVIEW

Table 1. AW9106B registers list

Addr

(HEX) W/R

Defaut Value

(HEX)

Function Description

00H R xxH GPIO_INPUT_A OUT4～OUT5 port GPIO input state

01H R xxH GPIO_INPUT_B OUT0～OUT3 port GPIO input state

02H W/R Depend on AD1/ AD0

GPIO_OUTPUT_A OUT4～OUT5 port GPIO output state;

In SMART-FADE mode, OUT4~OUT5 can be used for “fade-on” and “fade-off” dimming control.

03H W/R Depend on AD1/ AD0

GPIO_OUTPUT_B OUT0～OUT3 port GPIO output state;

In SMART-FADE mode, OUT0~OUT3 can be used for “fade-on” and “fade-off” dimming control.

04H W/R 00H GPIO_CFG_A OUT4～OUT5 port GPIO input and output direction control;

AW9106B Nov 2017 V1.1


In breathing mode, control OUT4~OUT5 to enter into BLINK mode or SMART-FADE mode.

05H W/R 00H GPIO_CFG_B OUT0～OUT3 port GPIO input and output direction control;

In breathing mode, control OUT0～OUT3 to enter into BLINK mode or SMART-FADE mode.

06H W/R 00H GPIO_INTN_A OUT4～OUT5 enable interrupt function

07H W/R 00H GPIO_INTN_B OUT0～OUT3 enable interrupt function

08H~10H - - - Reserved

11H W/R 00H CTL Global Control

12H W/R FFH GPMD_A Switch OUT4～OUT5 LED driver mode or GPIO mode

13H W/R FFH GPMD_B Switch OUT0～OUT3 LED driver mode or GPIO mode

14H W/R 00H EN_BRE Enable LED breathing mode

15H W/R 00H FADE_TMR In BLINK or SMART-FADE mode, LED “fade-on” or “fade-off” time parameter

16H W/R 00H FULL_TMR In BLINK mode, LED light all on or all off time parameter

17H W/R 00H DLY0_BRE In BLINK mode,OUT0 blink delay time before start



1AH W/R 00H DLY3_BRE In BLINK mode,OUT3 blink delay time before start

1BH W/R 00H DLY4_BRE In BLINK mode,OUT4 blink delay time before start

1CH W/R 00H DLY5_BRE In BLINK mode,OUT5 blink delay timer before start

1DH~1FH - - - Reserved

20H W 00H DIM0 OUT0 port 256 steps dimming control






26H~7EH - - - Reserve

7FH W 00H RESET Write 00H,reset by software

AW9106B Nov 2017 V1.1


11.2 REGISTER DETAIL

Table 2. DIM0~DIM5(20H~25H),256 steps dimming configuration register

Bit Symbol Description Default

D[7:0] DIM 256 steps dimming level choice

20H~25H corresponding to OUT0~OUT5 dimmer instruction; D[7:0] code from 0 to 255 corresponding to the current 0~IMAX

00H

Table 3. CTL(11H),Global control register


D7 GO Writing 1 to enable breathing in BLINK mode. 0

D[6:5] - - Remain

D4 GPOMD OUT4～OUT5 driver option in GPIO mode

0：OPEN-DRAIN

1：PUSH-PULL

0

D[3:2] - - Remain

D[1:0] ISEL 256 dimming range option

00：0～37mA

01：0～27.75mA

10：0～18.5mA

11：0～9.25mA

00

Table 4. GPMD_A(12H), GPIO control switch to LED driver register


D[7:2] - - Remain

D1 GPMD_A1 OUT5 mode control

0：LED mode

1：GPIO mode

1

D0 GPMD_A0 OUT4 mode control

0：LED mode

1：GPIO mode

1

Table 5. GPMD_B(13H), GPIO control switch to LED driver register


AW9106B Nov 2017 V1.1


D[7:4] - - Remain

D3 GPMD_B3 OUT3 mode control

0：LED mode

1：GPIO mode

1


0：LED mode

1：GPIO mode

1


0：LED mode

1：GPIO mode

1


0：LED mode

1：GPIO mode

1

Table 6. EN_BRE(14H),EN_BREATHING REGISTER


D[7:6] - - Remain

D5 EN_BRE5 OUT5 enable breath mode

0：disable

1：enable

0


0：disable

1：enable

0


0：disable

1：enable

0


0：disable

1：enable

0


0：disable

1：enable

0

D0 EN_BRE0 OUT0 enable breath mode 0

AW9106B Nov 2017 V1.1


0：disable

1：enable

Table 7. FADE_TMR(15H),Fade-on or fade-off time setting register in BLINK or SMART-FADE


D[7:6] - - Remain

D[5:3] FDOFF_TMR Fade-off time setting

000：0ms

001：315ms

010：630ms

011：1260ms

100：2520ms

101：5040ms

110/111：0ms

000

D[2:0] FDON_TMR Fade-on time setting

000：0ms

001：315ms

010：630ms

011：1260ms

100：2520ms

101：5040ms

110/111：0ms

000

Table 8. FULL_TMR(16H),All-on or all-off time setting register in BLINK mode.


D[7:6] - - Remain

D[5:3] FLOFF_TMR All-off time setting

000：0ms

001：315ms

010：630ms

011：1260ms

100：2520ms

101：5040ms

110：10080ms

111：20160ms

000

AW9106B Nov 2017 V1.1


D[2:0] FLON_TMR All-on time setting

000：0ms

001：315ms

010：630ms

011：1260ms

100：2520ms

101：5040ms

110：10080ms

111：20160ms

000

Table 9. DLY0_BRE~DLY5_BRE(17H~1CH),delay to breath time setting register in BLINK


D[7:0] DLY_TMR Start time to delay breathing in BLINK mode

00H：0ms

01H：315ms

……

FFH：80640ms

(per 1 unit: 315ms)

00H

Table 10. GPIO_INPUT_A(00H),GPIO input state register


D[7:2] - - Remain

D1 GPIO_INPUT_A1 OUT5 pin state

0：Low level

1：High level

x

D0 GPIO_INPUT_A0 OUT4 pin state

0：Low level

1：High level

x

Table 11. GPIO_INPUT_B(01H),GPIO input state register


D[7:4] - - Remain

D3 GPIO_INPUT_B3 OUT3 pin state

0：Low level

1：High level

x

AW9106B Nov 2017 V1.1



0：Low level

1：High level

x


0：Low level

1：High level

x


0：Low level

1：High level

x

Table 12. GPIO_OUTPUT_A(02H),GPIO output state register or as driver control in SMART-FADE

mode


D[7:2] - - Remain

D1 GPIO_OUTPUT_A1 GPMD_A1=1,as driving OUT5 pin state

0：Low level

1：High level

GPMD_A1=0 & EN_BRE5=1, OUT5 in SMART-FADE mode

0->1：fade-on

1->0：fade-off

Depend

on AD0

and AD1

D0 GPIO_OUTPUT_A0 GPMD_A0=1,as OUT4 pin state

0：Low level

1：High level

GPMD_A0=0 & EN_BRE4=1, OUT4 in SMART-FADE mode

0->1：fade-on

1->0：fade-off

Table 13. GPIO_OUTPUT_B(03H),GPIO output state register or as driver control in SMART-FADE

mode


D[7:4] - - Remain

D3 GPIO_OUTPUT_B3 GPMD_B3=1,as driving OUT3 pin state

0：Low level

1：High level

Depend

on AD0

and AD1

AW9106B Nov 2017 V1.1


GPMD_B3=0 & EN_BRE3=1,OUT3 in SMART-FADE mode

0->1：fade-on control

1->0：fade-off control

D2 GPIO_OUTPUT_B2 GPMD_B2=1, as driving OUT2 pin state

0：low level

1：high level





0：low level

1：high level





0：low level

1：high level


0->1：fade-on

1->0：fade-off

Table 14. GPIO_CFG_A(04H),GPIO input or output select register or as BLINK,SMART-FADE Mode

select


D[7:2] - - Remain

D1 GPIO_ CFG _A1 GPMD_A1=1, OUT5 input or output choice

0：output

1：input

GPMD_A1=0 & EN_BRE5=1, OUT5 BLINK or SMART-FADE mode choice

0：SMART-FADE mode

0

AW9106B Nov 2017 V1.1


1：BLINK mode

D0 GPIO_ CFG _A0 GPMD_A0=1, OUT4 input or output choice

0：output

1：input

GPMD_A0=0 & EN_BRE4=1, OUT4 BLINK or SMART-FADE mode choice

0：SMART-FADE mode

1：BLINK mode

0

Table 15. GPIO_CFG_B(05H),GPIO input or output selection register, or used for BLINK,SMART-

FADE mode choice


D[7:4] - - Remain

D3 GPIO_ CFG _B3 GPMD_B3=1 , OUT3 input or output choice

0：output

1：input

GPMD_B3=0 & EN_BRE3=1, OUT3 BLINK or SMART-FADE mode choice

0：SMART-FADE mode

1：BLINK mode

0

D2 GPIO_ CFG _B2 GPMD_B2=1, OUT2 input or output choice

0：output

1：input


0：SMART-FADE

1：BLINK

0


0：output

1：input


0：SMART-FADE mode

1：BLINK mode

0

AW9106B Nov 2017 V1.1



0：output

1：input

GPMD_B0=0 EN_BRE0=1, OUT0 BLINK or SMART-FADE mode choice

0：SMART-FADE mode

1：BLINK mode

0

Table 16. GPIO_INTN_A(06H),GPIO Enable Interrupt Register


D[7:2] - - Remain

D1 GPIO_ INTN _A1 OUT5 enable interrupt

0：enable

1：disable

0

D0 GPIO_ INTN _A0 OUT4 enable interrupt

0：enable

1：disable

0

Table 17. GPIO_INTN_B(07H),GPIO Enable Interrupt Register


D[7:4] - - Remain

D3 GPIO_ INTN _B3 OUT3 enable interrupt

0：enable

1：disable

0


0：enable

1：disable

0


0：enable

1：disable

0


0：enable

1：disable

0

AW9106B Nov 2017 V1.1


12 TAPE AND REEL INFORMATION

12.1 Carrier Tape

12.2 PIN1 Direction

User Direction of Feed

AW9106B Nov 2017 V1.1


12.3 Reel

Notes:

1. Material: polystyrene 2. Flatness: maximum permissible 3mm 3. All dimensions are in millimeters 4. Surface resistivity: 105 to 1011 ohms/sq or less

5. All unmarked tolerance: ±0.5

AW9106B Nov 2017 V1.1


13 PACKAGE DESCRIPTION

3.000±0.050

1.650±0.050

Exo.DAP

PIN 1# DOT

BY MARKING

TQFN-20L

(3 X 3mm)

TOP VIEW

1.650±0.050

Exp.DAP

PIN 1# IDENTIFICATION

CHAMFER C0.300x45º

3.000±0.050

0.400±0.050

0.400 Bsc

0.200±0.050

1.600

Ref.

BOTTOM VIEW

0.750±0.050

0.000-0.050

0.203 Ref.

SIDE VIEW

14 RECOMMENDED LAND PATTERN

4X(1.1)

20X(0.2)

4X(0.825)

20X(0.5)

16X(0.4)

TOP VIEW

0.3

0.3

AW9106B Nov 2017 V1.1


15 REFLOW

Reflow profile

Figure 17 Package Reflow Oven Thermal Profile

Parameters for classification reflow profile

Note: 1. All of the temperature parameters are measured from the top of package;

2、AW9817 is suitable for Pb-Free assembly.

AW9106B Nov 2017 V1.1


16 REVISION HISTORY

Vision Date Revision Record

V1.0 March 2017 First officially release

V1.1 Nov. 2017 Update the electrical characteristics

Update the ordering information

Add the recommended land pattern

AW9106B Nov 2017 V1.1


17 DISCLAIMER

Information in this document is believed to be accurate and reliable. However, Shanghai AWINIC Technology

Co., Ltd (AWINIC Technology) does not give any representations or warranties, expressed or implied, as to

the accuracy or completeness of such information and shall have no liability for the consequences of use of

such information.

AWINIC Technology reserves the right to make changes to information published in this document, including

without limitation specifications and product descriptions, at any time and without notice. Customers shall

obtain the latest relevant information before placing orders and shall verify that such information is current

and complete. This document supersedes and replaces all information supplied prior to the publication hereof.

AWINIC Technology products are not designed, authorized or warranted to be suitable for use in medical,

military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an

AWINIC Technology product can reasonably be expected to result in personal injury, death or severe property

or environmental damage. AWINIC Technology accepts no liability for inclusion and/or use of AWINIC

Technology products in such equipment or applications and therefore such inclusion and/or use is at the

customer’s own risk.

Applications that are described herein for any of these products are for illustrative purposes only. AWINIC

Technology makes no representation or warranty that such applications will be suitable for the specified use

without further testing or modification.

All products are sold subject to the general terms and conditions of commercial sale supplied at the time of

order acknowledgement.

Nothing in this document may be interpreted or construed as an offer to sell products that is open for

acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other

industrial or intellectual property rights.

Reproduction of AWINIC information in AWINIC data books or data sheets is permissible only if reproduction

is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.

AWINIC is not responsible or liable for such altered documentation. Information of third parties may be

subject to additional restrictions.

Resale of AWINIC components or services with statements different from or beyond the parameters stated by

AWINIC for that component or service voids all express and any implied warranties for the associated

AWINIC component or service and is an unfair and deceptive business practice. AWINIC is not responsible or

liable for any such statements.

6-LED Driver and GPIO Controller1 PIN CONFIGURATION AND TOP MARK2 PIN DEFINITION3 FUNCTIONAL BLOCK DIAGRAM4 TYPICAL APPLICATION CIRCUITS5 ORDERING INFORMATION6 ABSOLUTE MAXIMUM RATINGS(NOTE 1)7 ELECTRICAL CHARACTERISTICS8 I2C INTERFACE TIMING9 FUNCTIONAL DESCRIPTION9.1 SHUTDOWN AND RESET9.2 LED DIMMING FUNCTION9.3 GPIO FUNCTION9.4 INTERRUPT FUNCTION9.5 BLINK BREATHING MODE9.6 SMART-FADE MODE

10 I2C INTERFACE10.1 Start and Stop Condition10.2 Data Transmission10.3 Data Validity10.4 Acknowledge10.5 Address10.6 Writing Operation10.7 Reading Operation

11 REGISTER DESCRIPTION11.1 REGISTER OVERVIEW11.2 REGISTER DETAIL

12 TAPE AND REEL INFORMATION12.1 Carrier Tape12.2 PIN1 Direction12.3 Reel

13 PACKAGE DESCRIPTION14 RECOMMENDED LAND PATTERN15 REFLOW16 REVISION HISTORY17 DISCLAIMER

vcc 6-led driver and gpio controller vcc · support gpio input/output mode gpio input mode,...

Documents