Creating a Floorplan With Overlapping I/O, Macro and Standard Cell Areas Version F-2011.09, November 2011

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Contents

Using the I/O Area for Macro and Standard Cell Placement ................................. 4

Initializing the Floorplan ......................................................................................... 5

Initializing the Floorplan With Spacing Along the Edge of the Die ......................... 6

Creating Space Along the Edge of the Die Using Placement Blockages .............. 6

Inserting Space Between I/O Pads and Macros and Standard Cells .................... 7

Preventing Routing Over the I/O Pads .................................................................. 8

Power Routing ....................................................................................................... 9

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Using the I/O Area for Macro and Standard Cell Placement

This document describes the steps necessary to create a floorplan that uses the I/O placement area for the placement of I/Os, macros and standard cells. The placement and the power routing commands operate only in the core area, so changes to the default floorplanning flow are necessary to implement this type of layout.

An example floorplan using this methodology is shown in Figure 1:

Figure 1 Floorplan with Overlapping I/O and Macro Placement Areas

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Initializing the Floorplan

A default floorplan contains a core area enclosed by a die area. The space between the core area and die area is reserved for I/O pads as shown in Figure 2.

Figure 2 Core and Die Area with I/O Pad Spacing

The -left_io2core, -right_io2core, -top_io2core, and -bottom_io2core options

to the create_floorplan command specify the spacing between the die area and core

area. When you specify a positive value to these options, the spacing becomes larger and the core area becomes smaller.

To create a floorplan that uses the I/O area for macro and standard cell placement, as well as I/O pad and driver placement, you must specify a negative value for the

-left_io2core, -right_io2core, -top_io2core, and -bottom_io2core options.

Specifying a negative value for these options allows you to create a floorplan with the same core and die area size. The following script sets a negative value for the I/O to core spacing options.

01 set iopad_width 345.565

02 set io2core -$iopad_width

03 set die_width 2291.900

04 set die_height 2291.490

05 source pads.tcl

06 create_boundary -coordinate \

07 [list [list 0 0] [list $die_width $die_height]]

08 create_floorplan -control_type boundary \

09 -left_io2core $io2core -right_io2core $io2core \

10 -top_io2core $io2core -bottom_io2core $io2core

Note the minus sign in front of $iopad_width on line 2. This script creates a floorplan

with the same die and core area sizes. If you are using an IC Compiler version older

than F-2011.09, replace the create_floorplan command with initialize_floorplan.

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Initializing the Floorplan With Spacing Along the Edge of the Die

You might want to reserve space along the die boundary and avoid placing standard cells at the die edge. Cells that are too close to the edge might cause DRC violations. You can create additional spacing by reducing the I/O-to-core spacing. The following example script creates a die edge that is offset from the core area by 3.6 µm:

01 set iopad_width 345.565

02 set io2core [expr 3.6 - $iopad_width]

03 set die_width 2291.900

04 set die_height 2291.490

05 source pads.tcl

06 create_boundary -coordinate [list [list 0 0] \

07 [list $die_width $die_height]]

08 create_floorplan -control_type boundary \

09 -left_io2core $io2core -right_io2core $io2core \

10 -top_io2core $io2core -bottom_io2core $io2core

Note the change to line 2 of the script. This script creates a core area that is slightly smaller than the die area. If you plan to place your macros beyond the core boundary

and abut the die edge, the IC Compiler check_legality command will produce warning

messages. The check_legality command is run at the end of any placement-related

commands.

Creating Space Along the Edge of the Die Using Placement Blockages

To avoid warnings created by the check_legality command, you can create a hard

placement blockage around the entire die. You should block only a certain number of standard cell sites to prevent wasted die area and optimize the blockage. The following example creates a blockage of the same size as the 3.6 µm io2core offset used in the previous example. The script uses polygon commands to compute the dimensions of the placement blockages and avoids manual calculation.

01 set die_poly [get_attribute [get_die_area] boundary]

02 set place_block_poly [compute_polygons -boolean not $die_poly \

03 [resize_polygon -size -3.6 [convert_to_polygon $die_poly]]]

04 set n 0

05 foreach rectangle [convert_from_polygon $place_block_poly] {

06 create_placement_blockage -type hard \

07 -name fp_boundary_keepout_$n -bbox $rectangle

08 incr n

09 }

For the example floorplan, the command on line 1 defines the starting polygon bounding box as {0.000 0.000} {2291.900 0.000} {2291.900 2291.490} {0.000 2291.490} {0.000

0.000}. The compute_polygons command on line 2 calculates a polygon that

corresponds to the die area that is shrunk by 3.6 µm on each side. The loop beginning

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on line 5 converts the polygon to rectangles, which are used to create the placement blockages.

Inserting Space Between I/O Pads and Macros and Standard Cells

You may want to insert additional space between the I/O pads and the standard cells and macros. The easiest way to insert space is to create a keepout margin around all I/O

pads. The following example uses the get_flat_cells command. This command

should work for most designs. Note that $margin_width is the width of the keepout

margin.

01 set m [expr 2 * $margin_width]

02 set_keepout_margin -type hard -outer [list $m $m $m $m] \

03 [get_flat_cells -all -filter "is_io == true"]

You can also use the [get_cells -all -filter "mask_layout_type == io_pad"]

command to filter the I/O pad cells.

The preceding commands create a floorplan similar to the floorplan shown in Figure 3. The illustration shows the top left corner of the die containing one I/O pad with a margin and a placement blockage along the die edge.

Figure 3 Floorplan with Placement Blockages at the Die Edge

A different and more portable approach is to use placement blockages to create space between the I/O pads and the standard cells and macros in the design. This approach is useful if you are exporting the floorplan to DEF file later in the flow. Use the

compute_polygons and resize_polygon commands to create new boundaries for the

placement blockages.

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The following example script adds placement blockages to the design. The script creates a polygon around each I/O cell and increases the size by 3.6 µm on each side. Next, the script subtracts the core polygon from the die polygon. The result is used to create the placement blockages.

01 set core_poly [get_attribute [get_core_area] boundary]

02 foreach_in_collection iopad [get_flat_cells -all \

03 -filter "is_io == true"] {

04 set core_poly [compute_polygons -boolean not $core_poly \

05 [resize_polygon -size 3.6 [convert_to_polygon $iopad]]]

06 }

07 set die_poly [get_attribute [get_die_area] boundary]

08 set place_block_poly [compute_polygons \

09 -boolean not $die_poly $core_poly]

10 set n 0

11 foreach rectangle [convert_from_polygon $place_block_poly] {

12 create_placement_blockage -type hard \

13 -name fp_boundary_keepout_$n -bbox $rectangle

14 incr n

15 }

Preventing Routing Over the I/O Pads

If the FRAM views of the I/O pads are not completely blocked, you must create route

guides to prevent commands such as create_power_straps from creating straps over

the I/O pads. The following example adds route guides over all I/O pads and around the edges. The script allows routing 0.5 µm into the I/O pads and 0.5 µm in from the die edges.

01 set route_poly [resize_polygon -size -0.5 $die_poly]

02 foreach_in_collection iopad [get_flat_cells -all \

03 -filter "is_io == true"] {

04 set route_poly [compute_polygons -boolean not $route_poly \

05 [resize_polygon -size -0.5 [convert_to_polygon $iopad]]]

06 }

07 set route_block_poly [compute_polygons \

08 -boolean not $die_poly $route_poly]

09 set n 0

10 foreach rectangle [convert_from_polygon $route_block_poly] {

11 create_route_guide \

12 -name fp_route_block_$n \

13 -no_preroute_layers {METAL METAL2 METAL3 METAL4 \

14 METAL5 METAL6} \

15 -no_signal_layers {METAL METAL2 METAL3 METAL4 \

16 METAL5 METAL6} \

17 -zero_min_spacing \

18 -coordinate $rectangle

19 incr n

20 }

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Power Routing

To use some power routing commands, you must consider the negative io2core offset described in the previous sections. For example, to put VDD and VSS rings around the new core, use the following command:

create_rectilinear_rings -nets {VDD VSS} -offset {-360 -360} \

-width {5 5} -layers {METAL5 METAL6}

By default, when you specify -offset {0 0}, IC Compiler places the power rings

around the perimeter of the core area, However, if you are using the I/O area for cell and

macro placement, the -offset {0 0} option places the power rings outside of the die

area. To place the rings correctly, specify a negative offset that is larger than the width of the I/O pads.

You can use the route guides added in the previous steps to create power straps in x- and y-directions. The route guides prevent straps from routing over the I/O pads. Since the straps are not surrounded by the rings, the tool places some straps outside the die area. These straps are later removed by default. The following syntax retains the

horizontal floating pieces; the second create_power_straps command connects the

pieces to the vertical straps.

create_power_straps -direction horizontal -num_placement_strap 40 \

-increment_x_or_y 60 -nets {VDD VSS} -layer METAL5 -width 2 \

-keep_floating_wire_pieces

create_power_straps -direction vertical -num_placement_strap 40 \

-increment_x_or_y 60 -nets {VDD VSS} -layer METAL6 -width 2

Figure 4 shows a screenshot of the bottom-left corner of the design. The core rings surround the main core area and the power straps cross the entire chip.

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Figure 4 Floorplan with Power Rings and Straps