Using Real-Time System Design Methods

to Integrate SMPS Control Software

with Application Software

Avik Juneja, Alexander G. Dean and Subhashish Bhattacharya Dept. of Electrical and Computer Engineering

North Carolina State University

Raleigh, USA

ajuneja@ncsu.edu, agdean@ncsu.edu, sbhatta4@ncsu.edu

Abstract – A switch-mode power supply (SMPS) converts

power efficiently between different voltage levels, making power

optimizations through voltage scaling feasible. SMPS controllers

are generally dedicated hardware (analog/digital circuits,

microcontroller (MCU), digital signal processor (DSP)), and so are

expensive to add to very low cost embedded applications.

In this work, we show how to integrate SMPS control software

into the MCU running application software, which reduces system

cost while increasing the design space and flexibility for

developers. Real-time system design methods are employed to

ensure SMPS voltage regulation quality, while retaining the

original embedded application behavior. Our methods apply to a

wide range of software task schedulers, from simple interrupt-

based foreground/background systems to sophisticated

preemptive real-time kernels (RTOS). We demonstrate our

methods on a position-logging embedded system, with multiple

voltage domains controlled in software, resulting in power savings.

Keywords—SMPS, DVS, DPM, RTOS, DC-DC, Power Supply,

Embedded Systems, Firmware, Real-Time.

INTRODUCTION

Consider an embedded system consisting of an MCU and

peripherals as shown in Figure 1. The operating voltage ranges

of some sample components are depicted in Figure 2 with

vertical bars. One approach is to power all peripherals at 3.3 V,

as shown with the yellow horizontal line. However, we can save

significant power by lowering the operating voltages, as P α V2

for switching and resistive loads, and P α V for constant current

loads. For example, we can add two lower voltage domains

(1.7V (blue), 2.7V (green)) to power the peripherals to operate

at lower voltages.

Standard control approaches assume that the SMPS

controller is implemented with digital logic or on a processor

(MCU or DSP) entirely dedicated to that task [1] [2] [3] [4].

This additional hardware increases system cost and size.

We seek to reduce the cost of adding voltage domains by

controlling their buck converters in software in the same MCU

as the application software. To do this safely, we must ensure

that the control software runs without timing interference from

the application software. We use real-time (RT) system design

techniques to tackle this challenge. A preemptive task scheduler

and task priorities set by real-time design methods ensure

proper responsiveness of all tasks without missing deadlines.

This approach does not require allocation of dedicated CPU

time (such as time slicing). Our contribution is a practical

approach to integrate the SMPS control software into the

application MCU while guaranteeing proper timing and

operation of the SMPS control loops.

Figure 1: An embedded system with common peripherals

Figure 2: Operating voltage ranges of peripherals

A. Scope of Applicability

The embedded application design space and workloads

cover a wide spectrum of power and performance. Depending

on the platform used and the computational demands of the

application, the CPU utilization can vary anywhere from below

This work was supported in part by NSF CSR award 1116850. 978-1-4673-7151-3/15/$31.00 ©2015 IEEE

1% to as high has 100%. Similarly, the power variation between

a performance-limited low-cost MCU and a high end floating

point MCU with many peripherals can be quite significant,

from as low as a few milliwatts to hundreds of watts,

respectively. There is more variability in power vs.

performance on these platforms for wide range of workloads,

depending on software and hardware architecture, and

optimizations, such as fixed point math, direct memory access

(DMA), specialized functional units, ADC operation modes,

variable scaling and optimizations, code reuse, modularity etc.

Our methods provide a means to design and tailor an embedded

application for maximum performance benefits with reduced

power and span a wide range of applications, target hardware

and software. We demonstrate a proof of concept using a

sample embedded application with a variety of peripherals.

Our methods offer significant benefits to system designers,

even when using an unexceptional buck converter without

sophisticated circuit or control features. Performance can be

improved further through synchronous switching (for

efficiency) or feed-forward control (for response) and other

methods. We leave these for future work.

B. Paper Overview

Section II introduces our design methods. Section III presents our experimental platform’s hardware and software. Section IV presents experiments and analysis to evaluate various aspects of the resulting system. Section V summarizes our contributions and presents future directions. Section VI discusses related work.

DESIGN METHODS

A. Overview

Figure 3. Buck converter response to step increase in load current

Our design method is based on understanding the voltage and time characteristics of a buck converter’s response to the worst-case combined load transient, shown in Figure 3. We evaluate the impact of delaying the execution of the control loop software, temporarily increasing the controller delay td. We use real-time system design methods to determine the maximum interference timing interference (delay) possible from the application software. We then put these together to determine the impact of integrating the controller with the application software. We first present an overview of the proposed approach.

Evaluate all of the loads on each supply rail to determine the maximum loading and unloading transients imposed by the rail’s peripherals.

Design a buck converter using standard techniques, ensuring that Vout will not fall below the minimum acceptable voltage when using optimal control.

Design a discrete time control law (compensator) for the buck converter.

Use embedded and real-time system design methods to integrate the control loops into the application software. Leverage hardware peripherals for control operations, providing isolation from application software. Employ preemptive, prioritized task scheduling with interrupt service routines (ISRs).

Use a schedulability test to verify all tasks and ISRs will meet their deadlines.

Use real-time worst-case response time analysis methods to determine the maximum blocking time tb based on duration of other ISRs and other non-interruptible code sections in the application.

Derive an equation ΔVpeak(t) to determine maximum output voltage transient, allowing analysis of impact of delayed execution of the control loop.

Evaluate ΔVpeak(tb) to determine if voltage transient is acceptable. If so, design is complete. If not, adjust design, modify code to reduce tb, change scheduling approach. Repeat analysis.

B. Detailed Discussion

We now examine each of these steps in detail.

1. Evaluate Load Current Transients per Supply Rail Each supply rail r powers peripherals in the set P(r).

Determine the maximum worst-case loading transient for each supply rail r based on peripheral p.

∆𝐼𝑚𝑎𝑥(𝑟) = ∑ ∆𝐼𝑙𝑜𝑎𝑑𝑖𝑛𝑔,𝑚𝑎𝑥(𝑝)

∀𝑝∈𝑃(𝑟)

(1)

2. Design Buck Converter Design a buck converter using standard techniques [5]. The

buck converter shown in Figure 6 is targeted due to its ubiquity, simplicity, low cost and extensive analysis [6] [7] [8].

Select the components and operating parameters such that the maximum combined load transients ΔImax(r) for supply rail r will not cause Vout to fall below the minimum acceptable voltage when using optimal control. A buck converter’s output voltage response to a step change in load current has been characterized [6] [8]:

∆𝑉𝑜𝑢𝑡(𝑡) = −𝑟𝐶∆𝐼𝑜𝑢𝑡 − 𝑡∆𝐼𝑜𝑢𝑡𝐶𝑜𝑢𝑡

+ (𝑡 − 𝑡𝑑)𝑚𝑟𝐶 + (𝑡 − 𝑡𝑑)2𝑚

2𝐶𝑜𝑢𝑡 (2)

Here, m is the slope VL/L of the inductor current. For loading transients VL is (Vin - Vout); for unloading transients it is –Vout. The delay from the load transient to the PWM duty cycle update is represented as td.

The time of the peak output voltage deviation occurs after ¼ of a period of the circuit’s natural frequency [7]. Adding in the ripple voltage may shift this time by up to one switching period:

𝑇𝑝𝑒𝑎𝑘,𝑂𝐿 =𝜋√𝐿𝐶𝑜𝑢𝑡

2 ± 𝑇𝑠𝑤 (3)

This time can be treated as the worst case (smallest) scenario, which will increase with inclusion of circuit parasitic values and resistances.

The size of the inductor relative to the critical inductance value (equation (4)) determines whether the output voltage will rise immediately or after an additional delay [6].

𝐿𝑐𝑟𝑖𝑡 =𝑟𝐶𝐶𝑂𝑢𝑡(𝑉𝑖𝑛 − 𝑉𝑜𝑢𝑡)

∆𝐼𝑜𝑢𝑡 (4)

A smaller inductance (L<Lcrit) results in recovery of voltage immediately after td.

𝑇𝑝𝑒𝑎𝑘,𝐶𝐿 = 𝑡𝑑 (5)

Equation (2) then reduces to:

∆𝑉𝑜𝑢𝑡 = −𝑟𝐶∆𝐼𝑜𝑢𝑡 − 𝑡∆𝐼𝑜𝑢𝑡𝐶𝑜𝑢𝑡

(6)

At that time, the output voltage reaches:

∆𝑉𝑝𝑒𝑎𝑘,𝐶𝐿 = −∆𝐼𝑜𝑢𝑡 (𝑡𝑑𝐶𝑜𝑢𝑡

+ 𝑟𝐶) (7)

However, with a larger inductance (L>Lcrit) the peak output voltage deviation occurs later:

𝑇𝑝𝑒𝑎𝑘,𝐶𝐿 = max 𝑡𝑑 , 𝑡𝑑 +𝛥𝐼𝑜𝑢𝑡𝐿

𝑉𝐿− 𝑟𝐶𝐶𝑜𝑢𝑡

(8)

It is straightforward to apply this time to equation (2) to find ΔVpeak,CL for the closed loop case with a large inductor.

3. Design Buck Converter Controller We next derive the characteristic equation of the buck

converter using state space analysis [5] [9]. This determines open-loop performance parameters such as rise time, settling time, over/undershoot and steady state error. The characteristic equation of the buck converter for a constant current load is approximately:

𝑃 = 1 + (𝑅𝑙𝑜𝑠𝑠𝐶 + 𝑟𝐶𝐶)𝑠 + 𝐿𝐶𝑠2 (9)

This includes the effective parasitic resistances for the non-synchronous buck converter (Rloss = rL + rds*D + rf*(1-D)).

Figure 4: Block diagram of the closed loop system

A mathematical closed loop model was derived, as shown in Figure 4, representing the power stage (converter) and the sampling & control stage (MCU).

The compensator transfer function, D(z), is implemented as a discrete time difference equation using direct control law for simplicity [10]:

𝑑[𝑛] = 𝑑[𝑛 − 1] + 0.2033𝑒[𝑛] − 0.175𝑒[𝑛 − 1]; (10)

4. Implement SMPS Control Next we use embedded and real-time system design methods

to implement the control system for each SMPS.

First, design the system using the MCU’s hardware peripherals to isolate SMPS control operations from software scheduling and task blocking as much as possible. Use hardware timers to trigger the ADC sampling (at fc) and the PWM signal generation (at fsw). Use hardware event signals to transfer data or control signals. Use ADC data update features or use direct memory access to transfer ADC results if possible to eliminate the need for ISRs to perform these operations.

Second, employ a preemptive task scheduling approach and leverage ISRs [11] [12] [13]. The task scheduling approach will dictate how to prioritize task execution at run time, eliminating the need for any time-slicing. Any control loop processing which remains after leveraging hardware peripherals should be executed in a high-priority ISR to minimize blocking. However, it is still vulnerable to blocking when higher-priority ISRs execute, if ISRs are not interruptible, or when ISRs are disabled for data atomicity or other reasons.

5. Verify Task Set Schedulability The next step is to verify that the software task set is

schedulable for a given scheduling approach and priority assignment. This means that no task will ever miss its deadline. This analysis starts by describing each software task and ISR in terms of its worst-case execution time, deadline, maximum release rate, and durations of critical sections (e.g. when interrupts or task switching may be disabled). Suitable tests are well-documented, including both exact response-time tests and inexact but safe utilization-bound tests [14] [15] [16] [17].

6. Find Maximum Blocking Time for SMPS Control Tasks The SMPS control tasks will have been assigned high

priorities. Use well-known methods to determine the maximum blocking time tb for each SMPS control task [14] [17] [18]. These methods include blocking from interference from any higher priority tasks and non-preemptable code segments.

7. Derive Equation for ΔVpeak(tbq)

Figure 5. Impact of blocking time on output voltage

Next we extend the load transient response analysis to consider the blocking time and discrete-time nature of the digital control system. Figure 5 shows the impact of blocking the

Vref[n] e[n] Vo(t)

G(s)

TI - DSP

d(t)

1 −

Kpwm e-sTproc Gvd(s) D(z)

e-sTadc Kadc

control loop execution for blocking times tb1 and tb2. The first time tb1 is short enough that the control still has time to reduce ΔVpeak,CL compared with the open-loop case ΔVpeak,OL. The second time tb2 is long enough that the control responds too late and ΔVpeak,CL = ΔVpeak,OL.

The PWM output duty cycle is updated at a rate of fsw, so the possible time delays tbq are quantized as integer multiples of a switching period Tsw. We assume a one-period delay between ADC sampling and PWM duty cycle updating, but this delay could be reduced in future work.

𝒕𝑏𝑞 = 𝑇𝑠𝑤 ⌈𝑡𝑏𝑇𝑠𝑤

+ 1⌉ (11)

We can now determine the maximum voltage impact from blocking for time duration tbq. There are two cases to consider. If tbq < Tpeak,OL, then control system will have an effect on the peak output voltage:

∆𝑉𝑝𝑒𝑎𝑘,𝐶𝐿 = −∆𝐼𝑜𝑢𝑡 (𝑡𝑏𝑞

𝐶𝑜𝑢𝑡+ 𝑟𝐶) (12)

If tbq > Tpeak,OL then the control system’s response will occur after the open-loop peak and will not affect its magnitude:

∆𝑉𝑝𝑒𝑎𝑘,𝑂𝐿 = −∆𝐼𝑜𝑢𝑡 (√𝐿

𝐶𝑜𝑢𝑡) (13)

8. Evaluate Resulting Voltage Transient If output voltage transient ΔVpeak is acceptable, then this

portion of the design process is complete. If not, the design may be adjusted in various ways.

a) Software Changes

Increasing the control loop frequency will reduce td but will also proportionately increase the computational loading on the MCU. Reducing the blocking time will allow the control system to respond fast enough to reduce the peak voltage transient. This may involve raising the SMPS ISR priority, deferring work from within other ISRs to occur in tasks with lower priorities, making long ISRs interruptible, reducing critical section durations, not disabling all interrupts within critical sections, or adding a priority ceiling protocol.

b) Capacitor Changes

The “brute-force” approach is to increase the size of the output capacitor [7]. Increasing Cout by a factor of x will reduce the slope of the output voltage by a factor of 1 𝑥⁄ . It will delay

the open-loop voltage peak by a factor of √𝑥. Finally, it will

reduce the peak voltage by a factor of 1 √𝑥⁄ . However, this increases cost, volume and board area.

Using a capacitor with a lower ESR, rC. will reduce the ∆𝑉𝑝𝑒𝑎𝑘,𝐶𝐿 but also increase the 𝑇𝑝𝑒𝑎𝑘,𝐶𝐿 . For example, a tantalum

capacitor has a much bigger ESR than the ceramic. However, it will also reduce the critical inductance, making the system more likely to have a slower response even with optimal closed-loop control.

c) Inductor Changes

Increasing the inductance increases the delay until the open-loop peak voltage. For a closed-loop system with an

inductor larger than the critical inductance, the larger inductor will increase the delay between the duty cycle update and the ramp-up of the output voltage. In both cases the magnitude of that peak voltage increases.

Reducing the inductance raises the amount of ripple voltage, unless the switching period is also decreased proportionally (which will increase power losses). The maximum inductor current will also increase, potentially raising inductor costs. This may also lead the converter to operate in discontinuous conduction mode, further complicating control and converter design.

d) Operating Voltage Setpoint

Raising the operating voltage will allow the system to tolerate

a larger ΔVpeak. However, this will also raise the system power

dissipation.

SYSTEM DESCRIPTION

We demonstrate our methods on a prototype position-

logging embedded system, shown in Figure 1. This features a

GPS receiver, WiFi interface, LCD and microSD card. The

system has three voltage domains (3.3 V, 2.7 V, 1.7 V) as

shown in Figure 2, each powered by a software-controlled buck

converter with 5V input, fsw = 50 kHz and fc = 50 kHz. The

application MCU is a 16-bit Renesas RL78/G14 running at 32

MHz with 24 KB of RAM and 256 KB of flash ROM [19] [20].

It can operate from 1.6 to 5.5 V. As with many other

inexpensive embedded MCUs, there is no hardware support for

floating point math. Each of the power supply rails is driven by

a simple non-synchronous buck converter, shown in Figure 6.

The SMPS control software was implemented in the RL78

MCU using a standard control law (eqn. (10)) derived using

digital control theory for a PI compensator [1] [2] [5] [8] [21]

[22].

Figure 6: Circuit diagram and prototype buck converters

The overall control sequence is outlined in Figure 7 and is

implemented with both hardware peripherals and software (in

ADC_ISR). The control task was implemented in a high-

priority ISR. We performed various optimizations to reduce the

computation time. Major benefits came from using fixed point

math, and eliminating many ISRs by using the Event Link

Controller to allow peripherals to trigger each other. We

reduced the computation time tcontrol for one SMPS down from

over 50 µs down to only 2.24 µs with the MCU operating at

32MHz. For three domains the total computation time is

5.56µs. Thus, running these domains consumes only 27.8% of

the MCU’s time, leaving most of it free for application

processing.

Figure 7: SMPS control software sequence diagram

EXPERIMENTAL RESULTS

A. System Operation and Voltage Regulation

Figure 8: Blue: Transients on system 3.3V rail from Wifi activity. Red:

Current drawn by Wifi module, measured as voltage across 1Ω series

resistor

We evaluated the performance of the entire system, which

was fully functional. First we examined the supply rails to

verify proper voltage regulation. As shown in Figure 8 and

Figure 9, the buck converter controllers operate correctly,

regulating the output voltage despite large load current

transients from the WiFi module and SD cards, respectively.

The voltage deviations are acceptable.

Figure 9: Blue: Transients on system 2.7V rail as data is written to SD

card. Red: Current drawn by SD card, measured as voltage across 4.4

Ω series resistor

B. Timing Interference Analysis

We measured the impact of timing interference which

delays (blocks) the execution of the SMPS control ISR,

delaying the response to a load transient. Figure 10 shows the

SMPS response (with optimal control) to a step load transient

with increasing blocking times.

Figure 10: Effects on control task blocking on voltage regulation of

SMPS

Figure 11 shows the impact of different sampling

approaches on the dependence of ΔVpeak on tb. Normal sampling

occurs at the negative edge of the PWM cycle. For just-in-time

sampling (JIT), the ADC is sampled as late as possible to be

able to still reload the PWM counter in the current cycle.

Figure 11: Voltage deviation under normal and JIT sampling technique

for various blocking times

C. Energy Efficiency Analysis

Burst mode operation was added to improve buck converter

efficiency by reducing switching losses when operating under

very low load conditions.

Figure 12 shows that when the duty cycle falls below a

threshold, the controller disables SMPS switching operations so

the load circuit is powered by the output capacitor. When the

output voltage falls below a threshold, the control software

enables SMPS switching operartions, allowing the sytem to

charge the output capacitor again.

0

50

100

150

200

0 20 40 60 80 100

∆V

pe

ak_C

L (m

V)

tb (µs)

Normal Sample JIT Sample

Figure 12: Burst mode implementation of SMPS under very low duty

cycle (small loads)

Figure 13 shows how converter efficiency improves

significantly at lower load currents.

Figure 13: Efficiency improvement due to burst mode operation in

light load condition

Figure 14: Increased efficiency of SMPS at small loads using burst

mode implementation

The overall efficiency curve appears in Figure 14 and Figure

15. If better efficiency is needed at higher loads, the converter

can be changed to a synchronous buck converter to reduce the

conductive losses.

Figure 15: Buck converter efficiency under various load conditions

D. Output Capacitor Selection

We evaluated the transient response of the buck converter using

both ceramic and tantalum output capacitors, as shown in

Figure 16. Ceramic capacitors are more expensive but have a

lower ESR which reduces ripple voltage significantly.

However, this reduces the critical inductance, leading to a

slower response to transients even with optimal control [7] [8].

Figure 16: SMPS response to load transient with different output

capacitor technologies

E. System Energy Use

Three 1F ultracapacitors were employed to power the

system. The total energy available is constant for all test cases.

The ultracapacitors were charged for a fixed amount of time to

voltage Vinit and then allowed to discharge by powering the

system. The amount of time, tdischarge, taken by the system to

drop the voltage of the ultracapacitors to Vfinal determines the

rate of energy consumption or the average power, Pavg

consumed by the system, given as:

𝑃𝑎𝑣𝑔 =𝐸𝑡𝑜𝑡𝑎𝑙

𝑡𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒=1

2𝐶𝑉𝑖𝑛𝑖𝑡2 − 𝑉𝑓𝑖𝑛𝑎𝑙

2

𝑡𝑑𝑖𝑠𝑐ℎ𝑎𝑟𝑔𝑒 (14)

The average power reduction in various operating modes of

the embedded application is normalized and depicted in Figure

17 and Figure 18. It can be clearly seen that using an SMPS

with single voltage domain over a linear regulator results in

power savings of up to 59%. Using multiple domains results in

of power savings of 66%. When comparing the use of single vs.

multiple voltage rail SMPS design, up to 26% power savings

can be observed, as depicted in Figure 18. Although these

0.65

0.7

0.75

0.8

0.85

0.9

0 0.002 0.004 0.006 0.008 0.01 0.012

Load Current (A)

Efficiency @ 2.7V

Mr. Buck Burst Mode

0.7

0.8

0.9

1

0.001 0.01 0.1 1

Load Current (A)

Efficiency

V=2.1V V=2.7V V=3.3V

power gains are modest, they were achieved with three non-

synchronous buck converters with limited efficiency.

Converting them to synchronous converters would improve

efficiency significantly with negligible software impact.

Furthermore, load balancing on supply rails can significantly

improve the average power consumption in all modes of

operation. In the current system, most of the load is on 3.3V rail

(89.15%), resulting in little improvement of multi-rail over

single rail SMPS. Depending on low power applications, the

load can be distributed to 1.7V and 2.7V rails.

Figure 17: Comparison of average power between single SMPS vs.

multi-domain SMPS system

Figure 18: Average power of the three converter setups for various

operating modes

CONCLUSIONS AND FUTURE WORK

By using real-time system design methods to integrate

control software for an SMPS with the application software,

this work enables the SMPS designers as well the embedded

system design engineers to take advantage of a simple

switching power converter in exploiting it for either a tight

power management or loosen the control effort in order to

extract best CPU utilization for other tasks in hand. This

significantly empowers low cost system designers to extract

more efficiency with significant flexibility and scalability for

wide range of applications.

Due to the tight coupling of the hardware and software in

this work, there are limitations which need to be considered

during the design process. These include:

SMPS control software must be robust and isolated from

application software to avoid faults such as memory

overflow, peripheral misuse, etc.

Computational loading of the control software will lead

to application scheduling constraints.

Development time will be increased.

Sub-optimal load distribution may result in limited

energy savings.

Future work exists in various directions. Processor

computational loading can be reduced by leveraging additional

hardware peripherals (e.g. DMA controller), applying dead-

band control, and hardware-assisted feed-forward control.

Transient response can be improved using feed-forward

control. Cost and size can be reduced by increasing switching

frequency. Although this present work examines robustness of

the control software with respect to timing interference by the

application software, the SMPS controller’s peripherals and

memory space must also be protected from interference.

RELATED WORK

In the power supply design community, digital control of switching converters has been a very active field [1] [10] [21] [22] [23] [24]. The transient response has been investigated to identify critical relationships between circuit parameters [7] [25]. It is especially important for voltage regulator modules which must handle the large transients of power-hungry high-performance processors [6] [8].

There have been many investigations into the software issues with controlling power converters using MCUs and DSPs [2] [3] [4]. In fact, many MCU and DSP vendors provide working reference designs for such applications. The real-time design community has investigated the implications of jitter on digital controllers for other applications and suggested various solutions [14] [26] [27].

Designers of high-performance processors (e.g. personal computers and cellphones) have long relied on buck converters for dynamic voltage scaling. There are many papers which concentrate on power management at the microprocessor level [28] [29] [30] [31] [32]. These discuss various techniques to avoid voltage fluctuation by use of sense or prediction techniques, such as application interactions, microprocessor architectural changes, hybrid multi-phase converters, etc.

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0%

20%

40%

60%

80%

100%

Operating Standalone Low Power Sleep

Relative Average Power

Buck-3.3V Buck-3.3/2.7/1.7

0%

20%

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Operating Standalone Low Power Sleep

Relative Average Power

Linear 3.3V Buck-3.3V Buck-3.3/2.7/1.7

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