UNIVERSITY OF NOTRE DAME

Origin of Coulomb Blockade Oscillations in Single-Electron Transistors

Fabricated with Granulated Cr/Cr2O3 Resistive Microstrips

Xiangning Luo, Alexei O. Orlov, and Gregory L. Snider

University of Notre Dame, Dept. of Electrical Engineering, Notre Dame, IN 46556

UNIVERSITY OF NOTRE DAME

Outline

Purpose: to understand single-electron devices with resistive microstrips instead of tunnel junctionsCan single-electron transistor be built using only resistors with no tunnel junctions? SETs with metal islands and resistive microstrips are fabricated and tested. Coulomb blockade oscillations are observed, but what is the origin of these oscillations?Possible mechanisms for Coulomb blockade oscillations are investigated and discussed

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Fabrication of CrOx SETs by Two Steps of E-beam Lithography and Deposition

The top view of two versions of the single-electron transistor with CrOx barriers The inset is the cross section at the overlap area of Au layer and CrOx layer. First layer: Ti/Au 2nm/10 nm in thickness Second layer: Cr (8 nm-10 nm or 40 nm) was evaporated in the oxygen ambient. CrOx strips were 0.375-2 m long, 70 nm wide, and 6-10 nm thick

Gate

Source

DrainIsland

Cr

Cr

SiO2

Cr Au

Gate

Drain

Island

Cr CrSource

Cr

Au

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(a)

Different Microstrip Designs

(a) Type #1: CrOx layer consists of narrow lines (~70 nm) only.

(b) Type #2: large tabs (wider than 300nm in two dimensions) on both ends cover all of the steps where the two layers of metal overlap.

(c) Type #3: large tabs only cover the steps of source and drain and no tabs appear on the island.

Source Drain

Island

(b) Source Drain

Island

(c) Source Drain

Island

Schematic view of three types of pattern design

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(a)

Different Contact Designs

(a) Type #1: CrOx layer consists of narrow lines (~70 nm) only.

(b) Type #2: large tabs (wider than 300nm in two dimensions) on both ends cover all of the steps where the two layers of metal overlap.

(c) Type #3: large tabs only cover the steps of source and drain and no tabs appear on the island.

Source Drain

(b) Source Drain

Island

(c) Source Drain

Island

Schematic view of three types of pattern design

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R<2k /□, weak temperature dependence

2k /□<R<7k /□, significant nonlinearities and a temperature dependence characteristic of variable range hopping were observed; however, none of the devices exhibited Coulomb blockade oscillations.

R>7k /□, all of the devices were frozen out, showing no conductivity below 5 K.

Measurements on type #1 (tabs everywhere) (SETs

.

Type #2 Over 95% devices showed conductance at room temperature. The CrOx films were very uniform and lasted for a long time exposed to air. In the low temperature measurement (300mK)

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Measurements on type #3 SETs

Resistance range R<100k 100k <R<200k 200k <R<1M R>1M

Total number of devices 12 9 5 4

Number of devices showed CBO 0 5 3 3

Yield 0% 56% 60% 75%

Coulomb blockade oscillations were only observed when the resistance of devices was greater than 100 k . Devices with higher resistance were more likely to show Coulomb blockade oscillations

The yield vs. resistance of type #2 devices

Coulomb blockade oscillations were only observed in this type of SETs

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Low Temperature Measurements Type#?

(a) I-V curves of an SET in open state and blocked state. (b) I-Vg modulation curve of the same SET of (a) measured at 300 mK showed deep modulation by the gate.

(a) (b)

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Low Temperature Measurements

Charging diagram of an SET measured at 300 mK showed a charging energy of ~ 0.4 meV.

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AFM Images

(b)

Au island

CrOx wireGate

with tabsAu island

CrOx wire

Large tab

(a)

(a) AFM image of a CrOx wire deposited on the edge of Au island.(b) The AFM image of an abnormal SET revealed that only two edges were covered

by large tabs in the sample with a pattern shift.

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Step Edge Junctions or Resitive microstrips with “right” resistance and capacitance?

Top view (a) and cross section (b) of step edge junction.The areas where step edge junctions formed are marked by circles.

SiO2

Cr

Au islandAu island

Cr

(a) (b)

Cr

Au

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AFM Image

Gate

GateAu layer

Island

The abnormal devices which had a very rough surface of CrOx films.

CrOx

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Multiple Frequencies in I-Vg Modulation Curves

Multiple frequencies in I-Vg modulation curve of abnormal devices with a very rough CrOx surface.

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SETs with Thicker CrOx Wires

SETs with thicker (~ 40 nm) CrOx wires were also fabricated using pattern design type #3 with different widths of island (80 nm and 500 nm).

The room temperature sheet resistance of the devices showing significant nonlinearity in I-V curves at 300 mK is around 5 kΩ/□, which is about the same as our previous SETs with thinner (8-10nm) CrOx wires.

Among those devices having significant nonlinearity, about 95% (21 out of 22) exhibited Coulomb blockade oscillations, which is much higher than that of SETs with thinner CrOx wires.

Tunnel barriers other than step edge junction formed at the interface of Au island and CrOx providing small enough capacitance and resistance lager than RQ to fulfilled the two requirements of Coulomb blockade oscillations

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Low Temperature Measurements

(a) I-Vg modulation curves of an SET with 40 nm thick CrOx strips showed deep modulation by the gate. (b) Charging diagram of the same SET of (a) measured at 12 mK

(b)(a)

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SETs with Pt as the First Layer

SETs with Pt instead of Au as the first layer and thicker (~ 40 nm) CrOx as the second layer were also fabricated using pattern design type #3.

Most of the devices showed significant nonlinearity in I-V curves at 300 mK.

None of these devices showed any gate dependence.

More experiments are needed.

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Conclusions• Two basic requirements to observe single electron tunneling

effects:

– the total capacitance of the island, C, must be small enough that the charging energy EC = e2/2C >> kBT.

– the resistance of the tunnel barriers, RT > RQ = 25.8 k to suppress quantum charge fluctuations.

• Resistive microstrip itself does not provide localization of electrons in the island - first requirement may not be fulfilled.

• Two possible explanations:

– Step edge “break junctions” with low C are formed at the connecting interface between CrOx wires and Au wires

– Microstrips with small overlapping area and high resistance may satisfy both requirements