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UNIVERSITY OF CALIFORNIA

SANTA BARBARA

High-Power, High-Bandwidth, High-Temperature Long-

Wavelength Vertical-Cavity Surface- Emitting Lasers

A dissertation submitted in partial satisfaction of the

requirements for the degree of

Doctor of Philosophy

in

Electrical and Computer Engineering

by

Manish Mehta

Committee in charge:

Professor John E. Bowers, Chair

Professor Larry A. Coldren

Professor Art C. Gossard

Dr. Vijay Jayaraman

June 2006

The dissertation of Manish Mehta is approved:

____________________________________________________ Professor Larry A. Coldren

____________________________________________________ Professor Arthur C. Gossard

____________________________________________________ Dr. Vijay Jayaraman

____________________________________________________ Professor John E. Bowers, Chair

High-Power, High-Bandwidth, High-Temperature Long-Wavelength Vertical-

Cavity Surface- Emitting Lasers

Copyright 2006

by

Manish Mehta

Acknowledgements

One student’s Ph.D dissertation must be the result of encouragement, assistance, and

patience on the parts of countless individuals. This is even more pertinent when the

student begins a LW-VCSEL project without the slightest clue of the definition of a

photon.

I owe a huge debt of gratitude to my advisor, Professor John Bowers. His vast

knowledge of all things relevant to science and business provided me with an endless

pot of insight. But more importantly, his creativity is contagious and all of his

students are better off for it. He also has a house in Keystone.

In addition to Dr. Bowers, I would like to thank the other members of my

dissertation committee. Dr. Vijay Jayaraman, my mentor through the first year of the

project and the genius behind the wafer-bonded TJ intra-cavity VCSEL, taught me

how to approach optoelectronic device design from an intuitive perspective. He was

always available for technical help and discussion throughout the PhD process.

Professor Art Gossard provided valuable insight into TJ and active region design and

Professor Larry Coldren’s wealth of knowledge about semiconductor lasers was

invaluable to this research.

I would also like to thank all my colleagues at Agilent Laboratories. Steve

Lester, Jeff Miller, Franciose Mertz, Dan Mars, Dave Bour, David Lin, Kent Carey,

Waguih Ishak and my supervisor and mentor, Virginia Robbins provided me with the

facilities and freedom to pursue any research direction I see fit. And they supervised

ii

and collaborated with such grace in the midst of learning that their group was to be

shut down.

None of the device fabrication would have been possible without the UCSB

nanofabrication facility staff. Jack Whaley, Bob Hill, Brian Thibeault, Don Freeborn,

Luis Zuzunaga, and Mike Silva keep that place running efficiently in spite of the

incompetence that infests many cleanroom users.

Device development would also not have been possible without the several

growers associated with the LW-VCSEL project – Here’s to you Andrew Jackson,

Yae Okuno, Shaomin Wu, James Raring, Yi-Jen Chiu and Tecwell International.

Jon Geske and Staffan Bjorlin should probably be first authors of this

dissertation. But since that is not an option, a hearty thank you will have to suffice.

Whether it was snowboarding or surfing lessons, break dancing, the Press Room, or

the less important tutorials on optoelectronics, you guys taught me so much. And

your treatment of me is also proof that you often have to stick 49 daggers in a person

before he (that would be me) will rise back up and conquer. Garrett is my antithesis,

which makes him a quality researcher. Garrett, if I am Arnold Schwarzenegger, you

are my Danny Devito.

I would also like thank the rest of the members of Bowers’ group during my

tenure at UCSB – Gan, Hubert, Donato, Daniel, Maura, Kathy, Yi-Jen, Yae,

Shaomin, Qi, Emily, Toshio, Satoshi, Alex, Brian, Hyundai, Jae-Hong, Anand and

Shane. One last time – who do you hate the most?

iii

What would I have done without the assistance of Sue, Michelle, Hillary, Kate

and Jasmine. For one, I would have never received a reimbursement, and for that

alone – all of you occupy my wall of heroes.

I’d also like to thank my friends, classmates and collaborators from the

Coldren and Blumenthal groups: Roop, Chad, Vik, Anna, Matt S., James, Jill, Dave

B., and Rintaro. Danny Feezell deserves special thanks for all the insightful LW-

VCSEL discussions and for being a Twindian (stay tuned).

The inhabitants of Orange deserve mad props for having to hear one too many

knock-knock jokes. Qi, Chad and Emily are probably the only three people who

understand why I will never have a wife. I’d also like to give a shout-out to

Sportscenter for being the ultimate male bonding experience. And to Max, Eric,

Anders and Staffan - I will try my dearest to continue the legacy that is the OZONE

in my 10 last days there.

Krishna, you suck, but the Twindians will always hold a special place in my

heart. Pigs, rivers, holes, and rabbits’ souls will always remind me of Krishna,

Danny, and Alex. Oh what a band we could have been.

Texas folk deserve a special place on this list as they were privy to a much

more restrained and mature Manish. The Four Horsemen, D-E Squad and the Village

Idiot Posse – I love all of you! Samir and Vik – you are both dweebs and both of you

need a haircut.

iv

Janvi and Anjali had to put up with me during my worst times and deserve a

trophy for that alone. If you have ever found me annoying, you have no idea what

these girls have had to go through.

Finally, I could have never summoned the will to finish this thesis without the

care and love of my family - Mom, Dad and Megha. Thanks for everything!!

v

CURRICULUM VITAE

Manish Mehta

May 2, 1979 Born Bethlehem, PA May 2001 B.S., Electrical and Computer Engineering University of Texas, Austin June 2004 M.S., Electrical and Computer Engineering University of California, Santa Barbara June 2006 Ph.D., Electrical and Computer Engineering University of California, Santa Barbara PUBLICATIONS

1. M. Mehta, D. Feezell, D. Buell, A. Jackson, L. Coldren, and J.E. Bowers, “Electrical Design Optimization of Single-Mode Tunnel Junction-Based Long-Wavelength VCSELs,” Journal of Quantum ElectronicsApplied Physics, To be published Summer 2006.

2. M. Mehta, E.S. Bjorlin, J.E. Bowers, “Calculated voltage characteristics

for tunnel junctions in double intra-cavity long-wavelength surface emitting lasers,” IEEE Proceedings of the 4th International Conference on Numerical Simulation of Optoelectronic Devices, pp. 51-52 August 2004, Santa Barbara, CA.

3. M. Mehta, V. Jayaraman, A. Jackson, S. Wu, Y. Okuno, J. Piprek, J. E.

Bowers, “Wafer-Bonded VCSELs with Tunnel Junctions,” SPIE Proceedings 5248-20, (ITCOM’03), pp. 140-147 September 2003, Orlando, FL.

4. M. Mehta, V. Jayaraman, A. W. Jackson, S. Wu, Y. Okuno, J. Piprek,

J. E. Bowers, “134°C Continuous-Wave Operation of a 1.33-µm Wafer-Bonded VCSEL,” Technical Digest of Conference on Lasers and Electro-Optics (CLEO’03), June 2003, Baltimore, MD.

vi

5. M. Mehta, V. Jayaraman, A. Jackson, S. Wu, Yae Okuno, J. Piprek, and J. E. Bowers, “High Power 1320nm Wafer-Bonded VCSELs,” Proceedings of 29th European Conference on Optical Communication (ECOC´03), September 2003, Rimini, Italy.

6. E. S. Björlin, J. Geske, M. Mehta, J. Piprek, J.E. Bowers,

”Temperature Dependence of the Relaxation Resonance Frequency of Long-Wavelength Vertical-Cavity Lasers,” IEEE Photonics Technology Letters, vol. 17, no. 5, pp. 944-946, May 2005.

7. V. Jayaraman, M. Mehta, A. W. Jackson, S. Wu, Y. Okuno, J. Piprek,

J. E. Bowers, “High-Power 1320-nm Wafer-Bonded VCSELs With Tunnel Junctions,” IEEE Photonics Technology Letters, vol. 15, no. 11, pp. 1495-1497, November 2003.

8. J. Piprek, M. Mehta, and V. Jayaraman, “Design and optimization of

high-performance 1.3µm VCSELs,” in Proc. SPIE, Physics and Simulation of Optoelectronic Devices XII, Photonics West 2004, vol. 5349-49, 2004, pp. 375-384.

9. J. Piprek, V. Jayaraman, M. Mehta, J.E. Bowers, “Balanced

optimization of 1.31 µm tunnel-junction VCSELs,” in Proceedings of the IEEE/LEOS 3rd International Conference on Numerical Simulation of Semiconductor Optoelectronic Devices, pp.45-6 2003, Piscataway, NJ, USA.

vii

Abstract

High-Power, High-Bandwidth, High-Temperature Long-Wavelength

Vertical-Cavity Surface- Emitting Lasers

Manish Mehta

Access, metro-area, and storage-area network technologies are undergoing a

remarkable transition from copper and cable-based to fiber-based architectures. In

order for fiber-based technologies to penetrate the lucrative market termed the ‘last

mile,’ the optoelectronic component must be simple and inexpensive to manufacture

and perform well over a wide range of rack temperature. Long-wavelength vertical-

cavity surface-emitting lasers operating between 1300 nm and 1600 nm present an

attractive solution for low-cost optical networks requiring un-cooled sources.

The development of long-wavelength vertical-cavity surface-emitting lasers

(LW-VCSELs) capable of transmitting at 10 Gbit/s has been met with significant

challenges in the last decade due primarily to low quality Distributed Bragg

Reflectors (DBR) in the InP material system and large performance degradation at

high temperature due to low gain active regions and carrier leakage out of the active

region. Recent advances by several groups demonstrate an evolving maturity in the

field, but a significant obstacle remains – high performance single mode device

operation at high temperatures over the entire O-band (1260 – 1360 nm).

viii

This thesis presents design principles intended to optimize the high

temperature characteristics of a LW-VCSEL structure and demonstrates the state-of-

the-art high temperature performance results for LW-VCSELs operating above 1300

nm. By incorporating a tunnel junction current aperture with GaAs-based DBRs, we

minimize the thermal impedance and optical loss in our devices and provide ourselves

with a solid foundation by which to design for maximum performance at high

temperature. We theoretically also analyze the effect of the room temperature gain

peak-cavity mode offset on output power, thermal roll-over, threshold current and

differential gain in order to maximize the relaxation resonance frequency of our

devices at high ambient temperatures.

Fabricated devices demonstrate greater than 2 mW single mode output power

at 20 °C, 1.5 mW single mode output power at 70 °C, 10 GHz 3-dB bandwidth at 20

°C, 6 GHz 3-dB bandwidth at 70 °C, and a maximum relaxation resonance peak of 8

GHz at 70 °C by incorporating a single wafer-bonded GaAs/AlGaAs DBR, a

AlInGaAs MQW active region, an InP/AlInAs TJ current aperture, and a TiO2/SiO2

output coupler.

ix

Contents

1 Introduction 1

1.1 Motivation 3

1.2 LW-VCSEL Challenges 3

1.3 Progress of LW-VCSEL Research 4

1.4 Wafer-Bonded VCSELs at UCSB 7

1.5 This Thesis 8

2 Active Region and DBR Design 15

2.1 Device Structure 15

2.1.1 1st and 2nd Generation Device Structure 16

2.1.2 3rd Generation Device Structure 18

2.2 Active Region Design 19

2.2.1 AlInGaAs vs. InGaAsP Quantum Well Active Regions 20

2.2.2 Quantum Well Number Optimization 22

2.2.3 Absorption Loss from Active Region 25

2.3 Distributed Bragg Reflector (DBR) Design 27

x

2.4 Summary and Conclusion 28

3 Electrical Device Design and Optimization 32

3.1 TJ Design and Experiment 34

3.2 Lateral Current Spreading Optimization 42

3.3 WKB Parameter and Tunneling Probability 44

3.4 Voltage Contributions for Other Sources 47

3.5 Complete Device Model and SM Device Optimization 51


4 High Speed Device Design and Optimization 58

4.1 Cavity Length Optimization 59

4.2 Rollover Current and Threshold Current Optimization 62

4.2.1 Threshold Current Analysis 63

4.2.2 Idiff Optimization 65

4.3 Differential Gain Optimization 74

4.4 Complete Model 78


5 Device Fabrication 86

5.1 Lithographic Aperture Definition and Re-Growth 86

5.2 Wafer-Bonding Process Development 89

5.2.1 Bonding Fixtures 90

5.2.2 Sample Preparation 92

5.2.3 Furnace Conditions 94

xi

5.2.4 Bond Procedure Variation between Generations 97

5.3 1st Generation Fabrication Techniques 98

5.3.1 Top DBR Mesa Definition and Ring Contact Deposition 99

5.3.2 Contact Layer Isolation and Self-Aligned Bottom Contacts 100

5.3.3 Passivation, Airbridge Definition, and Bond Pad Formation 101

5.4 2nd Generation Fabrication Techniques 102

5.4.1 Top DBR Definition 102

5.4.2 Active Region Mesa Definition 105

5.4.3 High Speed Bond Pads and Electrical Isolation 107


6 Device Results and Analysis 111

6.1 1st Generation VCSEL Results 111

6.1.1 Results for 8 µm Aperture Diameter Devices 113

6.1.2 Results for 5, 12, 16 and 20 µm Aperture Diameter Devices 119

6.1.3 Voltage Characteristics of 1st Generation Devices 123

6.2 2nd Generation VCSEL Results 124

6.2.1 2nd Generation Test Structure Characteristics 124

6.2.2 2nd Generation VCSEL Characteristics 128

6.3 3rd Generation VCSEL Results 131

6.3.1 CW L-I Results and Analysis 133

6.3.2 CW I-V Characteristics and Analysis 141

6.3.3 Small-Signal Modulation Results and Analysis 144

xii


7 Conclusion 158

7.1 Future Work 159

7.1.1 Voltage Performance 160

7.1.2 Transmission Measurements 161

7.1.3 Full 2” and 3” Wafer Bonding Processes 161

7.1.4 Array Fabrication Techniques 162

7.1.5 Aperture Technique Determination and Reliability 162

7.2 Conclusions 163

A Wafer Bonded, Double Intra-cavity Contacted VCSEL 165

Process Follower

xiii

Chapter 1

Introduction

As we enter the knowledge-based era, providing quality and cost-affordable

communication services to all facets of the community becomes one of the

telecommunication industry’s greatest challenges. Services such as distance learning

and user-defined content applications will require high amounts of upstream and

downstream bandwidth. Thus, recent years have seen a remarkable shift in the focus

of research and development within the telecommunications industry. Core backbone

network technologies predicated on long haul systems are now dense enough to meet

the current demand for bandwidth. In the process, metro-area and access networks

have become the primary transmission bottlenecks and thus much effort has been

placed over the last decade into transitioning from copper and cable based networks

to optical metro-area and access networks.

Basic optical networks employ a semiconductor laser source due to their

relatively low-cost and small form factor when compared to solid-state lasers. While

1

medium and long-distance networks (> 2 km) rely on in-plane Distributed Feedback

(DFB) lasers operating close to 1300 nm and 1550 nm, most short range high-speed

communication networks (< 500 m) employ Vertical-Cavity Surface-Emitting Lasers

(VCSELs) operating at 850 nm and 980 nm wavelengths due to their low-cost and

small form factor.

The physical differences between in-plane lasers and VCSELs are vast.

Figure 1.1 shows schematics for both (a) in-plane and (b) vertical cavity lasers. In-

plane lasers show light emission perpendicular to the direction of crystal growth and

tend to exhibit elliptical output beams. Also, the cavity geometry is generally defined

by lithography, holography, or cleaving. Optical feedback is provided by etched

facets, cleaved facets, gratings, etc. VCSELs, on the other hand, show light emission

normal to the plane of growth and generate circular output beams which allow for on-

chip wafer-scale testing and high fiber coupling efficiency respectively. The

emission wavelength of a VCSEL is generally determined by the growth and

Distributed Bragg Reflectors (DBRs) provide optical feedback.

2

(a) in-plane device illustration (b) vertical cavity device illustration Figure 1.1: Illustrations for (a) in-plane devices and (b) vertical cavity devices. Arrows indicate light emission from structure.

1.1 Motivation

Long-Wavelength VCSELs (LW-VCSELs) operating in the 1300 nm band offer a

low cost alternative to their in-plane counterparts in Ethernet and Fiber channel

modules, access and metro area network components and parallel optic and

interconnect applications. As mentioned previously, the benefits of VCSELs over in-

plane lasers arise from low power consumption, on-chip testing, low-cost array

fabrication and packaging, and high fiber coupling efficiency. Interest in the O-band

(1260 nm -1360 nm) arises from the dispersion and loss minima properties associated

with the wavelength range. Thus, the band is used for Passive Optical Network

(PON) upstream traffic and 10-Gigabit Ethernet traffic. As deployment of Fiber-to-

the-Premises (FTTP) becomes more commonplace, the market for long-wavelength

sources also increases dramatically. As is the case with any commodity market, the

lowest cost product will gain the largest share of the market.

1.2 LW-VCSEL Challenges

The inclusion of LW-VCSELs into communication networks has been met with

significant resistance stemming from the physical limitations of the GaAs and InP

material systems. Most challenges involve integrating InP-based active regions with

low loss apertures and high reflectivity mirrors.

3

The development of short-wavelength VCSELs (SW-VCSELs) operating at

850 nm and 980 nm was aided by several forces of nature. It was quickly determined

that the active regions and DBRs could be grown monolithically due to the high-gain

properties of GaAs and InGaAs multi quantum-well (MQW) active regions and the

high index contrast and high thermal conductivity of GaAs/AlGaAs DBRs.

Furthermore, the discovery of the lateral oxidation of high content Al layers allowed

for the development of low loss apertures which facilitate high power and high speed

device operation.

Unfortunately, monolithic integration of high gain InP based active regions

capable of operating over the entire long wavelength range (1200 nm -1600 nm) and

high quality DBRs proved to be a daunting task due to the small index contrast and

low thermal conductivity of InP DBRs. Moreover, gain roll-off at elevated

temperatures limits the high temperature performance of LW-VCSEL technology [1].

But several groups have made significant progress over the last decade in the

development of LW-VCSELs. This thesis presents another step in the long journey to

fabricating sources capable of driving mid-range communication networks.

1.3 Progress of LW-VCSEL Research

Recent advances by several groups incorporating GaAs-based active regions, buried

tunnel junctions, and metamorphic, wafer-bonded, and Sb-based Distributed Bragg

Reflectors (DBR) have resulted in improved device performance of LW-VCSELs.

All-epitaxial approaches using InGaAsN active regions on GaAs substrates

4

have yielded 4.2 mW room temperature output power and 10 Gbit/s transmission at

1293 nm but this technology has not yet performed well above 1300 nm [2, 3]. More

recently, groups have begun to incorporate Sb into the InGaAsN structures to push

the emission wavelength out to 1600 nm, but the technology has not yet resulted in

high quality device performance [4].

Research at UCSB focused on the development of an all-epitaxial approach

using an AlInGaAs quantum well (QW) active region and Sb-based DBRs grown on

an InP substrate demonstrate 1.6 mW continuous-wave (CW) single-mode (SM)

output power at room temperature, 3.125 Gbit/s transmission up to 60 °C, and greater

than 60% differential efficiency at 1300 nm [5, 6]. The same platform technology

operating at 1550 nm achieved close to 1 mW SM output power at RT and a

maximum operating temperature of 88 °C [7].

The first buried aperture approach was conceived by Amann, et al. at the

Walter Schottky Institute. The approach integrates an AlInGaAs active region, a

buried InGaAs TJ current aperture, and a dielectric mirror to achieve 2.5 mW SM

output power at RT and device operation up to 90 °C [8, 9]. Due to the absorbing

nature of the InGaAs TJ for 1300 nm applications, this solution is only viable for

1550 nm applications. The work of this thesis incorporates many of the fundamental

ideas presented by Dr. Amann and his colleagues.

The pre-eminent results covering a wide range of temperature and capable of

being fabricated over the entire O-band (1260 nm – 1360 nm) have utilized at least

one wafer-bonded or metamorphic GaAs-based DBR in conjunction with tunnel

5

junction (TJ) current apertures and AlInGaAs QW active regions. The alternating

GaAs/AlxGa1-xAs layers used in the DBR exhibit high index contrast and high

thermal conductivity. Both characteristics aid the high temperature performance of

LW-VCSELs. The incorporation of two wafer-bonded GaAs/AlGaAs DBRs on an

AlInGaAs QW active region has resulted in 1.2 mW single-mode (SM) output power

between 20 °C and 80 °C and 3.125 Gb/s transmission capability up to 70 °C [10].

Research integrating one metamorphic GaAs/AlAs DBR and one dielectric DBR has

resulted in 2 mW and 0.9 mW SM output power at 20 °C and 70 °C respectively and

close to 10 Gb/s error free transmission over 10 km [11]. Table 1.1 summarizes the

pre-eminent long-wavelength VCSEL results mentioned above.

Group Amann E2O Seiko Beam Express Agilent Coldren

(UCSB) This

Work

λ (nm) 1550 1315 1262 1325 1298 1305 1320

Max Power

SM, CW (mW)

2.5 2.0 - 2.5 1.6 0.9 2.5

Max Power MM, CW

(mW)

7.3 9.0 4.2 - 2.5 2.2 -

Ith, CW 1.2 1.2 5.1 3.0 1.0 1.7 1.8

Tmax, CW 90 119 - 100 85 90 134

Substrate InP InP GaAs InP GaAs InP GaAs

6

Aperture Buried TJ

Buried TJ Oxide Buried

TJ Etched

TJ Etched TJ

Buried and

Etched TJ

DBRs AlInGaAs/

AlInAs, dielectric

GaAs/ AlGaAs, dielectric

GaAs/ AlGaAs

GaAs/ AlGaAs InP/air AlGaAsSb/

AlGaAsSb

GaAs/ AlGaAs, dielectric

Table 1.1: Summary of current long wavelength VCSEL results.

1.4 Wafer-Bonded VCSELs at UCSB

This thesis is the tenth in a series of wafer-bonded vertical cavity research projects

performed under the supervision of Dr. Bowers at UCSB. Each of the previous

projects left important and lasting contributions which helped pave the way for this

work.

We choose to employ wafer bonding to reap the benefits of a high gain InP-

based active region and high quality GaAs/AlGaAs DBRs. The first bonded VCSEL

was developed by Dudley et al. and resulted in a record low pulsed threshold current

of 8 mA [12]. Dubravko Babic then reported the first electrically pumped,

continuous-wave, room temperature operation of a LW-VCSEL using a double-fused

approach [13].

Near Margalit proceeded to incorporate a lateral oxide aperture within a

bonded device, facilitated by the bond process. With the reduction in loss, he

demonstrated CW operation up to 66 °C [14]. Alexis Black continued the progress of

bonded LW-VCSELs during her tenure at UCSB and showed record low threshold

currents of 0.8 mA, CW performance up to 74 °C, and 7 GHz small signal

7

modulation bandwidth [15]. Adil Karim then used super-lattice etching to develop

wave division multiplexing (WDM) arrays at 1.55 µm and showed record CW

operation up to 105 °C [16].

Two students during their tenure at UCSB have developed novel optically

pumped VCSEL structures. Yae Okuno developed wafer bonded VCSEL structures

that include polarization control [17]. Jonathan Geske incorporated lateral

heterogeneous integration and fully oxidized DBRs to fabricate course-wavelength

division multiplexed (CWDM) VCSEL arrays spanning 1470 nm to 1610 nm and

capable of spanning the entire long-wavelength regime [18]. Both Staffan Bjorlin

and Garrett Cole have published dissertations on the design and fabrication of

Vertical-Cavity Semiconductor Optical Amplifers (VCSOAs) incorporating InP-

based active regions and GaAs/AlGaAs DBRs [19, 20].

1.5 This Thesis

The use of LW-VCSELs as a low-cost, un-cooled solution to network capacity

challenges demands high performance at high ambient temperatures. While the

previously mentioned results show significant progress in LW-VCSEL technology, a

key obstacle remains — demonstration of 10 Gb/s operation at elevated temperatures

over the entire O-band.

The work presented in this dissertation presents design principles and

performance analysis of LW-VCSELs integrating AlInGaAs QW active regions with

8

at least one semiconductor GaAs/ AlxGa1-xAs DBR and InP/AlInAs TJ current and

optical apertures. We focus on SM output power and modulation bandwidth

maximization at high temperatures. To the best of our knowledge, we are the first to

incorporate TJs with LW-VCSELs on wafer bonded structures [21] in order to

remove the voltage drop across the p-p bonded interface [15] and minimize the p-

doping in the structure by eliminating a thick p-doped DBR. We are also the first to

present an intra-cavity contacting scheme in conjunction with wafer-bonding

eliminate current conduction through the bonded interface [21]. Figure 1.2 shows a

basic schematic of the device structure examined in this thesis.

Figure 1.2: Basic device structure developed and analyzed in this work.

We are also the first to present temperature and gain-mode offset design

principles to maximize modulation bandwidth at high temperatures for LW-VCSELs.

Analysis has been previously presented in the short-wavelength regime [22]. We

develop a simple and intuitive model to analyze the electrical, threshold, current-

power (L-I) and differential gain effects on modulation bandwidth. While the model

is not self-consistent, it provides us with a general idea of the effect of temperature

9

and gain-mode offset on modulation characteristics. The calculated characteristics

match measured results very well.

Based on initial intra-cavity, wafer-bonded LW-VCSEL results and structural

changes determined by temperature and offset modeling, we develop devices which

demonstrate greater than 2 mW single-mode (SM) output power at 20 °C and 1.5 mW

SM output power at 70 °C. The devices also demonstrate 10 GHz 3-db bandwidth at

20 °C and 6 GHz 3-db bandwidth at 70 °C. Finally, we show maximum relaxation

resonance peaks, fr, of 9 GHz and 8 GHz at 20 °C and 70 °C respectively.

This dissertation is divided into several chapters which discuss device

design, modeling, fabrication, results and analysis. Chapter 2 addresses the active

region and structural design of the devices. We focus primarily on the transition from

InGaAsP to AlInGaAs multi quantum-well (MQW) active regions, QW number

optimization, and DBR design.

In Chapter 3, we explain the electrical design and optimization of our devices.

Most of the material in the chapter is devoted to TJ characterization and optimization.

We present modeled TJ characteristics for our initial structures and address the sub-

par performance of the junctions. We also present the resistivity and doping levels

necessary to uniformly pump a TJ aperture and facilitate SM device operation. The

current leveling model was developed initially by Dr. Jeff W. Scott and modified for

TJ purposes for Dr. Eric Hall [7, 23]. We then present I-V characteristics for an

optimized SM device by including spreading and cladding resistances with the

optimized TJ resistance.

10

Chapter 4 presents a model to calculate theoretical modulation characteristics

based on L-I, threshold, and differential gain modeling. We show several design

curves which demonstrate the variation in output power and modulation response

with gain-mode offset and ambient temperature. Using the calculated results from

this chapter, we can define an optimal gain-mode offset which should maximize high-

temperature, high-speed performance.

Chapter 5 explains the fabrication steps involved in first, second, and third

generation devices. We focus on the problems encountered during the fabrication

process and the development steps taken to remedy these issues. Chapter 5 also

explains the buried aperture process used in first and second generation devices and

explains the bond process involved in the fabrication of all devices.

Chapter 6 presents results and discussion of devices for all three generations.

CW current-light-voltage (L-I-V) and light-current relationships versus temperature

(L-I-T) are presented for all three generations, in addition to threshold and thermal

analysis. The chapter concludes with a discussion of the modulation characteristics

of third generation devices.

Chapter 7 presents a summary of the dissertation work and offers several

suggestions for future work that could allow the devices to take the final leap in

performance necessary for commercial use. Appendix A offers a step by step process

follower for first generation devices and Appendix B offers step by step process

follower for second generation devices.

11

References

[1] C. Wilmsen, H. Temkin, and L. A. Coldren, Vertical-Cavity Surface-Emitting Lasers: Design, Fabrication, Characterization, and Applications: Cambridge University Press, 1999.

[2] T. Nishida, M. Takaya, S. Kakinuma, T. Kaneko, and T. Shimoda, "4.2mW

GaInNAs long-wavelength VCSEL grown by metalorganic chemical vapor deposition," presented at International Semiconductor Laser Conference 2004, Conference Proceedings, 2004.

[3] A. Ramakrishnan, G. Steinle, D. Supper, C. Degen, and G. Ebbinghaus,

"Electrically pumped 10 Gbit/s MOVPE-grown monolithic 1.3 mu m VCSEL with GaInNAs active region," Electronics Letters, vol. 38, pp. 322-324, 2002.

[4] V. Gambin, W. Ha, M. Wistey, H. Yuen, S. R. Bank, S. M. Kim, and J. S.

Harris, "GaInNAsSb for 1.3-1.6-mu m-long wavelength lasers grown by molecular beam epitaxy," IEEE Journal of Selected Topics in Quantum Electronics, vol. 8, pp. 795-800, 2002.

[5] D. Feezell, D. Buell, and L. Coldren, "InP-Based 1.3-1.6um VCSELs with

Selectively Etched Tunnel Junction Apertures on a Wavelength Flexible Platform," IEEE Photonics Technology Letters, vol. 17, 2005.

[6] D. Feezell, L. Johansson, D. Buell, and L. Coldren, "Efficient Modulation of

InP-Based 1.3um VCSELs with AsSb-Based DBRs," IEEE Photonics Technology Letters, vol. 17, 2005.

[7] E. M. Hall, "Epitaxial Approaches to Long-Wavelength Vertical-Cavity

Lasers," in Materials, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2001.

[8] M. Ortsiefer, S. Baydar, K. Windhorn, G. Bohm, J. Rosskopf, R. Shau, E.

Ronneberg, W. Hofmann, and M. C. Amann, "2.5-mW single-mode operation of 1.55-mu m buried tunnel junction VCSELs," IEEE Photonics Technology Letters, vol. 17, pp. 1596-1598, 2005.

12

[9] M. Arzberger, M. Lohner, G. Bohm, and M. C. Amann, "Low-resistivity p-side contacts for InP-based devices using buried InGaAs tunnel junction," Electronics Letters, vol. 36, pp. 87-88, 2000.

[10] V. Iakovlev, G. Suruceanu, A. Caliman, A. Mereuta, A. Mircea, C. A.

Berseth, A. Syrbu, A. Rudra, and E. Kapon, "High-performance single-mode VCSELs in the 1310-nm waveband," IEEE Photonics Technology Letters, vol. 17, pp. 947-949, 2005.

[11] J. Cheng, C.-L. Shieh, X. Huang, G. Liu, M. V. R. Murty, C. C. Lin, and D.

X. Xu, "Efficient CW Lasing and High-Speed Modulation of 1.3-um AlGaInAs VCSELs With Good High Temperature Lasing Performance," IEEE Photonics Technology Letters, vol. 17, pp. 7-9, 2005.

[12] J. Dudley, "Wafer Fused Vertical Cavity Lasers," in Electrical and Computer

Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1994.

[13] D. I. Babic, "Double-fused long-wavelength vertical-cavity lasers," in

Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1995.

[14] N. M. Margalit, J. Piprek, S. Zhang, D. I. Babic, K. Streubel, R. P. Mirin, J. R.

Wesselmann, J. E. Bowers, and E. L. Hu, "64 degrees C continuous-wave operation of 1.5-mu m vertical-cavity laser," IEEE Journal of Selected Topics in Quantum Electronics, vol. 3, pp. 359-365, 1997.

[15] A. Black, "Fused Long-Wavelength Vertical-Cavity Lasers," in Materials,

vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2000. [16] A. Karim, "Wafer Bonded 1.55 um Vertical Cavity Laser Arrays for

Wavelength Division Multiplexing," in Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2001.

[17] Y. Okuno, "Polarization control of long-wavelength vertical cavity surface

emitting laser (VCSEL) fabricated by orientation-mismatched wafer bonding," in Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2004.

[18] J. Geske, "Ultra-Wideband WDM VCSEL Arrays by Lateral Heterogeneous

Integration," in Electrical and Computer Engineering. Santa Barbara: University of California, Santa Barbara, 2004.

13

[19] E. S. Bjorlin, "Long-Wavelength Vertical-Cavity Semiconductor Optical Amplifiers," in Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2002.

[20] G. C. Cole, "MEMS-tunable vertical-cavity SOAs," in Electrical and

Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2005.

[21] V. Jayaraman, M. Mehta, A. W. Jackson, S. Wu, Y. Okuno, J. Piprek, and J.

E. Bowers, "High-power 1320-nm wafer-bonded VCSELs with tunnel junctions," IEEE Photonics Technology Letters, vol. 15, pp. 1495-1497, 2003.

[22] D. B. Young, J. W. Scott, F. H. Peters, M. G. Peters, M. L. Majewski, B. J.

Thibeault, S. W. Corzine, and L. A. Coldren, "Enhanced Performance of Offset-Gain High-Barrier Vertical-Cavity Surface-Emitting Lasers," IEEE Journal of Quantum Electronics, vol. 29, pp. 2013-2022, 1993.

[23] J. W. Scott, "Design, fabrication and characterization of high-speed intra-

cavity contacted vertical-cavity lasers," vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1995.

14

Chapter 2

Active Region and DBR Design

In this chapter, we introduce the device structure and briefly analyze multi-quantum

well (MQW) and Distributed Bragg Reflector (DBR) design. The focus of the

chapter is to explain our choice of structure through calculations comparing our

design to others that have been used in the development of LW-VCSELs.

Section 2.1 will present the structures fabricated in this work. Section 2.2 will

cover active region and multi-quantum well (MQW) design. Section 2.3

demonstrates the theoretical improvement in device performance by transitioning

from doped to un-doped DBRs.

2.1 Device Structure

All device structures examined in this work are shown in Figure 2.1. First and second

generation devices are represented in Fig. 1(a) while Fig. 1(b) shows a schematic for

third generation. Several features are common to all three generations: a multi-

15

quantum well (MQW) AlInGaAs active region, double intra-cavity contacts, an

AlInAs/InP TJ current aperture, and un-doped DBRs.

(a) 1st and 2nd generation device Structure (b) 3rd generation device structure Figure 2.1: Basic structures for all structures fabricated in this work. (a) illustrates buried aperture devices while (b) shows undercut aperture structures.

These features are in stark contrast to previous wafer-bonded LW-VCSEL

devices developed by Bowers, et al. which incorporated a top p-type DBR, current

conduction through a bonded interface, either etched post or oxide-confined optical

and current apertures, and InGaAsP MQW active regions [1-4]. We incorporate the

changes to maximize gain, minimize loss, and reduce operating voltage.

We transition from InGaAsP to AlInGaAs active regions to increase the

electron confinement in the QWs and improve the high temperature performance of

the devices. Calculations to support this hypothesis are presented in the next section.

Incorporating the TJ removes the p-type DBR from the structure and the intra-cavity

contacts allow us to eliminate all doping from the DBRs. Calculations demonstrating

the improvement from un-doped versus doped DBRs is presented in Section 2.3.

2.1.1 1st and 2nd Generation Device Structure

16

All devices in Figure 2.1(a) employ 3.5-λ active material. The p-cladding layer and

both n-contact layers are each a thickness of one lambda and the un-doped active

region contributes another half-lambda. Table 2.1 shows the layer structure of the

active material and the thickness of each layer as received from Tecwell International.

Material Thickness Doping (cm-3) Comment 3xP-1.1 µm InGaAsP/3xP-InP 7.5/7.5 nm 1x1018 Superlattice P-InP 0.41 µm 5x1017 Cladding U-AlInAs .03825 µm Undoped Active 5xU-AlInGaAs QW (1-1.5% CS)/6xU-AlInGaAs TS barrier

4.5/8.5 nm Undoped MQW

U-AlInAs .03825 µm Undoped Active N-InP 0.41 µm 1x1018 Cladding/Contact3xU-1.1 µm InGaAsP/3xU-InP 7.5/7.5 nm Undoped Supelattice U-InGaAs Layer 0.15 µm Undoped Etch-stop InP Buffer Layer 0.5 µm Undoped InP Substrate 400 µm

Table 2.1: 1st and 2nd generation epitaxial structure as received from vendor. The growth terminates at the top super-lattice region. The tunnel junction and top contact layers are subsequently re-grown.

Neither the TJ nor the top contact layer is shown in the Table 2.1 since both

are re-grown. The InGaAs layer is used only as a stop-etch layer during substrate

removal after the first bond. It is then removed to ensure that no inter-band

absorption layers remain in the structure. The super-lattice (SL) layers prevent defect

migration into the active region during the high temperature bond process and enable

cavity-length modifications prior to both bond steps [5]. Each SL is comprised of 3

periods of alternating InP and InGaAsP layers, and each layer is 7.5 nm thick. We

can selectively etch the SL layers to adjust the cavity length and compensate for

growth aberrations. We can also use SL-based cavity length adjustment to fabricate

17

variable offset devices. This process has also been used to fabricate DWDM and

CWDM device arrays [6, 7].

The complete active region will include a lithographically defined InP/AlInAs

TJ aperture buried in a full-wave InP contact layer. The fabrication process for this

structure is described in Chapter 5. Both DBRs in first and second generation devices

are wafer-bonded GaAs/AlGaAs.

2.1.2 3rd Generation Device Structure

The third generation structure incorporates an undercut TJ aperture and a dielectric

output coupler. We also use various structures for the back mirror including

dielectric, metamorphic GaAs/AlGaAs, and wafer bonded GaAs/AlGaAs DBRs.

Finally, we reduce the p-cladding thickness from a full-wave to a half-wave layer.

The introduction of the undercut aperture eliminates the re-growth. Thus, the entire

active region including the TJ and contact layer is grown in a single step. In order for

the dielectric output coupler deposition to be the final step in the fabrication process,

the active structure is grown in the reverse order of the first and second generation

growth process and bonded to any of the three various back DBRs during the first

fabrication step. Table 6.2 shows general layers and thicknesses for a 3rd generation

as-grown active region.

Material Thickness Doping (cm-3) Comment 3xU-1.1 µm InGaAsP/3xU-InP 7.5/7.5 nm Undoped Superlattice N-InP 0.41 µm 1x1018 Cladding/ContactU-AlInAs .01225 µm Undoped Active

18

7xU-AlInGaAs QW (1-1.5% CS)/8xU-AlInGaAs TS barrier

4.5/8.5 nm Undoped MQW

U-AlInAs .01225 µm Undoped Active P-InP 0.205 µm 5x1017 Cladding P-AlInAs 10 nm p++ TJ Layer N-InP 20 nm n++ TJ Layer N-InP 0.41 µm 1x1018 Cladding/ContactU-InGaAs Layer 0.15 µm Undoped Etch-stop InP Substrate 400 µm

Table 2.2: 3rd generation epitaxial structure, grown at Agilent Laboratories. We invert the acive region growth to accommodate the single bond process. Also, since the structure utilizes an undercut TJ aperture, the initial active region growth runs through the top contact layer.

2.2 Active Region Design

Groups have experimented with several distinct LW-VCSEL active regions to

improve the performance of the devices. Most initial work was done on InGaAsP.

InGaAsN has shown strong performance up to 1290 nm, but does not yet perform

well over the entire O communication bands [8]. In the last several years, AlInGaAs-

based devices have shown significant improvements over their InGaAsP counter-

parts. This work was the first to incorporate AlInGaAs MQW active regions with

wafer-bonding [9].

All previous wafer-bonded designs at UCSB incorporated InGaAsP MQW

active regions due to growth constraints. The InGaAsP/bonding technology resulted

in many milestones including the first demonstration of a CW LW-VCSEL and

several iterations of temperature performance world records. But even these devices

exhibited significant power degradation at higher temperatures [1, 2, 6]. While

19

material gain does decrease as temperature rises, gain-mode offset engineering allows

us to minimize this factor. Thus, much of the power roll-off is attributed to electron

leakage from the QW to the barriers due to the low conduction band offset (∆Ec) of

InGaAsP [10].

The LW-VCSELs investigated in this work will perform functions in un-

cooled applications and will thus require high injection efficiency (ηi) and low

leakage recombination (Rl) over a wide range of temperature. Both of these factors

are affected by carrier leakage recombination currents arising from electrons and

holes that escape the QW and become free to diffuse. Moreover, we must ensure that

the active region will provide enough material gain to sustain lasing at high

temperatures. Thus, in this section, we present design principles to minimize carrier

leakage out of the QW at high temperature and optimize QW number and standing

wave enhancement factor (ξ) in order to minimize threshold current density and

reduce the active region temperature increase as we increase current injection.

2.2.1 AlInGaAs vs. InGaAsP Quantum Well Active Regions

AlInGaAs active regions exhibit a ∆Ec = 0.72∆Eg compared to ∆Ec = 0.4∆Eg of

InGaAsP [10]. Since our goal is to maximize high temperature performance, we

choose to incorporate AlInGaAs rather than InGaAsP QWs in our structure. Table

2.3 shows the energy difference between the carrier state in the QW and the barrier

for which 4.5 nm Al0.18In0.67Ga0.15As and In0.75Ga0.25As0.54P0.46 quantum wells lase at

1.3 µm.

20

AlInGaAs InGaAsP Electron Confinement (meV) 109 41.5

Hole Confinement (meV) 64.5 132 Table 2.3: Electron and hole confinement for 4.5 QWs designed to for an initial state transition of 1.3 µm in both AlInGaAs and InGaAsP active regions.

Since the hole quasi Fermi-level (EFv) should sit further in the QWs than the

electron quasi Fermi-level (EFc) due to the larger effective mass, we expect the holes

to be more tightly confined in the wells than the electrons. The effect becomes more

prominent at high temperatures. For that reason, we choose AlInGaAs QWs for the

gain region.

Figure 2.2 shows a photo-luminescence (PL) spectrum for one of our active

regions. The measurement shows a PL peak of 1274 nm with a full-width, half-

maximum (FWHM) of 33.46 nm. InGaAsP QWs on the other hand, show FWHM

values of 70-80 nm [5]. The sharper PL peak and smaller FWHM are characteristic

of a higher gain active region.

21

Figure 2.2: PL intensity of 1st generation active region measured on a micro-PL setup (designed by Jonathan Geske). The active region demonstrates a PL peak of 1274 nm and a FWHM of 33.5 nm.

2.2.2 Quantum Well Number Optimization

Now that we have quantified the advantage of AlInGaAs vs. InGaAsP QWs at high

temperatures, we can turn our attention to QW number optimization. The reduction

in gain with temperature presents a challenge in minimizing QW number. Employing

too few wells may result in insufficient material gain to sustain lasing at high

temperatures.

Our goal is to choose the number of QWs which theoretically minimize Ith at

high temperature. For simplicity, we limit our analysis to structures incorporating

three, five and seven QWs. All calculations are based on measurements which show

a threshold material gain of 550 cm-1 for five QW active regions [9].

22

In order to quantify the gain characteristics of various QW structures, we first

present calculations for the standing wave enhancement factor, or Γenh. The method

for calculating Γenh can be found elsewhere [11]. Figure 2.4 shows the variation in

average Γenh between one and eleven QWs. The plot shows a sharp reduction in Γenh

to below 1.5 beyond six QWs. As we will show later, the reduction in Γenh for large

numbers of QWs severely limits the improvement in material gain improvement that

we generally observe with more QWs.

Figure 2.3: Calculation of standing wave enhancement factor (ξ) versus number of quantum wells. Calculations are based on 4.5 nm wells and 8.5 nm barriers.

Under the assumption that increasing the number of QWs does not increase

the intra-band absorption losses in the device, we can assume that the single pass gain

for a structure regardless of well number must remain constant. This relationship is

expressed as follows:

(1) )**exp()***exp(11 athenhawthenh LgLNg

wwwNwNΓ=Γ

23

where Nw is the number of wells, and La is the length of a single QW. Based on Eq.

(1), the data in Figure 2.3, our knowledge of gth for a five QW structure, and a single

QW length, La, of 4.5 nm, we can calculate gth for structures incorporating any

numbers of QWs. Calculated values for gth are shown in Table 2.4.

Number of Quantum Wells gth (cm-1)3 821 5 550 7 468 9 471

Table 2.4: Calculated threshold gain (gth) characteristics for various numbers of QWs. Calculations are based on the knowledge of gth = 550 cm-1 for 5 QW devices.

The increase in gth from seven to nine QWs arises from the reduction in Γenh.

Figure 2.4 plots calculated Ith versus QW number for three different lasing

wavelengths. We extend the data to seven QWs because the design provides a

minimum gth. All material exhibits a gain peak of 1280 nm. The variation in

characteristics versus lasing wavelength is a pre-cursor to the offset analysis

performed in Chapter 3. Figures 2.4(a) and (b) calculate Ith at 20 °C and 140 °C

internal temperature, respectively.

24

(a) Tactive = 20 °C (b) Tactive = 140 °C Figure 2.4: Theshold current (Ith) versus number of quantum wells at active region temperatures of 20 °C and 140 °C. Both curves show characteristics at 0 nm, 20 nm, and 40 nm gain-mode offsets.

The curves in Figure 2.4 clearly show a reduction in Ith between three and

seven QWs. This data is consistent with the gth values in Table 2.3. The data does

not take into account non-uniform pumping of the wells. It is possible that in

practice, not all wells will be pumped to transparency and the some wells may

provide excess optical loss to the device. But as we will show in Chapter 6, third

generation devices which incorporate seven QWs do provide superior performance to

first generation five QW devices. The data in Figure 2.4 also shows a reduction in Ith

with increasing difference between the gain peak and lasing mode at 140 °C.

Analysis of this trend will be presented in Chapter 4.

2.2.3 Absoprtion Loss Contribution from Active Layer

25

The VCSEL cavity (minus DBR penetration depth) in each of our structures includes

two full-wave n-type cladding layers and one full-wave p-type cladding layer. Due to

the thickness and high doping levels of these layers, they contribute the largest

percentage of optical loss to our structure. We will analyze the optical loss due to the

TJ layers in Chapter 3.

Increased doping levels in a VCSEL cladding layer result in a trade-off

between lower transport resistance and higher optical loss. A quantitative discussion

of this trade-off can be found in [12]. Based on calculations in the previous

reference, we find that reasonable doping levels for the n-type layers are between

1x1018 cm-3 and 1x1019 cm-3 and between 1x1018 cm-3 and 5x1019 cm-3 for the p-side.

The range is reduced for the p-layer due to the high intra-valence band absorption

associated with p-doped layers. Figure 2.5 shows the variation in single pass free-

carrier absorption (FCA) over the doping range of interest to our devices.

(a) n-doped layer (b) p-doped layer

Figure 2.5: Single pass (FCA) versus doping in (a) n-doped layer and (b) p-doped layer.

26

2.3 Distributed Bragg Reflector (DBR) Design

Proper DBR design to minimize operating voltage and optical loss of the structure

can improve device performance significantly. Devices incorporating a p-type wafer-

bonded DBRs show maximum output powers less than 1 mW [1-4]. This is in large

part due to free-carrier absorption in the GaAs layers that can be as high as 25 cm-1 at

an acceptor doping level of 1x1018 cm-3 [13]. DBRs employing 1x1018 cm-3 n-type

doping demonstrate optical absorption on the order of 6 cm-1. Moreover, the

resistance of n-doped DBRs is sufficiently low for VCSEL operation [14]. These

mirrors are capable of replacing intra-cavity contacts in large area apertures if current

crowding becomes an issue.

All of our structures employ an un-doped bottom DBR and at least one intra-

cavity n-contact. Figure 2.5 shows an experimental L-I curve along with the

theoretical reduction in output power given a top n-type DBR and a top p-type DBR.

We calculate the theoretical reduction in output power by calculating the change in

differential efficiency (ηd) given a change in internal loss (αi). Replacing the undoped

DBR with a p-type or n-type DBR yields ~ 35% and 15% reduction in maximum

output power respectively.

27

Figure 2.6: Theoretical decrease in room temperature output power of first generation devices if un-doped top DBR is replaced with p-type and n-type DBRs doped high enough to provide minimal electrical resistance.

2.4 Summary and Conclusion

We present calculations and arguments in this chapter to explain why we choose our

particular device design. Each device design we examine in this thesis employs a

MQW AlInGaAs active region, double intra-cavity contacts, an AlInAs/InP TJ

current aperture, and un-doped DBRs. While first and second generation devices

incorporate two wafer bonded GaAs/AlGaAs DBRs and a buried TJ current aperture,

third generation devices replace one bonded DBR with a dielectric DBR and replace

the buried current aperture with an undercut TJ aperture.

We decided upon replacing previously used InGaAsP QWs with AlInGaAs

QWs due to the higher electron confinement in the QWs. The transition results in

significantly higher power and temperature performance over previous wafer-bonded

28

LW-VCSELs. The results will be presented in Chapter 6. Further investigation finds

that seven AlInGaAs QWs will minimize gth and allow for the lowest Ith over the

entire range of reasonable operating temperature. In the next chapter, we present the

electrical device design and optimization while paying specific attention to TJ design

and simulation.

29

References

[1] D. I. Babic, J. Piprek, K. Streubel, R. P. Mirin, N. M. Margalit, D. E. Mars, J.

E. Bowers, and E. L. Hu, "Design and analysis of double-fused 1.55-mu m vertical-cavity lasers," IEEE Journal of Quantum Electronics, vol. 33, pp. 1369-1383, 1997.

[2] N. M. Margalit, J. Piprek, S. Zhang, D. I. Babic, K. Streubel, R. P. Mirin, J. R.

Wesselmann, J. E. Bowers, and E. L. Hu, "64 degrees C continuous-wave operation of 1.5-mu m vertical-cavity laser," IEEE Journal of Selected Topics in Quantum Electronics, vol. 3, pp. 359-365, 1997.

[3] K. A. Black, P. Abraham, N. M. Margalit, E. R. Hegblom, Y. J. Chiu, J.

Piprek, J. E. Bowers, and E. L. Hu, "Double-fused 1.5 mu m vertical cavity lasers with record high T-o of 132K at room temperature," Electronics Letters, vol. 34, pp. 1947-1949, 1998.

[4] A. Karim, S. Bjorlin, J. Piprek, and J. E. Bowers, "Long-wavelength vertical-

cavity lasers and amplifiers," IEEE Journal of Selected Topics in Quantum Electronics, vol. 6, pp. 1244-1253, 2000.


vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2000. [6] A. Karim, "Wafer Bonded 1.55 um Vertical Cavity Laser Arrays for




[8] T. Nishida, M. Takaya, S. Kakinuma, T. Kaneko, and T. Shimoda, "4.2mW

GaInNAs long-wavelength VCSEL grown by metalorganic chemical vapor deposition," presented at International Semiconductor Laser Conference 2004, Conference Proceedings, 2004.



30

[10] J. W. Pan and J. I. Chyi, "Theoretical study of the temperature dependence of 1.3-mu m AlGaInAs-InP multiple-quantum-well lasers," IEEE Journal of Quantum Electronics, vol. 32, pp. 2133-2138, 1996.

[11] N. Margalit, "High-Temperature Long-Wavelength Vertical-Cavity Lasers,"

in Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1998.

[12] D. Feezel, "Long-Wavelength Vertical-Cavity Surface-Emitting Lasers with

Selectively Etched Thin Apertures," in Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2005.

[13] D. I. Babic, "Double-fused long-wavelength vertical-cavity lasers," in

Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1995.

[14] M. G. Peters, "Molecular beam epitaxial growth of vertical-cavity lasers for

optical communications," in Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1995.

31

Chapter 3

Electrical Device Design and Optimization

Tunnel junctions (TJ) have found widespread application in high-frequency

oscillators and thermophotovoltaic devices since their discovery in 1958 [1-3]. More

recently, groups have incorporated TJ structures into long-wavelength vertical-cavity

surface-emitting lasers (LW-VCSELs) in order to realize reduced optical loss, as well

as current and optical confinement.

A large portion of the work in this dissertation focuses on the design of the

electrical properties of TJs in LW-VCSELs. Several parameters are important to

consider when designing a device capable of operating SM in a modular

communication system, e.g. differential resistance, absolute resistance and lateral

current spreading in the aperture. As stated in Chapter 1, these devices are to be used

as 50 Ω terminations in modules driven by 3.3 V circuitry. Furthermore, transmission

distances of 2 – 15 km necessitate SM devices in order to limit the dispersion effects

during data transmission.

32

While groups have presented work on the theoretical modeling and design

principles of InGaAs and InGaAsN TJs on GaAs substrates, little has been made

public about the modeling and design of AlInAs/InP and AlInGaAs/AlInGaAs TJs

developed on InP [4]. Moreover, little work has been presented on TJ design for SM

applications. The conventional wisdom on TJ growth has been to impress a

maximum flux of Carbon (C) atoms on a Hall calibration sample of the p++ layer and

rely on the measured hole concentration to serve as the experimental limit.

Unfortunately, this technique does not provide the most accurate or steadfast TJ

design method for several reasons. First, the accuracy of the doping calibration is

questionable since the actual AlIn(Ga)As p++ layer thickness (10 nm) is only ~1% of

the prepared Hall sample thickness (1 µm). Second, the amphoteric nature of C in

AlIn(Ga)As can yield compensation effects reducing the overall hole concentration in

the TJ [5]. Finally, it is necessary that the tunnel junction provides enough lateral

spreading resistance to uniformly spread carriers into the active region. Designs

which fail to take into account this effect tend to produce MM devices which are not

suitable for applications requiring signal propagation beyond several hundreds of

meters.

The aim of this chapter is to model optimal TJ operation for use in SM LW-

VCSELs and incorporate the modeled TJ characteristics with optimized electrical

designs for the rest of the device in order to determine a theoretical maximum SM

output power and roll-over current for our device structure. In Section 3.1, we

present theoretical TJ characteristics based on a model developed by Demassa and

33

Knott, and compare the model to experimental TJ results [6]. In Section 3.2, we

derive the TJ resistivities necessary to uniformly pump the active region over a range

of aperture sizes, and use the model from Section 3.1 to determine the TJ doping

densities required to achieve the desired resistivity. Once the electrical properties of

the TJ are optimized, Section 3.3 examines physical layer thickness design of the TJ

using tunneling probability metrics. We use the redesigned layer thicknesses to

quantify the reduction in optical loss due to free-carrier absorption in the TJ layers as

compared to our experimental design and calculate the effect of growth aberrations on

the optical loss. Section 3.4 incorporates the results of the TJ optimization in the

previous sections with active region diode characteristics, spreading resistance,

hetero-barrier voltage, and transport resistance to generate a complete I-V model for

the VCSEL. We present two calculated curves – one which closely matches our

experimental I-V results and the other which presents a theoretical I-V curve for an

optimized device. While some reduction in device voltage in the optimized structure

arises from changes in device geometry and cavity length reduction, most

improvement stems from TJ optimization presented in earlier sections. Finally, we

present the theoretical increase in SM output power and roll-off current associated

with optimizing the electrical characteristics of the device.

3.1 TJ Design and Experiment

Figure 3.1 illustrates the energy band diagram for an AlInAs/InP TJ doped 2x1020

cm-3 and 5x1019 cm-3 on the p-side and n-side respectively. This particular

34

Figure 3.1: Band diagram for an p++-AlInAs/n++-InP TJ doped 2x1020 cm -3 and 5x1019 cm-3 on the p and n sides respectively. The points x1 and x2 represent the tunneling width limits at the Fermi level at equilibrium. The p-side is 10 nm thick while the n-side is 20 nm.

configuration benefits from a Type II band alignment which facilitates the degeneracy

required for TJ operation. Ef represents the equilibrium Fermi level and x1 and x2 will

present the limits of integration for WKB analysis in Section 3.3. An effective

reverse bias of the degenerate TJ layer quantum mechanically extracts electrons from

the valence band into the conduction band of the TJ. The generated conduction

electrons drift towards the positive electrode while the generated holes drift into the

active region. The fundamental tunneling current is given by [6]:

(3.1) dEzEGEGEFEFAI vcvc ∗∗∗∗−= ∫ )()()]()([

where Fc(E) and Fv(E) represent the Fermi probability functions in the conduction

and valence bands respectively, Gc(E) and Gv(E) serve as density of states functions

35

in the conduction and valence bands respectively, and z defines the tunneling

probability. Figure 3.1 demonstrates that the stated doping levels place the Fermi

level significantly further into the conduction band of the n++ layer than the valence

band of the p++ layer. Since changes in Fermi level will more significantly affect the

number of available states in the valence band as opposed to the conduction band,

acceptor concentration gradients will predominantly determine the current-voltage (I-

V) characteristics of the diode.

A closed form solution to Eq. (3.1) is given by:

⎟⎠⎞

⎜⎝⎛ −⎟

⎠⎞

⎜⎝⎛=

ppp

VV

VVJJ 1exp (3.2)

where Jp and Vp are the current density and voltage values corresponding to the peak

tunneling current density before the Esaki dip [7]. Jp and Vp have been analytically

defined by Demassa, et al. as [6]:

3)( pn

P

VVV

+≈ (3.3)

and

(3.4) 2/12/1

2/13

*2 dVnqF ⎟⎟

⎠

⎞⎜⎜⎝

⎛=

ε

⎥⎥⎦

⎤

⎢⎢⎣

⎡= ⊥ hF

EmDE

hqmJ g

p 2/1

2/32/1

3 )2(2*

exp36

* π2/12/1

2/1

*2

gEmhFE

π=⊥

where Vn and Vp represent the degree of Fermi level penetration into the conduction

and valence bands on the n and p sides respectively, m* is the reduced effective mass,

D is the overlap integral and can be estimated as VP, and Vd serves as the diffusion

potential estimated by Eg.

36

We can use Eqs. (3.2), (3.3) and (3.4) to generate theoretical J-V

characteristics for TJs based on doping and bandgap variations, and subsequently fit

these characteristics to experimental results to deduce the actual doping density of our

test structures and devices. Since we are primarily focused on the reverse bias

characteristic for TJ operation, all modeled characteristics from here forward will

transpose the third quadrant of the modeled characteristic into the first quadrant, i.e.

we will show only reverse bias TJ characteristics. Figure 3.2 shows J-V

characteristics at various bandgap energies for TJs with the expected doping levels

mentioned earlier in this section. According to the data, we should observe a

negligible 25 mV voltage drop across a 1.1Q AlInAs/InP TJ at a nominal operating

current density of 10 kA/cm2 and reduce the voltage drop even further by using a

1.2Q AlInGaAs/AlInGaAs TJ. The 1.3Q and 1.4Q TJs are instructive for 1.55 µm

device design but will severely limit performance in 1.3 µm devices due to band-to-

band optical absorption. Groups have seen operating voltage drops on the order of 30

mV in InGaAs-based TJs [8]. The 25 mV voltage drop corresponds to an effective

contact resistivity of 2.5x10-6 Ω-cm2, similar to the best p-type contact resistivities

and generally accepted n-type contact resistivities [9, 10].

No group developing Al-based TJs for LW-VCSELs has reportedly seen

characteristics on par with the values observed in Fig 3.2. Example characteristics of

TJ test structures are shown in Fig. 3.3. The structures demonstrate contact

37

Figure 3.2: Calculated variation in characteristics for various band gap TJ characteristics at nominal VCSEL operating current densities (10 – 20 kA/cm2). Calculations assume 2x1020 cm -3 and 5x1019 cm-3 on the p and n sides respectively.

Figure 3.3: Measured data for TJ test structures. Both AlInAs/InP and AlInGaAs/AlInGaAs test structures exhibit similar J-V characteristics. Test structures are grown p-side down on a p-type substrate and employ a back side p-type contact which minimizes the effect of the p-contact resistance.

38

resistivities two orders of magnitude larger than the calculated characteristic results

(~ 1.5x10-4 Ω-cm2). Since doping density determines the J-V characteristics of the

junction, we extend the TJ modeling to determine which dopant type is in short

supply and limiting TJ performance.

Figures 3.4 and 3.5 plot the variation in TJ characteristics with doping

densities far different than those in Figure 3.2, but which match the characteristics of

our test structures more closely. Figure 3.4 displays modeled J-V curves for

structures incorporating a constant n-type doping level of 1x1019 cm-3 and varying the

p-type doping between 2x1018 cm-3 and 6x1018 cm-3. Fig. 3.5 displays modeled J-V

Figure 3.4: Calculated J-V curves for TJ structures which more closely match measured characteristics in Figure 3.3 than calculated curves in Figure 3.2. The curve shows the large effect of p-doping variation on TJ characteristics. All curves assume n-type doping of 1x1019 cm-3 and vary p-type doping from 2x1018 to 6x1018 cm-3.

curves for structures incorporating a constant p-type doping level of 2x1018 cm-3 and

varying the n-type level between 10x1018 cm-3 and 13x1018 cm-3. All the curves in

39

Figures 3.4 and 3.5 calculate characteristics for structures designed with a 918 nm

bandgap. The two curves clearly show that changes in p-type doping levels have a

much stronger effect on TJ characteristics than do changes in n-type doping levels.

While the 3x1018 cm-3 doping increase shows nominally no change in TJ resistivity

with n-type doping changes, the same increase on the p-side results in an order of

magnitude decrease in TJ resistivity. The inherent effect of p-type doping density on

TJ characteristics further confirms the difficulty in incorporating high levels of C as

an acceptor into Al-based layers.

Calculated J-V curves TJ structure which assumes a constant p-ty and varies n-type doping from 10x1018 to 13x1018 cm-3. The curve

t that the n-doping level has on TJ resistivity.

Figure 3.5: pe doping of 2x1018 cm-3 illustrates the minimal effec

characteristics of Figures 3.4 and 3.5, we extract a p-type doping level of

approximately 2x1018 cm-3 on our devices. Figure 3.6 demonstrates a 1 V

Based on the TJ test structure characteristic of Fig. 3.3 and the modeled

40

improv

ng the epitaxial deposition process and

increas

ement in TJ operating voltage by decreasing the bandgap of the TJ from 918

nm to 1200 nm. As before, 1300 nm and 1400 nm characteristics are shown for

instructional purposes on 1.55 µm devices.

Actual LW-VCSELs show similar extracted resistivities to our test structures.

Possible reasons for the low acceptor levels as compared to our initial design include

non-optimized C/In and III/V ratios duri

ed dopant diffusion or compensation during growth of the VCSEL structure

versus the Hall samples [5]. Furthermore, the electric field gradient will vary for the

actual sample when compared to the Hall samples due to the absence of the alternate

highly doped layer of the TJ in the Hall sample, presenting another factor which

could serve to displace acceptor ions from their primary lattice sites.

Figure 3.6: Bandgap variation of TJ characteristics based on an p-type doping level of 2x1018 cm-3 and an n-type doping from 10x1018 cm-3.

41

3.2 Lateral Current Spreading Optimization

Given an intra-cavity contacting scheme, a simple analytic expression to define the

current density as a function of distance from the aperture edge is given by [11]:

(3.5)

where x is the distance from the aperture edge, Rtd is the TJ resistivity, lh is the contact

layer thickn is the contact layer conductivity, and defines a characte

ngth which we will use to determine the optimal resistivity of the current spreading

r to provide uniform current spreading, ξ should be larger than the radius

the

⎟⎟⎜⎜=J exp⎠

⎞

⎝

⎛ξx

RV

td

otdhh Rl **σξ =

ristic ξess, σh

le

TJ aperture.

In order to realize SM VCSEL operation, the current must spread evenly

throughout the TJ aperture. Previous work has shown that in order for the highly-

resistive laye

of current-confining aperture [11]. We hold lh and σh constant at values which

optimize the optical loss/resistance trade-off in the contact layer. Figure 3.7 plots the

minimum resistivity required to uniformly pump aperture sizes up to 20 µm based on

Eq. 3.5. Any reduction in resistivity from these values will cause current crowding

around the edges of the TJ aperture and enhance MM VCSEL operation. Our

VCSEL results corroborate this model as we see more output power in higher order

lasing modes rather than the fundamental mode on devices between 12 µm and 20

µm, as will be shown experimentally in Chapter 6. Devices with 8 µm apertures

42

show single mode operation and concurrently more uniform current distribution.

According to Figure 3.7, the minimum resistivity required to uniformly pump an 8µm

Figure 3.7: Minimum TJ resistivity necessary to uniformly spread carriers throughout various diameter TJ aperture.

aperture is 6x10-5 Ω-cm2, a value less than we observe experimentally. Table 3.1

918 nm and 1200 nm band gap TJs for 8, 12, 16, and 20 µm devices. We note several

shows the p-doping values which correspond to the single mode threshold for both

observations when considering the data from Figure 3.7 and Table 3.1. First, a highly

conductive TJ is not the best design for optimized SM performance unless the

structure includes an alternate high mobility layer to spread the carriers uniformly.

Second, large devices for use in multi-mode applications may be better suited for use

with current pumping through a DBR which naturally spreads carriers more evenly

throughout an aperture than intra-cavity schemes.

43

Aperture size Optimized p-(in µm) doping @ E =918 doping @

Eg=1200 nm g

nm

Optimized p-

8 5x10 cm18 -3 18 -32.3x10 cm

12 3x1018 cm-3 1.5x1018 cm-3

16 2x1018 cm-3 1.1x1018 cm-3

20 1x1018 cm-3 1x1018 cm-3

Table 3.1: Maximum T ing leve c ll spread carriers uniformly throughout the aperture for 8, 12, 16, and 20 µm devices. Th f as optimized doping levels for SM device desi

Before calculating the complete device I-V and L-I characteristics, we define the

e highly doped

(3.6)

The analysis presented h eter in brac

ined by Mars, et al., as the WKB parameter, to determine tunneling quality [4]:

(3.7)

As WKB in

The limits of integration, x1 and x2, are delineated in Figure 3.1, and serve as the

constructs for the quantum tunneling width. The energy potential barrier is defined as

J dop ls whi h wiey can also be thought o

gn.

3.3 WKB Parameter and Tunneling Probability

physical limits of tunneling in order to minimize optical loss in th

layers in the TJ. The tunneling probability is defined as [4]:

⎥⎦

⎤

⎢⎣

⎡ 2

1

*22

x

xfct

mh

⎥⎢ −−≅ ∫ )(2exp dxEEP

kets, ere compares the absolute value of the param

co

∫ −≅ )(2 dxEEWKB

2

1

*22

x

xfc

mh

creases linearly, the tunneling probability, z, decreases exponentially.

44

(Ec-Ef), and closely resembles a triangular potential barrier with an energy barrier

defined by (Eg/2 – qεx) where Eg and ε define the bandgap and electric field

respectively.

The WKB parameter serves as a first-order design metric in determining TJ

layer thickness. The TJ needs to be thick enough as not to deplete the layers, but as

thin as possible to minimize free-carrier optical absorption. We calculate the single

vels in the p and n layers are 5x1018 cm-3 and

x1019

pass absorption using standard standing wave enhancement methods and further

developed by Margalit in order to calculate loss in a vertical cavity structure [12].

We attempt to minimize the free carrier absorption by placing the TJ close to a

standing wave null in the device.

Figure 3.8 displays the single pass absorption due to free carrier losses in the

TJ versus the relative offset of the TJ layer from a standing wave null for four layer

thickness variations. The doping le

1 cm-3 respectively, the optimized doping values we calculate in the last section.

45

Figure 3.8: Free carrier absorption (FCA) versus relative offset of the n++/p++ TJ interface from a standing wave null. The structure assumes doping levels of 2x1018 cm-3 and 10x1018 cm-3 on the p-side and n-side respectively. The four curves show the loss characteristics for various TJ dimensions. All TJ dimensions illustrated will allow for proper TJ operation.

Zero offset corresponds to the n++/p++ interface placed at a standing wave

null. A positive relative offset represents the TJ moving towards the active region of

the device. The 20 nm n-layer and the 10 nm p-layer serve as our default test

structure values. We can reduce the n-layer thickness from 20 nm to 10 nm and

minimize absorption without any increase in the WKB parameter. We can reduce the

greatest advantage gained from reducing l proved

19 cm-3 on the n-side. From these curves, we see that

n and p-layer thicknesses even further, but we then begin to see an increase in the

WKB parameter and orders of magnitude reduction in tunneling probability. The

ayer thickness and optical loss is im

growth tolerances. We experimentally observe an order of magnitude increase in loss

from growth aberrations of tens of nanometers as we increase 10 nm TJ layers to 20

nm.

It is important to note that the minimum absorption does not occur at 0 nm

offset. Because p-type losses are significantly higher than n-type losses, an optimal

design would place the standing wave null at approximately the center of the p-type

layer. While this effect is not significant in our optimized doping scheme, the design

methodology will have an effect on more highly doped TJ layers, e.g. large aperture

MM devices pumped through a DBR. The design curve in Figure 3.9 shows optical

loss versus offset curves for various width TJs incorporating doping levels of 2x1020

cm-3 on the p-side and 5x10

46

la hickness TJs coupled with 10 nm – 20 nm offset aberrations can cause

significant increase in optical loss and reduce the effective mirror reflectivity by 0.1

% if the standing wave null rests within the n-layer. Thus, growth procedures would

prefer to err on the side of negative relative offset, or placing the standing wave null

within the p-layer in order to minimize the effect of growth aberrations on optical

loss. Figure 3.9 also demonstrates that the TJ thickness can be more significantly

reduced as doping levels increase as a result of the decrease in depletion and

tunneling width of the structure.

rge t

Figure 3.9: Free carrier absorption (FCA) versus relative offset of the n++/p++ TJ interface from a standing wave null. The structure assumes doping levels of 2x1020 cm-3 and 5x1019 cm-3 on the p-side and n-side respectively.

3.4 Voltage Contributions from Other Sources in an Intra-

Cavity Contacted VCSEL Structure

47

Now that we have theoretically designed the TJ to operate at the lowest possible

voltage while still facilitating SM VCSEL requirements, we can incorporate voltage

contributions from other sources to develop a complete electrical model for the

device. The active region diode, intra-cavity contact related resistances associated

with electron transport from the TJ to contacts, p-cladding layer resistances, and other

hetero-barrier voltages will also contribute significantly to the overall I-V

characteristics of these devices. Fig. 3.10 shows our complete VCSEL structure

including labels for contact radius parameters. Rt represents the distance from the

enter of the TJ, and L represents the

thickness of the p-cladding layer.

inside of the top ring contact to the center of the TJ, Rb represents the distance from

the inside of the bottom ring contact to the c

Figure 3.10: Basic device structure. Rb represents the bottom contact inner radius and Rt

resistance associated with the intra-cavity contacts. L defines the length of the p-cladding

The variation in lateral spreading resistance versus inner contact radius for an

8 µm aperture diameter devices is shown in Figure 3.11. The figure shows

represents the top contact inner radius. These two dimensions define the lateral spreading

layer.

48

characteristics for both full-wave (~400 nm) and half-wave (~200 nm) contact layer

thicknesses. The inner contact radius varies between 10 µm and 50 µm. The low end

(10 µm) of the analysis is determined by the mask and process limitations of placing

the top ring contact around the top DBR. On the high end, 50 µm provides sufficient

ease of processing and a further increase in radius will increase resistance without any

benefit. Since both top and bottom contact layers show equal layer thickness and

doping density, we can use the characteristic to calculate resistance values for both

top and bottom contacts. The large increase in resistance derived from reducing the

increase from 25 Ω to 60 Ω. The bottom contact resistance would increase by more

contact layer to a half-wave explains why the layer thickness cannot be reduced

below a full wave. For a 12 µm top contact inner contact radius, the resistance would

than 50 Ω.

Figure 3.11: Lateral spreading resistance comparison for full and half wave InP contact

18

cm-3.

layers versus inner-contact radius. Both curves assume an n-type doping density of 1x10

49

Previous sections presented optimal TJ characteristics. We now calculate the

minimum possible voltage contribution of the spreading, transport, and barrier layers

by reducing device geometries to sizes still within our fabrication capability. We

decrease the top contact radius from 25 µm to 12 µm, decrease the bottom contact

radius from 46 µm to 25 µm, reduce the p-cladding layer thickness from 400 nm to

200 nm (full-wave to half-wave) and delta dope around the hetero-barrier to remove

the hetero-interface voltage. The voltage contributions associated with lateral

spreading, vertical transport, hetero-barriers and the active region diode are shown in

Fig. 3.12. Table 3.2 demonstrates the reduction in resistance contribution from each

of these factors by optimized the device geometry. All data is calculated for an 8 µm

aperture operating at 10 mA. The optimized geometries reduce the initial voltage

improvement due to geometry optimization is not as large as the improvement

afforded through TJ optimization, it is nonetheless important as it nudges the total

differential resistance towards 50 Ω, a key parameter for devices intended for use in

transmission line systems.

drop by 0.3 V and improve the overall differential resistance by 36.19 Ω. While the

voltage

50

Figure 3.12: I-V characteristics of voltage contributions other than the TJ. We include the active region diode characteristic, lateral spreading resistance, vertical transport resistance, and barrier voltage. Device dimensions are 25 µm and 46 µm for Rt and Rb respectively and a 400 nm p-cladding layer.

Top Contact

Spreading Resistance

(Ω)

Bottom Contact

Spreading Resistance

(Ω)

p-Cladding

Resistance (Ω)

Hetero- barrier voltage

(V)

Experimental 27.1 36.12 32.63 .3 Structure

Optimized Structure

16.25 27.1 16.31 0

Table 3.2: Contributions of various resistance contributions for the 1st generation experimental structure versus the optimized dimenstions of: Rt = 12 µm, Rb = 25 µm, and L =

nm.

3.5 Complete Device Model a D p tion

200

nd SM evice O timiza

51

Now that we have optimiz ur de ructur minim the voltage

contribution tive t in th SEL w ll maintaining uniform

urrent spreading, we can compare I-V models for experimental and theoretically

oltage reduction. An experimental I-V curve for an 8µm VCSEL is plotted in Fig.

µm

ed o vice st e to ize

of each resis elemen e VC hile sti

c

optimized devices and predict the improvement in output power associated with the

v

3.13 along with two calculated curves. All calculated curves assume an 8

aperture. The calculated curve that is in strong agreement with the experimental

curve is derived using structural and material values equal to those in the

experimental structure. As mentioned earlier in this chapter, the overestimated

acceptor concentration can arise from many factors, most of which cause large

portions of the C content to act as donors rather than acceptors. Low temperature

AlInAs growth as well as C/In ratio and III-V ratio optimization should improve the

acceptor concentration in the p++ layers. Other groups developing TJs for use in

1300 nm VCSELs have demonstrated low voltage devices and confirm that higher

acceptor concentrations are possible, although to the best of our knowledge, none of

these groups have designed TJs to optimize SM characteristics [13-15].

52

Figure 3.13: I-V characteristics for an 8 µm 1st generation device versus calculated curves based on the I-V characteristics of the TJ and other factors modeled in this chapter. The top calculated curve shows a nice fit with experimental data while the bottom calculated curve shows optimal I-V characteristics for an 8 µm SM TJ apertured device.

The maximum acceptor concentration for single mode operation as defined by

Table 3.1 is 5x1018 cm-3 for an 8 µm device. Incorporating a TJ with this optimized

acceptor concentration and the improved device geometries exhibiting voltage drops

shown in Table 3.2 yield the second calculated curve in Fig. 3.13. This curve

presents the optimized I-V characteristics for an 8 µm device. Given the theoretical

improvement in I-V characteristics, we can estimate the potential improvement in

output power of the VCSEL, as demonstrated in Fig. 3.14. We expect the output

power to roll over at higher current levels than in the experimental curve due to a

reduced rate of heating in the active region and thus higher gain values at the similar

current levels. Moreover, increased current will contribute directly to the stimulated

emission and subsequently improve the output power of the device. Given a thermal

53

impedance value of 1.289 °C/mW and the LIV characteristics recorded previously,

we can derive a junction temperature – differential efficiency relationship [16]. We

can then apply this relationship to a device exhibiting the optimized

I-V characteristics from Fig. 3.12 in order to predict the differential efficiency at a

given current. Using this optimized device design we predict a 1.5 mW increase in

output power, a substantial improvement.

Figure 3.14: Perceived improvement in output power through electrical optimization. The calculations are made for an 8 µm aperture diameter at 20 °C.

By improving the I-V characteristics, we not only increase the absolute output

power, but we also increase the roll-over current of the device. Because the

resonance frequency of lasers is inherently based on the difference between the drive

and threshold currents, improving the roll-over will also serve to increase the

modulation bandwidth.

54


We present a methodology for TJ design and incorporation in single-mode LW-

VCSELs. Using band diagrams and the WKB approximation, we determine the TJ

layer thicknesses which optimize tunneling probability and optical loss due to the TJ.

We find that our present 20 nm n++-InP layer can be reduced to 10 nm without any

loss of tunneling probability.

Once we determine the physical dimensions of the TJ, we examine the effects

of varying the doping levels from our expected levels of 5x1019 cm-3 on the n-side

and 2x1020 cm-3 on the p-side and attempt to match experimental TJ results with

calculated curves. While it is evident from inspection that our experimental results do

not resemble characteristics of highly degenerate TJs, we quantify the discrepancy as

an order of magnitude reduction in acceptor concentration on the p++ side of the TJ.

Variations in donor concentration do not prove to have much effect on the operation

of InP-based TJs.

While our designed doping levels would yield low voltage devices, the TJs

would not support single-mode operation of VCSELs. An 8 µm aperture requires a

minimum resistivity of 6x10-5 Ω-cm2 to uniformly inject current into the active

region. This resistivity corresponds to an acceptor concentration of 5x1018 cm-3, more

than an order of magnitude less than our design levels. Given this optimized

resistivity and doping level, we calculate the I-V and L-I characteristics for an

optimized 8 µm device and predict devices operating well under 3 V and single-mode

output powers exceeding 3.5 mW.

55

References

[1] O. Boriclubecke, D. S. Pan, and T. Itoh, "Fundamental and Subharmonic Excitation for an Oscillator with Several Tunneling Diodes in Series," IEEE Transactions on Microwave Theory and Techniques, vol. 43, pp. 969-976, 1995.

[2] O. Kwon, M. M. Jazwiecki, R. N. Sacks, and S. A. Ringel, "High-

performance, metamorphic InxGa1-xAs tunnel diodes grown by molecular beam epitaxy," IEEE Electron Device Letters, vol. 24, pp. 613-615, 2003.

[3] L. Esaki, "New Phenomenon in Narrow Germanium Para-Normal-Junctions,"

Physical Review, vol. 109, pp. 603-604, 1958. [4] D. E. Mars, Y. L. Chang, M. H. Leary, S. D. Roh, and D. R. Chamberlin,

"Low-resistance tunnel junctions on GaAs substrates using GaInNAs," Applied Physics Letters, vol. 84, pp. 2560-2562, 2004.

[5] J. Yan, G. Ru, Y. Gong, and F. S. Choa, "Study of P-Type Carbon Doping on

In0.53Ga0.47As, In0.52Al0.2Ga0.28As and In0.52Al0.48As," Proceedings of SPIE, Applications in Photonic Technology 6, vol. 5260, pp. 446-449, 2003.

[6] T. A. Demassa and D. P. Knott, "Prediction of Tunnel Diode Voltage-Current

Characteristics," Solid-State Electronics, vol. 13, pp. 131-&, 1970. [7] S. M. Sze, Physics of semiconductor devices. New York: Wiley-Interscience,

1969. [8] M. Arzberger, M. Lohner, G. Bohm, and M. C. Amann, "Low-resistivity p-

side contacts for InP-based devices using buried InGaAs tunnel junction," Electronics Letters, vol. 36, pp. 87-88, 2000.

[9] M. H. Park, L. C. Wang, J. Y. Cheng, and C. J. Palmstrom, "Low resistance

Ohmic contact scheme (similar to mu Omega cm(2)) to p-InP," Applied Physics Letters, vol. 70, pp. 99-101, 1997.

[10] C. L. Chen, L. J. Mahoney, M. C. Finn, R. C. Brooks, A. Chu, and J. G.

Mavroides, "Low Resistance Pd/Ge/Au and Ge/Pd/Au Ohmic Contacts to Normal-Type Gaas," Applied Physics Letters, vol. 48, pp. 535-537, 1986.

[11] J. W. Scott, "Design, fabrication and characterization of high-speed intra-

cavity contacted vertical-cavity lasers," vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1995.

56

[12] N. Margalit, "High-Temperature Long-Wavelength Vertical-Cavity Lasers,"

in Electrical and Computer Engineering, vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 1998.

[13] J. Cheng, C. L. Shieh, X. D. Huang, G. L. Liu, M. V. R. Murth, C. C. Lin, and

D. X. Xu, "Efficient long wavelength AlGaInAs vertical-cavity surface-emitting lasers for coarse WDM applications over multimode fiber," Electronics Letters, vol. 40, 2004.







57

Chapter 4

High Speed Device Design and Optimization

A large contribution of this work to the field is in the development of design

methodologies for high-speed LW-VCSEL modulation performance at high

temperature. The inherent bandwidth of any laser structure is ultimately limited by

the relaxation resonance frequency (fr) of the second-order carrier-photon oscillation

defined as:

(1) ( )21

21

⎥⎦

⎤⎢⎣

⎡−= th

m

igo II

qVav

fη

π

where vg is the group velocity, ηi is the injection efficiency, a is the differential gain,

q is electron charge, Vm is the mode volume, I is the bias current and Ith is the

threshold current [1]. The modulation response rolls off sharply beyond fo, and the

bandwidth is generally taken to be the 3-dB down point, f3db = 1.55fo.

58

While fixed gain-mode offset devices such as Fabry-Perot lasers always lase

at the gain peak due to the small spacing between modes, variable gain-mode offset

devices such as Distributed Feedback Lasers (DFB) and VCSELs allow for a larger

design space due to the effect of the internal temperature on differential gain,

threshold current and rollover current. Assuming a constant ηi, the parameters within

our design space are Vm, a, and (I-Ith).

Since our goal is to design devices capable of driving 10 Gbit/s

communication systems between an ambient temperature range of 20 °C and 80 °C,

we define a theoretical f3db floor of 5.5 GHz. Unfortunately, driver electronics and

the advantage of filtering at the receiver render this metric unrealistic, and we take 7.5

GHz to be a more reasonable f3db floor. The focus of this chapter is to analyze the

impact of temperature on the various parameters in Eq. (4.1) and use the analysis to

maximize the inherent resonance frequency of our devices at high ambient

temperatures. Section 4.1 will take a brief look at the impact of cavity length on

modulation bandwidth. Sections 4.2 and 4.3 analyze threshold current and rollover

current design metrics respectively. Section 4.4 develops a model for differential

gain-cavity mode offset analysis. Any analysis which takes into account the gain

characteristics of the active region is based on calculated gain curves for our

particular active region provided by Dr. Joachim Piprek.

4.1 Cavity Length Optimization

59

If we perform our analysis over a constant aperture radius, the cavity length (L),

including the penetration depth into the DBRs, will be the only dimensional factor to

affect the mode volume, Vp, of the cavity. The constant aperture radius

approximation is legitimate in the analysis of SM devices since the radius will vary

between only 3.5 µm and 4.5 µm. The various layer lengths for first and second

generation devices are listed in Table 4.1.

Layer Length (µm) Top contact layer (n-type) 0.41 Cladding layer (p-type) 0.41 Bottom Contact Layer (n-type 0.41 Active Region (uid) 0.15 Top DBR (GaAs/AlGaAs) penetration depth (PD)

0.714

Bottom DBR (GaAs/AlGaAs) PD 0.715 Table 4.1: Length of individual layers in the 1st generation device structure. A full-wave at 1.3 µm in InP corresponds to a length of 0.41 µm.

The DBR penetration depth is approximated by [1]:

)tanh(

21

geff LL κκ

= (4.2)

where the reflection per unit length, κ, is defined as:

gL

mr2=κ (4.3)

and Lg defines the physical length, m defines the number of periods in the grating, and

2r defines the reflection per grating segment.

Fig. 4.1 shows the effect of various structural cavity length modifications on

the resonance frequency of the device. Table 4.2 describes each of the structures. All

bars are normalized to first and second generation devices (A) whose dimensions are

60

listed in Table 4.1. This structure includes three full-wave cladding and contact

layers, a half-wave active layer, and an additional 1.4 µm of penetration into the

GaAs/AlGaAs DBRs. Bar B shows the effect of reducing the p-cladding layer to half

its thickness and the structure in Bar C replaces one of the semiconductor DBRs with

a dielectric DBR. The smaller physical length of dielectric DBRs versus

semiconductor DBRs results in a smaller penetration depth. Based on equations 4.2

and 4.3, replacing a 25 period GaAs/Al0.92Ga0.08As output coupler with a 4 period

TiO2/SiO2 output coupler increases the reflection per grating from 14.6 % to 81.4 %

and reduces the DBR penetration depth from 714 nm to 283 nm.

Structure Characteristics A 3.5-λ lambda cavity, two semiconductor DBRs B 3-λ cavity, two semiconductor DBRs

C 3-λ cavity, one semiconductor DBR, one dielectric DBR

D 1.5-λ cavity, two semiconductor DBRs E 1.5-λ cavity, two dielectric DBRs

Table 4.2: Description of various structures and cavity lengths examined in Figure 4.1.

Figure 4.1: Variation in relaxation resonance frequency (fr) for various cavity lengths assuming that no other factors are present. All data are normalized to Structure A.

61

Implementing the two previously mentioned changes yields a 16 % increase in

inherent fr according to Figure 4.1. The combination of these two structural changes

allows us to achieve the high measured modulation bandwidth which we present in

Chapter 6. The chart also includes normalized comparisons to various 1.5-lambda

cavities incorporating both semiconductor and dielectric DBRs. These calculations

are shown for instructional purposes to demonstrate the possible advantage of

eliminating intra-cavity contacts, TJ layers, or the p-cladding layer. Unfortunately,

these devices cannot be driven as hard as the structures in Bars A-C due to higher

thermal impedance and increases in optical loss. Thus, inherent fr will saturate more

quickly than for structures A-C.

4.2 Rollover Current and Threshold Current Optimization

Threshold current and rollover current both vary with temperature in un-cooled,

variable gain-mode offset devices as a result of gain peak and cavity mode shifts with

temperature. Since the gain peak red-shifts more quickly than the cavity mode as the

active region temperature rises, devices employing room temperature (RT) negative

offset (gain peak blue-shifted with respect to the cavity mode) experience improved

high temperature characteristics. Since positive offsets are not suitable for high

temperature performance, all referred offset values from this point forward will be

presented as the absolute value of the RT negative offset.

62

4.2.1 Threshold Current Analysis

In our attempt to maximize high temperature modulation bandwidth, we first address

threshold current optimization with respect to temperature and gain-mode offset.

Figure 4.2 plots the active region temperature at which the gain-mode offset is zero

versus the RT gain-mode offset. The temperature at which the gain and mode are

aligned should correspond to the temperature at which threshold current is minimum.

Figure 4.2: The graph plots the active region temperature at which the gain peak and cavity mode come into alignment for a given room temperature gain-mode offset. The calculations are based on gain curves provided by Dr. Joachim Piprek.

Based on the data in Figure 4.2, we can plot the relationship between

threshold current and RT gain-mode offset. Figure 4.3 illustrates the variation in Ith

versus RT gain-mode offset at both 20 °C and 80 °C. The values are derived from the

steady-state current/carrier relationship below threshold [1]:

63

τη ththi NqV

I=

(4.4)

where V is the active region volume, Nth is the threshold carrier density and τ is the

carrier lifetime. We make the following substitution [1]:

(4.5) 32ththth

th CNBNANN++≈

τ

in which the first and third terms represent a combination of the non-radiative and

leakage recombination rates and the second term defines the recombination rate due

to spontaneous emission. The values for A, B, and C at the wavelength of interest

can be found in [1]. This simplification allows us to ignore the inherent dependence

of τ on Nth. We determine Nth at a given offset by generating a gain versus carrier

density curve at the mode wavelength and extracting N at the predetermined gth value

of 550 cm-1 [2]. Figure 4.3 shows a monolithic increase in Ith versus offset at 20 °C.

Since heating has minimal effect on the offset at RT, we would expect the gain to

decrease and threshold to increase as the offset increases and the gain peak and mode

move out of alignment at 20 °C. At 80 °C, on the other hand, we achieve a minimum

Ith at 20 nm RT gain-mode offset. The gain and mode do not come into alignment

until the offset approaches 20 nm.

64

Figure 4.3: Calculated Ith versus gain-mode offset at both 20 °C and 80 °C ambient temperature. A gain-mode offset of 0 nm corresponds to a lasing wavelength of 1280 nm.

4.2.2 Idiff Optimization

Now that we have an understanding of the relationship between threshold current,

internal temperature and offset, we can begin to optimize the maximum drive current

minus threshold, or Idiff. The presence of (I-Ith) in Eq. (4.1) implies that we should be

able to increase the relaxation resonance simply by driving the device to higher

current levels. This is only valid while the stimulated emission increases linearly

with increases in current. In the case of CW operation, internal heating of the active

region forces a sub-linear L-I characteristic and the relaxation resonance saturates

close to thermal roll-over. Our first goal then is to determine the current at which

rollover takes place.

65

4.2.2.1 Development of L-I Model

We address this issue by developing a simple L-I model. A CW (includes heating

effects) L-I curve can be thought of as a superposition of several points from various

pulsed L-I curves (no heating effects). To first order, we can assume the differential

efficiency (ηd) of the pulsed curves to be [1]:

mi

mid αα

αηη

+=

to be equal assuming that ηi and αi do not change with temperature. The threshold of

a particular pulsed curve is determined using the same method used in Section 4.2.

Figure 4.4 visually demonstrates how a CW curve can be formed from several pulsed

L-I curves.

Figure 4.4: Example of a continuous-wave (CW) L-I characteristic derived from a series of pulsed L-I curves. The figure also shows the possibility of increasing ηd in the CW case versus the pulsed case if offset engineering is employed to initially reduce the effective Ith with drive current.

66

In actuality, ηd will reduce as temperature increases. We assume a 2.0 %

reduction in ηd for a 10 °C increase in active region temperature. Figure 4.5 displays

a flow chart which describes the method used to generate the calculated CW L-I

curves. We have already stated that we can evaluate the CW Ith value for a given

ambient temperature and offset and that we will hold ηd constant. With prior

knowledge of thermal impedance and the I-V characteristics of the device, we

increment the current from threshold and calculate the internal temperature rise.

Given the temperature rise, we can calculate the new lasing wavelength and the new

carrier density required to sustain lasing. We can then calculate a new ‘effective’ Ith.

The new Ith value corresponds to a new pulsed curve in Figure 4.4. With knowledge

of the incremented current level, the new effective Ith, and ηd, we can calculate the

next output power data point. We then increment the current and re-calculate power.

67

Calculate Initial Ith

Increment Current

Calculate Power Dissipation

Calculate Temperature Rise

Calculate New Nth

Calculate and Store New Output Power

Calculate New ‘Effective’ Ith

Figure 4.5: Flowchart explaining procedure to calculate theoretical L-I characteristics given knowledge of Ith, ηd, and Rth..

It is important to note that the model does not use self-consistent methods and

should be taken only as a first order approximation. In any case, it provides an

adequate design baseline, as will be shown in Chapter 6.

4.2.2.2 L-I Model Calculations

Now that we have developed a model to calculate L-I curves, we begin to analyze the

variations in output power and Idiff characteristics with changes in offset, ambient

68

temperature, and differential resistance. Recall that our goal is to maximize fr at high

ambient temperature, so we analyze the calculated results at 20 °C and 80 °C.

Figure 4.6 shows calculated L-I curves for 8 µm devices operating with 330 Ω

differential resistance (1st generation devices) at 20 °C. The gain-mode offset for the

curves varies between 0 nm and 40 nm. Similar curves are shown for 80 °C ambient

temperature in Figure 4.7. All offsets stated in the curves are RT offsets. The curves

do not exhibit significant rollover variation with offset. The output power is fairly

constant versus offset at 20 °C. We calculate a maximum output power of ~ 2.27

mW and calculate less than 1% change between 0 nm and 40 nm, we calculate a 10 %

change in maximum output power between 0 nm and 40 nm offset devices at 80 °C.

From these simulations, we gather that internal heating dominates offset in

determining roll-over position.

Figure 4.6: Theoretical L-I curves for 8 µm aperture devices operating with 0, 20, and 40 nm gain-mode offsets at an ambient temperature of 20 °C. Rd for all curves is 330 Ω.

69

Figure 4.7: : Theoretical L-I curves for 8 µm aperture devices operating with 0, 20, and 40 nm gain-mode offsets at an ambient temperature of 80 °C. Rd for all curves is 330 Ω.

To examine the effect of reduced heating, we reduce the differential resistance

of the devices from 330 Ω to 100 Ω (3rd generation devices) and calculate the changes

in rollover position and output power. Figure 4.8 shows the effect of reducing the

differential resistance at 20 °C. Figure 4.8a shows the variation in calculated L-I

characteristics versus offset and Figure 4.8b compares 40 nm offset devices operating

with 100 Ω and 330 Ω differential resistance. The theoretical maximum output power

for all offsets at 20 °C improves to over 3 mW. The maximum output power for 40

nm devices at 80 °C improves to 1.35 mW. More importantly (for the purposes of

modulation) the rollover current increases by 3 mA and 2.5 mA at 20 °C and 80 °C

respectively. The impact of reducing differential resistance is more significant than

offset design on the current and power characteristics of the devices.

70

(a) Tambient = 20 °C, Rd = 100 Ω (b) , Tambient = 20 °C, RT offset = 40 nm Figure 4.8: Comparison of theoretical L-I curves with varying offset and Rd,at a stage temperature of 20 °C.

(a) Tambient = 80 °C, Rd = 100 Ω (b) , Tambient = 80 °C, RT offset = 40 nm Figure 4.9: Comparison of theoretical L-I curves with varying offset and Rd at a stage temperature of 80 °C.

71

4.2.2.3 Idiff Analysis

Thus far, we have been calculating the output power and rollover characteristics of

the devices. While the analysis in the previous sub-sections presents us with an idea

of how the laser characteristics vary with offset and temperature, the exact parameter

we look to define from Eq. (4.1) is (I-Ith). In constructing the L-I model defined in

Section 4.2.2.1, we define an ‘effective’ Ith value for each data point and thus define

the difference between drive current and effective Ith, defined as Idiff. We can

represent Idiff as a function of I. Using the Ith value that corresponds with a given I

value when evaluating (I-Ith) in the Eq. (1) ensures that all current above the effective

Ith contributes linearly to stimulated emission. Under these conditions, the onset of

heating effects and thermal rollover should result in the saturation of Idiff during the

course of a CW L-I sweep.

The relationship between the maximum Idiff and offset at 20 °C is shown in

Figure 4.10. As with maximum output power and roll-over, internal heating

dominates the Idiff characteristics. We see little variation in Idiff between 0 nm and 40

nm, but we do observe a 50% improvement in Idiff when we reduce Rd from 330 Ω to

100 Ω. Figure 4.11 shows maximum Idiff versus offset characteristics at 80 °C. The

characteristics show a similar 50% improvement in maximum Idiff as we saw at 20 °C.

But unlike the 20 °C case, employing a 40 nm offset improves the maximum Idiff by

13% over the 0 nm design. An improvement of 13% in Idiff will improve f3db on the

order of 0.5 GHz at modulation bandwidths of interest.

72

Figure 4.10: Idiff versus gain-mode offset for 8 µm devices at 20 °C ambient temperature. The figure shows curves for Rd = 100 Ω and 300 Ω.

Figure 4.11: Idiff versus gain-mode offset for 8 µm devices at 80 °C ambient temperature. The figure shows curves for Rd = 100 Ω and 300 Ω.

73

4.3 Differential Gain Optimization

Finally, we calculate the effect of temperature and offset on the differential gain of

the structure. Differential gain is defined as the change in gain for a given change in

carrier density, or dg/dN. It serves as an optical capacitance. The higher the

differential gain, the more quickly carriers contribute to stimulated emission and thus

the device will have higher inherent modulation characteristics. Since the gain-carrier

density relationship varies with both temperature and wavelength, the thermal and

offset parameters will have an effect on the differential gain of the device. Moreover,

since the internal temperature and operating wavelength of a device both rise as the

operating current and dissipated power increase, the differential gain of device at a

constant stage temperature will also vary with operating current.

Figure 4.12 shows calculated differential gain versus wavelength

characteristics for active-region temperatures ranging from 20 °C to 180 °C. The

gain along all curves is fixed at the gth value of 550 cm-1 in order to show the

differential gain values at threshold. Slight increases in gth at higher temperatures did

not impact the results of these calculations.

74

Figure 4.12: Differential gain versus wavelength at internal temperatures between 0 °C and 180 °C. All calculations are based on gain curves which demonstrate a RT gain peak of 1.28 µm. The wavelength at which differential gain is maximum red-shifts as internal temperature increases.

The differential gain drops rapidly with increasing wavelength at low

temperatures. This is to be expected since the short-wavelength side of the gain peak

generally shows higher differential gain than the long side. As the temperature

increases, the differential gain peak shifts to higher wavelength. This takes place in

conjunction with the red-shift of the gain peak at higher temperatures.

Based on the calculations in Figure 4.12, we can derive a differential gain

versus active region temperature relationship for various offset designs, shown in

Figure 4.13. Each curve is superposition of several points from the curves in Figure

4.12 assuming a 0.09 nm/°C red shift of the cavity mode wavelength with

temperature.

75

Figure 4.13: Differential gain versus active region temperature for various room temperature gain-mode offset designs. Increasing the offset increases the internal temperature at which differential gain is maximum.

While we can achieve maximum differential gain values of 19x10-16 cm2 with

0 nm offset, the large differential gain roll-off and output power decrease with

temperature will result in modulation response non-linearities. As we increase offset,

the maximum differential gain decreases, but we observe a more steady response.

We can relate the active region temperature in Figure 4.13 to Idiff based on the

Rd and I-V characteristics of our devices and describe the relationship between

differential gain and Idiff at various offsets. Figure 4.14 demonstrates this relationship

at an ambient temperature of 20 °C. It is once again clear that at low temperatures,

the offset does not have much impact on performance.

76

Figure 4.14: Differential gain versus gain-mode offset for varying drive currents at Tambient = 20 °C. The aperture diameter is 8 µm.

Figure 4.15 demonstrates the differential gain – offset relationship at 80 °C.

Here, we discover that we can improve the differential gain at high drive currents by

more than 10% by incorporating a large offset design into the structure.

Figure 4.15: Differential gain versus gain-mode offset for varying drive currents at Tambient = 80 °C. The aperture diameter is 8 µm.

77

4.4 Complete Model

Now that we have calculated differential gain, threshold current, and rollover as a

function of temperature, offset, and differential resistance, we can calculate

theoretical Modulation Current Efficiency (MCEF) characteristics, which plot

resonance frequency versus (I-Ith)1/2, using Eq. (4.1).

Standard MCEF characteristics for fixed gain-mode offset devices tend to

show linear characteristics until the relationship begins to saturate. According to Eq.

(4.1), this is reasonable so long as differential gain is nominally constant. But as we

have shown throughout this chapter, the differential gain and drive current

characteristics will vary versus temperature for variable gain-mode offset devices

such as un-cooled VCESLs.

Figure 4.16 shows calculated MCEF characteristics for an 8 µm device with

Rd of 330 Ω at 20 °C stage temperature. The curves extend only as far as roll-over on

the devices which was determined in Section 4.2.2.3 to be the limit of stimulated

emission increase. For devices designed with offsets less than 30 nm, we observe

classic linear MCEF properties. Devices with a 30 nm offset begin to show super-

linear properties which become even more prominent on 40 nm devices. The

experimental data points in Figure 4.16 are measured Relative Intensity Noise (RIN)

relaxation resonance data points from actual devices. The implication of super-linear

characteristics is that the square root dependence of fo on (I-Ith) in Eq. (4.1) can be

78

made linear by designing the structure such that differential gain rises with increased

temperature.

* Measured RIN Data for 40 nm offset device

Figure 4.16: Calculated resonance frequency (fo) vs. (I-Ith)1/2 for various gain-mode offsets on an 8 µm device operating with Rd = 330 Ω at an ambient temperature of 20 °C. Stars represent measured points from RIN analysis on an actual 8 µm device structure employing a 40 nm gain-mode offset at 20 °C. The stage temperature during the measurement is 20 °C. The measured data fits the 40 nm calculated characteristic very well.

While the maximum fr is lower for higher offset devices at room temperature,

the curves in Figure 4.17, calculated at 80 °C ambient temperature, show that the

MCEF characteristics become very similar at higher ambient temperatures. When

coupled with the higher output power associated with large offset devices, we begin

to understand the value of offset engineering.

79

Figure 4.17: Calculated resonance frequency (fo) vs. (I-Ith)1/2 for various gain-mode offsets on an 8 µm device operating with Rd = 330 Ω at an ambient temperature of 80 °C.

We can calculate theoretical values for the 3db modulation bandwidth of these

devices by using the relationship f3db = 1.55*fr [3]. This relationship assumes low

damping. Recall that we target f3db values of 7.5 GHz for 10 Gbit/s operation.

Figures 4.18 and 4.19 show that all offsets will achieve 7.5 GHz between 20 °C and

80 °C.

80

Figure 4.18: Calculated 3-db bandwidth (f3db) vs. (I-Ith)1/2 for various gain-mode offsets on an 8 µm device operating with Rd = 330 Ω at an ambient temperature of 20 °C.

Figure 4.19: Calculated 3-dB bandwidth (f3db) vs. (I-Ith)1/2 for various gain-mode offsets on an 8 µm device operating with Rd = 330 Ω at an ambient temperature of 80 °C.

81

Figure 4.20: Zoom in of Figure 4.18. The figure more precisely shows the variation in 3-db bandwidth at high drive currents.

Figures 4.21 and 4.22 show the effect of reducing Rd from 330 Ω to 100 Ω.

First, the maximum (I-Ith) value increases due to the reduction in internal devivce

heating and improvement in thermal roll-over. But we also see a decrease in the

super-linearity of large offset devices. Because the device heats up more slowly at

with lower Rd, the rate of differential gain with drive current will decrease for large

gain-mode offset devices. The increase in Idiff more than compensates for this effect

and results in higher fr values than the 330 Ω case. The improvement also improves

the maximum fo at 80 °C from 7 GHz for 330 Ω devices to 8.5 GHz for 20 nm and 30

nm offset devices operating with Rd = 100 Ω devices.

82



83


One of the main objectives of this thesis is to maximize modulation bandwidth at high

temperatures. Based on the fundamental equation for fr, we design methods to

minimize Ith, and maximize the rollover current and differential gain. We find that at

80 °C ambient temperature, designs employing gain-mode offset values between 20

nm and 30 nm show minimum Ith at 80 °C.

We then develop an L-I model to calculate thermal L-I rollover and find that

while rollover doesn’t change significantly for offset variations, reducing Rd will

significantly enhance rollover. This conclusion will be confirmed in Chapter 6.

Using calculated gain curves, we develop a differential gain model which allows us to

design the gain-mode offset so that the differential gain is fairly linear over the

temperature range of interest.

Finally, we incorporate each of the previous calculations into a complete

model to determine the theoretical MCEF characteristics of our devices. In the

process, we find that by using proper gain-mode offset design, we should observe

super-linear MCEF characteristics. This hypothesis is confirmed with RIN data from

an actual device. Now that we have completed all device design and modeling, we

turn our attention to a description of device fabrication.

84

References

[1] L. A. Coldren and S. W. Corzine, Diode lasers and photonic integrated

circuits. New York: Wiley, 1995. [2] E. S. Bjorlin, J. Geske, M. Mehta, J. Piprek, and J. E. Bowers, "Temperature

dependence of the relaxation resonance frequency of long-wavelength vertical-cavity lasers," IEEE Photonics Technology Letters, vol. 17, pp. 944-946, 2005.

[3] J. E. Bowers, "High-Speed Semiconductor-Laser Design and Performance,"

Solid-State Electronics, vol. 30, pp. 1-11, 1987.

85

Chapter 5

Device Fabrication

This work has introduced several new fabrication techniques as well as improvements

on previous wafer-bonding processes. The buried aperture process on wafer-bonded

structures described in Section 5.1 is new to this work while the wafer bonding

preparation and handling techniques presented in Section 5.2 went through several

iterations before we arrived at an exceedingly robust and simple process for 3rd

generation quarter-wafer bonding. Sections 5.3 – 5.5 describe the subsequent

fabrication steps post aperture definition and wafer bonding.

5.1 Lithographic Aperture Definition and Re-growth

Until now, UCSB wafer bonded LW-VCSELs defined current and mode confinement

structures using etched pillars and lateral oxidation. This work is the first to

incorporate buried hetero-structure re-growth techniques with wafer bonding. The

procedure allows for precise lithographic aperture definition. The process is

86

significantly easier to control and characterize than lateral techniques such as wet

oxidation and undercut etching. All steps regarding aperture definition and re-growth

are performed on the InP-based active region. Figure 5.1 illustrates the process to

define the buried hetero-structure TJ aperture. All of our active regions were grown

by MOCVD in order to maximize the gain and minimize material loss. In order to

maximize the doping in the TJ, we re-grow the TJ by MBE above the MOCVD

grown active layer. Technologies now exist to grow entire structures by either MBE

or MOCVD leaving the TJ re-growth unnecessary.

Pattern and etch tunnel junction

Re-grow InP n-contact layer

Figure 5.1: Procedure to lithrographically define and bury TJ undercut aperture structures.

We coat the sample with thin photo resist (AZ 4110) and then pattern and

develop circular mesas of various sizes into the resist. We use a 3:1 H3PO4:HCl

solution to etch the 20 nm InP layer of the TJ and a 1:1:10 H2SO4:H2O2:H2O solution

cooled to room temperature to etch the 10 nm AlInAs layer. Both of these etches are

quick dips so as not to under-etch the apertures and reduce the diameter. We use an

etch time of 5 seconds for each. While the actual etch time for ~10 nm for each

material is less than 5 seconds, the time is sufficient as not to under-etch the aperture

any noticeable amount.

87

Once the TJ aperture is defined, we prepare the sample for the 400 nm re-

growth of the InP contact layer. We use MOCVD to perform the contact layer re-

growth. Sample preparation before re-growth involves a Buffered Hydrofluoric

(BHF) acid dip and a dilute sulfuric acid dip to remove oxides and organics that may

accumulate on the sample during wafer transfer.

A significant problem arises during the two re-growth process that reduces

device yield. Figure 5.2(a) shows the wafer morphology after both re-growth steps.

Bump-like defects are visible all over the sample. Some even reside directly on top

of the aperture. Figure 5.3(b) shows a zoomed out image of the sample after both re-

growth steps. The oval area on the left which is devoid of defects did not receive was

masked during the TJ re-growth by a holding clip. Since the entire sample is exposed

during the contact layer growth, the defects, while not visible after the 30 nm TJ re-

growth, seem to originate during the TJ re-growth and propagate during the

subsequent contact layer re-growth.

a) Visual of active region after CL regrowth (b) Zoomed out visual of (a) Figure 5.2: Micrographs of active region post TJ and contact layer (CL) re-growth. The picture in (a) is a close up, while (b) shows a large region of the wafer including a region (left side) which underwent CL re-growth but not TJ regrowth.

88

While the two re-growth process is not feasible for manufacturing, processes

incorporating a single growth active region/TJ structure should see significantly less

defect density than the TJ re-growth process. Thus, applying a single re-growth

would still allow for a lithographically defined and buried aperture.

5.2 Wafer Bonding Process Development

Wafer bonding techniques have been used extensively in the last 15 years for a

variety of applications. Flip-chip, anodic, and epoxy bonding techniques are used

readily in manufacturing applications. Plasma assisted wafer bonding techniques

have been studied in great detail recently and have been used recently in the

fabrication of Silicon evanescent lasers [1, 2]. Direct wafer bonding, a process in

which we place two semiconductor samples in direct contact and perform a high

temperature anneal on the contacted samples to facilitate mass transport and covalent

bonding at the interface, has been used to fabricate hybrid Si/InGaAs Avalanche

Photo-detectors (APD) and GaN/GaAs Heterojunction Bipolara Transistors (HBT) [3,

4]. Much of the recent focus on direct wafer bonding has been to develop high

performance LW-VCSELs [5-7].

Wafer bonding permits the synthesis of highly lattice-mismatched materials

without incurring the defect density observed after epitaxial growth of lattice-

mismatched layers. All defects associated with direct wafer-bonding are limited to

the dangling bonds at the bonded interface; these defects do not thread through the

material [8]. Thus, bonding allows us to incorporate high gain InP based active

89

regions with high index contrast and high thermal conductivity GaAs/AlGaAs DBRs

to maximize LW-VCSEL performance. In our work, wafer bonding also allows us to

process the active region and DBRs individually prior to bonding. Thus, we can

modify a standard growth to design for a wide range of wavelengths and gain-mode

offsets. The next few sub-sections will address several issues related to bonding, e.g.

bonding fixtures, sample treatment before bonding, furnace conditions, and the bond

procedure variation between 1st and 2nd generation devices and 3rd generation devices.

5.2.1 Bonding Fixtures

The purpose of the bond fixture is to hold the samples together during the high

temperature bond anneal at a given pressure. Fixture design is critical to limiting

sliding of the sample parallel to the bottom plate. Sample sliding could potentially

result in pressure non-uniformity. Fixture design is also critical in determining the

sample load time. Because native oxide formation will negatively affect bond

quality, we attempt to minimize the time between removing the samples from a

reducing solution and placing the sample in the bond furnace. The bonding fixtures

used prior to 1st and 2nd generation devices are show in Figure 5.3(a) while 1st and 2nd

generation fixtures are shown in Figure 5.3(b), designed by Dr. Vijay Jayaraman. All

fixtures are made of graphite to ensure that no particulates disassociate during the

high temperature anneal from the fixture and deposit between the samples. The key

improvement from fixture A to fixture B is the addition of a graphite sleeve. The

sleeve includes a 1.44 cm2 opening to ensure that the samples cannot slide a large

90

distance while also facilitating simple placement and removal of the sample sizes

between 0.64 cm2 and 1.0 cm2. In addition to the sleeve, we also remove the

depression in the bottom plate. Graphite will tend to become non-uniform with large

a) Early bonding fixtures (b) Re-designed bonding fixtures Figure 5.3: Early generation and re-designed bond fixtures. The illustration in (a) shows fixtures which require an intermediate Si wafer due to graphite roughness. The illustration in (b) displays fixtures, redesigned by Dr. Vijay Jayaraman, which allow fixture lapping for smoothness and incorporate a sleeve so that samples do not slide laterally during the process

pressure application. An uneven fixture plate will cause pressure non-uniformities

and sample cracking due to large pressure application over small areas. The

depression in Fixture A requires a third sample which can be replaced periodically.

We choose to use Si. Adding a third sample to an already questionable design

increases sliding uncertainty even further. Removing the depression in fixture B

allows us to periodically planarize the bottom plate by lapping methods. Because

much care and patience must be taken to ensure that samples do not slide in fixture A,

the sample load process can take far longer than it will on fixture B. Once again, a

91

key component of this work is to simplify the bond process to a level which can be

used in large-scale manufacturing.

5.2.2 Sample Preparation

Much work has been done on characterizing optical and electrical properties of the

bonded interface for different surface preparation techniques [9]. Because we are not

concerned with current conduction through the bonded interface, we can eliminate

preparation techniques which are unnecessary to realize low-voltage bonded

interfaces.

5.2.2.1 DBR Defect Removal

Under these conditions, surface uniformity becomes the most significant factor in

determining bond quality and oval defects on MBE grown GaAs/AlGaAs DBRs

limits the bond yield. The oval defects are thought to be Ga-rich and can range as

high as 10 µm. Attempting to bond samples with a large density of these defects

(100/cm2) will result in a bond yield of ~ 0%. To eliminate the large oval defects, we

spin resist on the DBR and expose defects individually using a high magnification

microscope. This method was originally developed at Gore Photonics. While the

Ga-rich defects will not etch directly, we undercut the defects from the surface of the

wafer using 1:5:15 H3PO4:H2O2:H2O which etches GaAs at ~ 1.5 µm/minute. Figure

5.4 shows the DBR defect removal process. The size of the oval defects are

exaggerated for purposes of instruction. While the process seems laborious, the

92

actual defect density is generally on the order of 10/cm2. Morever, manufacturing

processes can automate this process to eliminate the time lag that the process may

cause.

Spin thick photo resist (3 µm) onto DBR

Expose defects individually using microscope

Underetch away defects

5.2.2.2 Bond Channels

Bond channel processes have been clearly defined and explained in prior UCSB

VCSEL publications [5]. The channels, defined prior to bonding, provide an escape

path for trapped particulates and gasses during a wet bond process which is defined in

Section 5.2.2.3. We have determined that channels as shallow as 7.5 nm provide

sufficient gap thickness to eliminate air and gas bubble formation that arise during

wet bond processes.

For our process, the InP contact layer re-growth on the patterned TJ leaves

gaps large enough to extract intermediate materials during the bond. Thus, the first

bond does not require any additional channel processing. For the second bond step,

we pattern 10 µm width channels at a 400 µm pitch in grid formation. We then etch

the channels into the remaining layers of the InP/InGaAsP SL using 3:1 H3PO4:HCl

and 1:1:10 H2SO4:H2O2:H2O for 20 seconds each to etch the InP and InGaAsP

respectively. While each layer is only 7.5 nm, we over-etch to ensure that we pass

Figure 5.4: GaAs/AlGaAs DBR defect removal process courtesy of Dr. Jonathon C. Geske.

93

through the layer. Moreover, because the channels are a large distance from the

devices (~ 200 µm), the undercut arising during the over etch will have no effect on

the devices.

5.2.2.3 Wafer Cleaning, Oxide Removal, and Load Process

tion during the bond

ist spun on the

Foreign particulates can cause non-uniform pressure applica

process. They also minimize the contact area during the bond. Simple species like

dust can have detrimental impact on bond quality. For that reason, all samples that

will be bonded undergo a simple solvent swab clean prior to bonding. We choose to

use acetone, but there is no evidence to suggest that acetone has any advantages over

methanol. We first apply a gentle acetone spray, and then stroke the square sample

with a cotton swab twenty times in each direction. We apply only gentle pressure to

ensure that the sample does not break. Most importantly, we begin each stroke with

the swab in the middle of the sample and move the stroke towards the edge, thus

removing any foreign particulates from the sample. The particulates we speak of

could be remnants of semiconductor from cleaning or general contamination from the

working environment. The cotton swab will often leave trace amounts of cotton

residue which can be easily removed by a subsequent acetone spray. Finally, we

apply isopropanol to the sample to remove acetone from the surface.

Following the solvent clean, any sample that has had res

surface, be it for defect removal or channel formation, undergoes an O2 plasma clean

94

for 20 seconds at 100 W and 300 mTorr. This descum step eliminates hydro-carbons

which may remain from preceding steps involving polymers.

We then proceed to eliminate native oxides from the sample surface by

immersing the samples in BHF for 10 seconds followed by an ammonium hydroxide

soak (NH4OH) for 2 minutes. We use the two step process because the general

cleanroom facilities and the bond system are in separate buildings. Thus, the more

aggressive BHF dip eliminates any native oxides prior to removing the samples from

the cleanroom environment and the NH4OH dip, situated next to the bond furnace,

removes any oxides formed during wafer transport. We learned during 3rd generation

process development that the BHF dip is not necessary for devices which do not pass

current through the bonded interface when the cleaning environment and bond

furnace are in a conjoined low contamination environment.

We transfer the samples directly from NH4OH to methanol and bring the

samples into contact while both samples are still wet. This process prevents native

oxides from forming on the surface. The samples are then placed in the sleeve in

Figure 5.3b. Pressure application on the samples is applied by way of torque on the

screws. We apply 125 N of force on the pressure dome. Assuming flat sample

surfaces and 8 mm x 8 mm sample sizes, 125 N corresponds to a pressure of 2 MPa.

The bond fixture is now ready to be placed in the furnace.

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5.2.3 Furnace Conditions

We use a converted Liquid Phase Epitaxy (LPE) furnace to perform our bonds

although any pump-purge system which can hold at high temperatures (650 °C) for an

extended period of time (> 60 minutes) is sufficient. The rest state of the furnace tube

includes a continuous flow of house supplied nitrogen (N2) and the system evacuates

using a Venturi pump. The basic bond process is to load the sample, close the

chamber, evacuate the chamber to 0.1 atm, purge the system with N2 to 1 atm and

then begin the temperature cycle. The evacuated pressure of 0.1 atm is the limit of

our Venturi pump and has been sufficient for our devices as well as devices which

pass current through a bonded interface [5].

The standard temperature cycle includes a ramp rate of 85 °C per minute from

room temperature to the bond temperature (550 °C – 580 °C), a 20 – 30 minute hold

at that temperature, and a 10 °C per minute ramp down from the bond temperature to

room temperature. The 10 °C ramp down serves as the optimal point between

holding the sample at high temperature for too long which in our case may degrade

the TJ and cooling the sample down too quickly which may cause cracking due to

coefficient of thermal expansion (CTE) mismatch.

The three most important parameters of the bond seem to be the pressure,

bond temperature, and temperature ramp down rate. Increasing pressure and

temperature can compensate for surface non-uniformities but also may damage the

sample physically, electrically, and optically. We find in 1st and 2nd generation

96

devices that 2MPa, 570 °C, and a 10 °C/min ramp down rate provide sufficient bond

yield while maintaining structural and TJ integrity.

5.2.4 Bond Procedure Variation between Generations

Several changes were made between 1st and 2nd generation bond processes and the 3rd

generation bond process. Most of the processes mentioned previously apply to 1st and

2nd generation bonding. While certain aspects of 3rd generation bonding cannot be

disclosed due to confidentiality, we do note several changes which simplified the

bond process and resulted in ~ 100 % quarter-wafer (2 inch) structural bond yield.

First, as mentioned in Section 5.2.2, the cleaning facilities and bond furnace

were located in a conjoined low-contamination environment. The cleaning procedure

involved only a solvent swab clean, an O2 descum, a 2 minute NH4OH soak, and

sample contact in methanol. The samples were then ready for load. The entire

process, from cleaving the individual wafers to loading the samples in the furnance,

was reduced to under 15 minutes.

Next, we mitigate CTE mismatch issues by including a soft graphite foil over

which the samples could slide. We incorporate the foil in an effort to reduce cross-

hatch marks due to stress at the interface.

Finally, the 3rd generation fixtures allowed us to apply variable pressure

during the thermal cycle as opposed to the constant pressure applied by the fixture in

Figure 5.3b. We successfully eliminated cross-hatch features on the entire bonded

sample by removing pressure application during the temperature ramp down.

97

5.3 1st Generation Fabrication Techniques

The fabrication process for 1st generation devices employ primarily wet etches,

silicon nitride passivation and standard electron-beam (E-beam) contact deposition.

The fabrication process involves a top DBR mesa etch, ring contact deposition around

the DBR, contact layer isolation, a self-aligned bottom intra-cavity contact, nitride

passivation, airbridge definition and pad metal evaporation. Figure 5.5 visually

describes the process. The next three sub-sections describe the steps involved in each

process.

Pattern and etch DBR using wet etch process

Deposit ring contact, isolate TJ aperture

Wet etch down to CL, deposit contact

Deposit and pattern SiN to passivate surface

Form PMGI airbridge, deposit pad metal on nitride

Figure 5.5: Process flow for 1st generation devices incorporating primarily wet etches.

98

5.3.1 Top DBR Mesa Definition and Ring Contact Deposition

The first step after both bonds and substrate removals are complete is to define the

top DBR mesa. The mesa must be aligned to the TJ apertures which were defined

prior to the contact layer re-growth. In order to see through the thick DBR stack, we

use infrared contact alignment with backside illumination. The 50 µm diameter

mesas are patterned onto 3 µm thick AZ 4330 photo-resist and etched in 1:5:15

H3PO4:H2O2:H2O for ~ 4 minutes. Because the etch propagates from the center of the

wafer to the edge, interference patterns emerge during the etch which correspond to

the temporal difference in etch depth. The etch is selective over InP, and thus, the

interference patterns will disappear when the etch is complete. Although the etch is

isotropic, the large size of the mesa versus the 5 µm – 20 µm TJ apertures allows us to

over etch without reducing the width of the mesa to the mode width.

After etching the DBR mesa, we deposit a Ge/Au/Ni/Au ring contact around

the DBR with respective layer thicknesses of 260 Å, 540 Å, 200 Å, and 2000 Å and

an inner contact radius of 25 µm. We use an E-beam evaporator for the evaporation.

The outer contact radius is 35 µm. This leaves a contact area of ~ 1900 µm2. We use

a two coat polymer layer to pattern the contact. The first layer is SF11 PMGI which

has an approximate thickness of 1 µm. On top of the PMGI is 3 µm AZ 4330 photo-

resist. We generate the pattern in the photo-resist using contact alignment and expose

the PMGI in a UV setup. The diffraction of light from the edge of the photo-resist

produces sufficient undercut for easy lift-off. We anneal the metal at 420 °C for 30

seconds to generate ohmic contacts.

99

5.3.2 Contact Layer Isolation and Self-Aligned Bottom Contacts

The next step is to isolate the contact layer. This is done by etching a mesa into the

InP contact layer using 3:1 H3PO4:HCl for 60 seconds. The etch will stop on a

InGaAsP SL layer resting atop the InP p-cladding layer. The mesa diameter and

depth are 35 µm and 4100 Å respectively. Again the mesa is patterned into AZ 4330

photo-resist.

After contact layer isolation, we pattern the 46 µm inner radius bottom intra-

cavity contacts into AZ 4330 and etch through the remaning InP/InGaAsP SL layers,

the InP p-cladding layer and the AlInGaAs active layer. This step proves to be the

most troublesome and is improved in the 2nd generation process by incorporating RIE

dry etching. The several alternations between 3:1 H3PO4:HCl etchant for InP layers

and cooled 1:1:10 H2SO4:H2O2:H2O for quaternary layers is inefficient and hardly

repeatable. Several profilometer measurements are required between etches to ensure

that the wet etch removed the necessary layers. Because 7.5 nm SL layers are too

thin to resolve on our profilometer setup, we can only resolve the thicker cladding

layers and it is often difficult to distinguish which layer has not etched properly.

The advantage of the wet etch is that no double layer resist or image reversal

is necessary for metal lift-off due to the natural undercut of the wet-etch, thus

allowing for a self-aligned contact deposition. The same contact composition,

evaporation process, and anneal is used for the bottom contact that is used for the top

ring contact.

100

5.3.3 Passivation, Airbridge Definition and Bond Pad Formation

At this stage in the process, semiconductor formation is complete and no further

etches are necessary. Thus, the next step is to deposit 1600 Å of silicon nitride (SiN)

on the entire sample and open nitride holes over certain regions of metal. We deposit

the SiN using a Plasma-Enhanced Chemical Vapor Deposition (PECVD) system and

etch the SiN using a Technics PEII system equipped with CF4 gas. The etch

conditions are 100 W at 300 mTorr for 4 minutes. Were we to etch smaller features,

we would use an RIE system to ensure an anisotropic etch, but for our feature sizes

the simplicity and speed of use of the PEII system proved paramount.

While the bottom n-metal is large enough to probe, the top ring contact is too

small to probe directly so we affix a bond pad to the ring contact. The bond pad will

rest on the SiN which sits atop the bottom contact layer. In order for the metal to

reach the top ring contact, we pattern an SF11 PMGI airbridge prior to bond pad

metal evaporation. We pattern the PMGI bridge using the same process used for

liftoff of the ring contact and reflow the PMGI for 20 seconds at 250 °C to achieve a

smooth gradient between the nitride layer and the ring contact layer.

Finally, we deposit a 50 Å titanium (Ti) layer, 200 Å Platinum (Pt) layer, and

5000 Å Gold (Au) layer to form the bond pad metal. Since this metal layer is not

making contact with semiconductor, no anneal is necessary. The large thickness is

for potential wire bonding and packaging of devices. Figure 5.6 shows an aerial view

of a complete device.

101

Figure 5.6: Top view micrograph of a complete device. The inner ring shows the top DBR and ring contact. The narrow width of metal just below the ring passes over the PMGI airbridge and connects the ring contact with a bond pad.

5.4 2nd Generation Fabrication Techniques

The layer structure for 2nd generation devices is analogous to the 1st generation so we

will not describe fabrication steps in detail. Instead, we will describe any changes

that were made between the first and second generation processes. The key changes

are transitions to RIE dry etching of the DBR and active region mesas and bond pad

isolation.

5.4.1 Top DBR Definition

Because 2nd generation devices are designed for high speed performance, we reduce

all mesa geometries to minimize the parasitic capacitance of the devices. In order to

102

reduce the inner contact radius of the top ring contact, we reduce the top DBR mesa

to a 20 µm diameter. The isotropic wet etch of a 6 µm DBR used in the 1st generation

process will leave a DBR width too small to support the lasing mode. Thus we

employ a chlorine (Cl2) based dry etch to define the DBR mesa. We tried several

etch masks and etch conditions in developing the dry etch process. All processes

incorporate 1.5 sccm flow of Cl2 and 19.5 sccm flow of BCl3. Figure 5.7 shows the

effect of using a 6000 Å SiN etch mask and dry etching at 15 mT and 75 W. Figure

5.7(a) shows SEM photos of the mesa prior to nitride mask removal and Figure 5.7(b)

shows the mesa after mask removal. The figures clearly show lateral etching of the

DBR mesa.

a) DBR mesa prior to nitride mask removal (b) DBR mesa post nitride mask removal Figure 5.7: Scanning Electron Micrographs of Cl-based GaAs/AlGaAs DBR mesa etch incorporating SiN etch mask. The figures shows significant lateral etching of the DBR.

In an attempt to reduce the lateral etching, we try using an AZ 4330 photo-

resist etch mask. SEM micrographs of a photo-resist mask process etching at 15 mT

and 50 W is shown in Figure 5.8. The photo-resist has not been removed in the

103

pictures. The plasma power incident on the resist displaces resist from the center of

the mesa and places it on the edges. The temporal characteristics of the resist

displacement generate the “flower pot” effect seen in Figure 5.8. The edges of the

bottom of the DBR ultimately spread into the ring contact region which is not

acceptable.

a) DBR mesa prior to resist mask removal (b) DBR mesa prior to resist mask removal Figure 5.8: Scanning Electron Micrographs of Cl-based GaAs/AlGaAs DBR mesa etch incorporating photo-resist maske w/o a post exposure hard-bake.

To eliminate the “flower pot” effect, we introduce a 1 minute resist hardbake

at 110 °C prior to the dry etch. Figure 5.9 shows the effect of including a hardbake.

The hardbake keeps the resist from sputtering out of the center of the mesa and

provides straighter sidewalls and less lateral etching than the SiN mask. We believe

that the reaction of the plasma with the resist forms a polymer coating at the edge of

the mesa as the etch progresses inhibiting lateral etching. Figure 5.10 shows an

alignment feature of mask width 4 µm. The lateral etching is less ~ 1 µm in each

direction, sufficient for our process. Reducing the DBR mesa diameter allows us to

104

reduce the inner ring contact radius from 25 µm to 12 µm and the contact area from

1900 µm2 to 700 µm2.

Figure 5.9: Scanning Electron Micrographs of Cl-based GaAs/AlGaAs DBR mesa etch incorporating photo-resist mask w/ a post exposure hard-bake.

Figure 5.10: Scanning Electron Micrographs of Cl-based GaAs/AlGaAs DBR mesa etch incorporating photo-resist mask w/ a post exposure hard-bake. The picture shows the etch effect on the smallest features on the mask..

5.4.2 Active Region Mesa Definition

We also replace all active region wet etches with a methane/hydrogen/argon (MHA)

based wet etch. We encountered several problems in 2nd generation device

fabrication prior to employing the MHA dry etch. Figure 5.11 shows samples after a

active region wet etch. In Figure 5.11a, we observe haziness on the sample after

etching signifying uneven etching across the sample. Figure 5.11b shows islands of

105

material remaining after the wet etch. From island height analysis, we determine that

no material etching takes on these areas during the wet etch.

a) post wet-etch on active region (b) islands not etched during active wet etch Figure 5.11: The pictures show the effect of wet etches on 2nd generation material after TJ and CL re-growth. The re-growth process leaves regions which do not etch selectively with standard wet etch processes for InP and quaternary material.

The MHA etch process is delineated in Appendix A and will not be explained

here. We would like to mention that the flow rates for the CF4, H2, and Ar are 4, 20,

and 10 sccm respectively. The dry etch easily etches through the InP contact and

cladding layers and the InGaAsP SL layers. The etch rate slows down considerably

on the AlInGaAs active region and we use this layer as an etch stop for the dry etch.

Thus, we do not have to employ laser monitoring during the etch. We finish off the

active region etch with a 1 minute dip in 1:5:15 H3PO4:H2O2:H2O. We mask the dry

etch with 1500 Å of SiN.

Figure 5.12 shows the benefit of a dry etch versus the wet etch. Figure 5.12a

shows the sample after an 8’ etch. The dirty stripes are areas upon which etching

stops at the re-growth interface, signifying that the re-growth process is responsible

106

for the islands in Figure 5.11b. The wet-etch would not be able to penetrate this

layer, but a subsequent 6’ dry etch etched the entire sample into the AlInGaAs layer,

shown in Figure 5.12b. Rather than performing separate etches for the contact layer

isolation and the self-aligned bottom contacts (Figure 5.5), we perform the RIE etch

and AlInGaAs clean up wet etch all the way to the bottom contact layer and use the

PMGI/AZ 4330 lift-off procedure described in Section 5.4.1 for the bottom contact

layer lift-off. A schematic process flow signifying changes in the structure is shown

at the end of Section 5.5.

a) active region post 8’ MHA dry etch (b) active region post 14’ MHA dry etch Figure 5.12: The pictures show the improvement in etch quality by transitioning from a wet etch to an MHA dry etch. The picture in (a) shows the regions which have large amounts of defects and would not etch during the wet etch. The figure in (b) demonstrates the same sample after an addition 6’ etch and exhibits the ability of a dry etch to penetrate defect layers.

5.4.3 High Speed Bond Pads and Electrical Isolation

We also attempt in 2nd generation devices to minimize bond pad capacitance by

etching away doped material under the ring contact bond pad. Since the entire field

of the sample at this point in the process is InP, we use an 1 minute 3:1 H3PO4:HCl

107

wet etch to remove the doped InP material before the SiN passivation step. Figure

5.13 shows the changes in the process flow over 1st generation devices.

Dry etch DBR mesa, evaporate ring contacts

Dry etch active region down to CL, evaporate bottom contacts

Deposit nitride, form airbridge, evaporate pad metal

Figure 5.13: Process flow for 2nd generation devices incorporating primarily dry etch processes..

Figure 5.14 shows a SEM micrograph of a complete device including the

bond pad isolation. Figure 5.15 zooms in on the device in Figure 5.14. The zoomed

in picture shows the DBR sitting in the middle of the ring contact and shows the pad

metal rising over the PMGI bridge and bonding to the ring contact. We can also

clearly see the dry etched DBR and active region mesas.

108

Figure 5.14: SEM micrograph of an entire device. We can clearly see the DBR mesa and the bond pad etch.

Figure 5.15: SEM micrograph zoomed in on a single device. The ring contact, active region mesa formation, PMGI bridge and pad metal are much more clear in this picture than they are in Figure 5.14. 5.5 Summary and Conclusions In this chapter, we present the fabrication procedures for the first and second

generation processes. Aside from the undercut etch, the third generation fabrication

process does not vary much from the second generation process. We present a

detailed description of the bond process, including sample preparation and loading.

We also present basic recipe conditions which yield the highest quality bonds. By

incorporating dry etches, we transition to a significantly more robust fabrication

process between the first and second generations. Step-by-step process followers can

be found in Appendices A and B.

109

References [1] D. Pasquariello and K. Hjort, "Plasma-assisted InP-to-Si low temperature

wafer bonding," IEEE Journal of Selected Topics in Quantum Electronics, vol. 8, pp. 118-131, 2002.

[2] H. Park, A. W. Fang, S. Kodama, and J. E. Bowers, "Hybrid silicon

evanescent laser fabricated with a silicon waveguide and III-V offset quantum well," Optics Express, vol. 13, pp. 9460-9464, 2005.

[3] A. R. Hawkins, T. E. Reynolds, D. R. England, D. I. Babic, M. J. Mondry, K.

Streubel, and J. E. Bowers, "Silicon heterointerface photodetector," Applied Physics Letters, vol. 68, pp. 3692-3694, 1996.

[4] S. Estrada, A. Huntington, A. Stonas, H. Xing, U. Mishra, S. DenBaars, L.

Coldren, and E. Hu, "n-AlGaAs/p-GaAs/n-GaN heterojunction bipolar transistor wafer-fused at 550-750 degrees C," Applied Physics Letters, vol. 83, pp. 560-562, 2003.

[5] A. Black, A. R. Hawkins, N. M. Margalit, D. I. Babic, A. L. Holmes, Y. L.

Chang, P. Abraham, J. E. Bowers, and E. L. Hu, "Wafer fusion: Materials issues and device results," IEEE Journal of Selected Topics in Quantum Electronics, vol. 3, pp. 943-951, 1997.



[7] V. Jayaraman, J. C. Geske, M. H. MacDougal, F. H. Peters, T. D. Lowes, and

T. T. Char, "Uniform threshold current, continuous-wave, singlemode 1300nm vertical cavity lasers from 0 to 70 degrees C," Electronics Letters, vol. 34, pp. 1405-1407, 1998.

[8] N. Y. Jin-Phillipp, W. Sigle, A. Black, D. Babic, J. E. Bowers, E. L. Hu, and

M. Ruhle, "Interface of directly bonded GaAs and InP," Journal of Applied Physics, vol. 89, pp. 1017-1024, 2001.


vol. Ph.D. Santa Barbara: University of California, Santa Barbara, 2000.

110

Chapter 6

Device Results and Analysis

In Chapters 2-5, we present methods to design and fabricate high-speed, high-power,

SM LW-VCSELs operating at high ambient temperature. In this chapter, we

characterize complete VCSELs and analyze the results of three different device

generations.

6.1 1st Generation VCSEL Results

First generation devices exhibit a device structure introduced in Chapter 2 and

repeated in Fig. 6.1. These devices employe an MOCVD grown 5 QW AlInGaAs

active region, an MBE re-grown and lithographically defined AlInAs/InP TJ current

and mode aperture, and a final MOCVD re-grown InP contact layer. The final

structure employs a buried TJ and a n-InP/p-InP interface surrounding the TJ aperture

which is is reverse biased during VCSEL operation with reverse bias breakdown

111

characteristics (taken from on-chip test structures) shown in Fig. 6.2. The large 12 V

breakdown voltage creates an effective current blocking layer and funnels intra-cavity

current into the TJ region.

Figure 6.1: 1st generation device structure employing buried TJ aperture and current blocking reverse biased p-n junction surrounding the aperture.

Figure 6.2: Measured breakdown characteristic for reverse biased p-n junction. This junction is analogous to junction surrounding the TJ aperture. The junction shows 12 V breakdown voltage.

Device sizes on the mask for this generation are 5, 8, 12, 16, and 20 µm, and all

employ GaAs/Al0.92Ga0.08As DBRs. We fabricate three first generation structures,

Designs A, B, and C. Designs A and B employ a 31 period back DBR and a 27

112

period output coupler. Design C employs a 35 period back DBR and a 25 period

output coupler. The increase in the high reflectivity DBR reflectivity is to minimize

back substrate reflection and loss through the back DBR. We decrease the output

coupler reflectivity in order to improve the ηd of the devices. In addition to exhibiting

different DBR reflectivities, various devices also show different gain-mode offsets

allowing us to analyze reflectivity and offset effects on laser characteristics.

6.1.1 Results for 8 µm Aperture Diameter Devices

Light-current-voltage (L-I-V) characteristics at RT for 8 µm devices from designs A

and B operating with 56 nm and 40 nm gain-mode offsets are shown in Fig. 6.3.

Light-current characteristics of these two devices over temperature (L-I-T) are shown

in Fig. 6.4. The device employing a 56 nm offset operates to 134 °C while the device

operating with a 40 nm offset operates to 123 °C. Fig. 6.5 shows the 134 °C L-I

characteristic.

(a) 56 nm offset device (b) 40 nm device

113

Figure 6.3: L-I-V characteristics for 8 µm Lot A devices employing 40 nm and 56 nm gain-mode offsets. Measurements are taken 20 °C stage temperature.

(a) 56 nm offset device (b) 40 nm device Figure 6.4: L-I-T characteristics for 8 µm Lot A devices employing 40 nm and 56 nm gain-mode offsets. . While the device operating to 134 °C did, to the best of our knowledge, set a

world record at the time of publication [1], operation to such high a temperature is not

necessary in our target applications. Of greater importance is device performance at

an ambient temperature of 80 °C. The device employing a 40 nm offset

demonstrates far better output power characteristics at 20 °C and 80 °C. While the 40

nm device shows SM output powers of 1.6 mW at 20 °C and 0.8 mW at 80 °C, the 56

nm device yields only 1 mW and 0.5 mW at 20 °C and 80 °C respectively. Fig. 6.6

shows the single mode optical spectrum for the 40 nm device at 20 °C.

114

Figure 6.5: L-I characteristic for 8 µm Lot A devices employing a 56 nm gain-mode offset operating to a maximum ambient temperature of 134 °C.

Figure 6.6: Optical spectrum showing SM performance of a high power, 40 nm offset Lot A device. The device diameter is 8 µm and the measurement is taken at a stage temperature of 20 °C.

RT L-I-V and L-I-T characteristics of an 8 µm device from design C are shown in

Fig. 6.7. This device also employs a 40 nm gain-mode offset, but as stated

115

previously, employs a higher back DBR reflectivity and a lower output coupler

reflectivity in order to eliminate back substrate reflection and improve ηd over designs

A and B. These devices operate to a maximum ambient temperature of 110 °C. The

reduction in maximum operating temperature versus the 40 nm design B device is due

to higher mirror loss. But we now achieve 2 mW SM output power at 20 °C and 1

mW SM output power at 80 °C. We also improve the maximum ηd from 32% to

46%. A summary of the design and characteristics of the three devices mentioned

previously is shown in Table 6.1. All devices mentioned previously show Ith values

between 1 mA and 2 mA. The increase in ηd and thermal roll-over current in design

C versus design B devices more than compensate for the increase Ith from 1.3 mA to

1.8 mA between the two lots.

(a) L-I-V characteristic (b) L-I-T characteristic Figure 6.7: L-I-V and L-I-T characteristics for 8 µm Lot B device employing a 40 nm gain-mode offset. The increase in maximum output power over Lot A devices corresponds with a

c upler r flectivireduction in the output o e ty.

116

Design Characteristics Definitive Results

A - 56 nm offset - 2- 31 period. back DBR

- Operates to 134 °C CW - > 1 T 7 period. top DBR mW output power @ R

B - 40 nm offset - 27 period top DBR - 31 period bottom DBR

- Operates to 123 °C CW - 1.6 mW RT SM output power- 1 mW SM power @ 66 °C

C - 40 nm offset - 25 period top DBR

- 35 period back DBR

- Operates to 110 °C - 2mW SM RT output power - 1 mW SM power @ 80 °C

Table 6.1: Summa of d evi ee 8 µm designs analyzed.

in, Loss, and Thermal Characteristics

Based on the gain curves used earlier in this thesis to calculate theoretical high speed

characteristics and the threshold properties of Lot B devices, we approximate a 550

cm-1 threshold gain (g ) for the Lot B structure. This corresponds to an internal loss

of 3.63 cm-1. All devices are assumed to operate with an η of 65%.

We calculate the thermal impedance, R , of design B, 8 µm devices by

individually measuring the output wavelength change with dissipated power (dλ/dP)

and with ambient temperature (dλ/dT). The quotient of (dλ/dT) and (dλ/dP) yields the

value of R . Fig. 6.8 shows the change in operating wavelength with ambient

temperature on the Lot B device. We measure an R to be 1.289 °C/mW.

ry evice structure and d ce characteristics for the thr

6.1.1.1 Ga

th

i

th

th

th

117

Figure 6.8: Optical spectra for design C device between stage temperatures of 20 °C and 110 °C.

6.1.1.2 Threshold Characteristics

Based on the theory presented in the high speed design chapter, the large offsets

associated with these devices will prompt the gain peak and cavity mode to come into

alignment at ambient temperatures higher than room temperature. Fig. 6.9 shows Ith

versus temperature characteristics for designs A and C in Table 1. Both designs

shows an initial decrease in Ith vs. temperature. But while design C, incorporating a

40 nm offset, exhibits an Ith minimum at 50 °C, design A, employing a 56 nm offset,

exhibits an Ith minimum at 90 °C. We would like to have a monotonic decrease in Ith

over the range of temperature over which we will operate so long as reducing

threshold does not compromise other device characteristics. We will show in our

analysis of 3rd generation devices that a constant reduction in Ith coupled with other

SM design factors does maximize device performance at high temperature.

118

Figure 6.9: Threshold characteristics versus temperature for design A and design C devices. Both curves show a local minimum confirming that the gain peak and cavity mode come into alignment at higher temperatures.

6.1.2 Results for 5, 12, 16, and 20 µm Aperture Diameter Devices

While devices with 8 µm aperture diameters provide maximum SM performance on

1st generation devices, we now examine the performance characteristics of other

device diameters in order to further understand several VCSEL operating

mechanisms. L-I-V characteristics for a 5 µm device operating at RT are shown in

Fig. 6.10. While the output power is greater than 1.4 mW, the device demonstrates

saturable absorber characteristics close to threshold. The large size of the mode with

respect to the 5 µm current aperture incites absorption loss at the edges of the optical

mode. The structure does not achieve threshold until the current density is large

enough to induce lateral carrier diffusion and population inversion at the edge of the

119

mode. Thus the devices shows higher Ith values than would be the case with smaller

mode diameters.

Figure 6.10: L-I-V curves for a 5 µm device. While the maximum output power is greater than 1.4 mW, the L-I characteristics show saturable absorber effects characteristic of many of the smaller devices.

RT L-I-V characteristics for a 12 µm device are shown in Fig. 6.11. This device

was fabricated on the same chip as designs A and B and employs a gain-mode offset

of 40 nm. The device demonstrates 2 mW output power and 30% ηd at 20 °C and

operates to 100 °C. The value of this structure in our work is severely limited due to

the MM nature of the device.

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Figure 6.11: L-I-V curves for a 12 µm device. Maximum output power approaches 2 mW, but the larger devices are predominantly multi-mode. Data is taken at 20 °C stage temperature.

Within all first generation fabrication lots, only one 16 µm device lased. The RT

L-I-V characteristic of this device is displayed in Fig. 6.12. We would expect the

output power of larger aperture devices to be higher than that of the smaller aperture

devices, but this is clearly not the case. We attribute the performance drop off to

uneven pumping of the TJ current aperture due to the intra-cavity contact scheme.

We verify this contention through optical spectrum data for the device at RT, as

shown in Fig. 6.13. The dominant nature of the shorter-wavelength, higher-order

modes confirms that the edges of the current aperture are pumped more strongly than

the center of the aperture. Furthermore, the 160 Ω Rd presents too small TJ resistivity

to spread carriers evenly through a 16 µm aperture according to calculations in

Chapter 3. Consequently, very few large area devices operate. No 20 µm devices on

chip operated CW at RT.

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Figure 6.12: L-I-V curves for a 16 µm device. The output power decreases significantly compared to smaller devices due to non-uniform pumping from the intra-cavity contacts into the TJ aperture.

Figure 6.13: Optical spectrum for a 16 µm device. The dominant higher order modes confirm stronger pumping on the edges of the TJ aperture compared to the center and thus non-uniform lateral carrier distribution in the active region.

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6.1.3 Voltage Characteristics of 1st Generation Devices

The inherent drawback on all First generation devices lies in their voltage and Rd

characteristics. All RT L-I-V curves shown previously in this chapter show operating

voltages above 5 V and Rd values above 150 Ω and 350 Ω. Table 6.2 shows average

Rd values for lasing device aperture sizes. 5 V operating voltages are far too high for

access and metro area applications. Modules incorporating these devices in the field

will employ 3.3 V driver circuits. Thus, the VCSEL must be able to operate at less

than 3 V. Moreover, these devices will act as a termination impedance for 50 Ω

transmission line systems sending up to 10 GHz signals into the device. We attribute

most of the high voltage characteristics to sub-par TJ performance of the device. The

theory and modeling behind this hypothesis are described in Chapter 3, and

confirmation of voltage improvement in accordance with TJ improvement will be

presented in the section on 3rd generation results. Characterization and analysis of

sheet resistance, contact resistance, and reverse bias breakdown voltages will be

presented in the next section on 2nd generation devices.

Aperture Diameter (µm) Rd (Ω)

5 390 8 330 12 230 16 160

Table 6.2: Average differential resistance for various 1st generation device size. The values for SM device sizes are above 300 Ω, thus far too high for any industrial application.

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6.2 2nd Generation VCSEL Results

We made several mask changes for 2nd generation devices, but the active region

remained the same. Unfortunately, second generation devices did not perform to the

level we expected. The reasons for sub-par performance will become clear when we

perform result analysis in this section. Although devices did not perform well, we

were able to characterize several device and material parameters that we could not

measure on devices from the 1st generation due to test structures on the new mask.

Since the active regions for both sets of devices are the same, values for sheet

resistivity, contact resistivity, and reverse bias breakdown voltage should be

nominally similar. TJs from both generations were grown separately and in some

cases in different reactors yielding significantly different device voltage

characteristics. The next several sub-sections will explain device characteristics and

explain the sub-par device performance.

6.2.1 2nd Generation Test Pattern and Test Structure Characteristics

The 2nd generation mask set included Transmission Line Measurement (TLM) test

patterns to test contact and sheet resistivities of both contact layers as well as mesa

structures to test device voltage characteristics without the intra-cavity effects of the

top contact and to test the reverse bias breakdown characteristics of the n-InP/p-InP

current blocking interface surrounding the TJ current aperture.

In addition to gathering data from the test patterns, we also fabricated one set

of devices without DBRs to ensure proper current injection through the TJ and

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electro-luminescence from the QWs. This test run allowed us to work through a

process with the new mask set without having to immediately incorporate wafer

bonding and a new RIE process required to etch the 20 µm diameter GaAs/AlGaAs

output coupler. TLM data taken on the top contact of this structure is shown in Fig.

6.15. The extraction of sheet resistance (Ω/), contact resistance (Rc), resistivity (ρ)

and specific contact resistance (ρc) values based on the TLM pattern geometry is

shown in Table 6.3. The values compare favorably to those in literature based on the

contact layer doping level of 1x1018 cm-3. We expect the resistivity values for the

bottom contact layer to closely resemble values for the top layer since they are both

4100 Å thick InP layers with nominally the same doping levels.

Figure 6.15: TLM data taken on a 0.41 µm InP layer doped 1x1018 cm-3 n-type.

Parameter Value Sheet Resistance, Rs (Ω/) 92.95 Contact Resistance, Rc (Ω) 1.07

Resistivity, ρ (Ω-cm) 3.72x10-3

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Specific Contact Resistance, ρc (Ω-cm2) 2.07x10-6

Table 6.3: Various derived resistance and resistivity parameters based on TLM measurement of 0.41 µm InP layer doped 1x1018 cm-3 n-type.

A comparison of J-V characteristics from 1st generation and 2nd generation

devices is shown in Fig. 6.16. While the turn-on voltage of Second generation

devices is higher than First generation devices, the Rd and voltage at operating current

densities are 1 V less for Second generation structures. An optical spectra of

spontaneous emission in the Second generation test structure is shown in Fig. 6.17 to

verify that the carriers are recombining in the MQW active region. We attribute the

voltage improvement on the test devices to two key factors. First, the temperature

during the TJ re-growth was reduced to less than 500 °C in order to minimize

amphoteric effects of the carbon dopant atoms. Second, the reduced intra-cavity

contact propagation distances minimize the excess voltage factors in the device.

Figure 6.16: Comparison between first and second generation J-V characteristics While 2nd generation devices show higher turn on, Rd is reduced significantly.

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Figure 6.17: Optical spectrum of spontaneous emission from test structures fabricated on actual 2nd generation active material. Emission around the gain peak confirms that the carriers in Figure 6.16 are pumping the active region rather than traversing a leakage path.

While the test structures showed improved voltage characteristics over 1st

generation devices, the actual devices incorporated a TJ re-growth from a different

MBE system. Thus, the defect density incurred during re-growth was quite high and

resulted in several runs of catastrophic diode failure, an example of which is shown in

Fig. 6.18. Diode failure was a result of metal migration into the p-cladding layer and

beyond during the contact anneal. We subsequently removed all contact anneal steps

from the process in order to eliminate diode failure.

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Figure 6.18: I-V curve for fabricated 2nd generation devices showing irreversible diode failure at 5 V. The failure is attributed to metal migration through defects generated during the re-growth process.

6.2.2 2nd Generation VCSEL Characteristics

L-I-V and L-I-T characteristics for a 2nd generation VCSEL are shown in Fig. 6.19.

The increase in voltage over the test structures in Fig. 6.16 is due to the absence of a

contact anneal. Several other groups do not anneal n-type contacts on LW-VCSELs

[2]. In order to minimize contact resistance, those devices employ a contact layer

doped as high as 1x1019 cm-3. Since our doping levels are an order of magnitude

lower, contact resistance does provide significant contribution to the voltage of the

device.

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(a) L-I-V characteristic (b) L-I-T characteristic Figure 6.19: L-I-V and L-I-T characteristics for an 8 µm 2nd generation device. Device characteristics are sub-par to 1st generation devices due to an extended n-cladding layer thickness.

The low output power characteristics are in part due to the higher voltage and in

part due to an over-growth of the re-grown contact layer. Fig. 6.20 shows optical

spectra for the device in Fig. 6.19 at various current levels. Two longitudinal modes

are apparent from the spectra. Based on the mode spacing and lasing wavelength, we

calculate a 30 nm over-growth of the InP contact layer. Fig. 6.21 shows a

VERTICAL simulation plot of the optical band structure of the high reflectivity DBR.

The lasing wavelength corresponds to a back mirror reflectivity of 99.89 %. Most

back DBRs show reflectivities around 99.99%. Thus, the back DBR on 2nd

generation devices contributes an extra 0.1 % optical loss to the device. The low

back DBR reflectivity explains the high Ith and ripple in the L-I curve.

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(a) Lasing optical spectrum (b) Spontaneous emission optical spectrum Figure 6.20: Optical spectra for a 2nd generation device below and above threshold. The increase in contact layer thickness increases the design mode to greater than 1.35 µm. Thus a second longtiduinal mode arrives within the gain bandwidth (1.277 nm) reaches threshold.

(a) Back DBR spectrum – zoom out (b) Back DBR spectrum – zoom in Figure 6.21: Calculated Reflectivity spectrum for the back DBR. The spectrum is calculated using VERTICAL. The zoomed-in curve in (b) shows that the high reflectivity mirror does not reach 99.9 % reflectivity, thus increasing loss and severely limiting device performance.

It is interesting to note that the device achieves threshold at the shorter mode

wavelength in spite of the larger wavelength mode residing further within the mirror

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stopband, according to Fig. 6.22. This characteristic shows that the lasing

characteristics of the device are dominated by the gain properties of the active region

rather than the reflectivity properties of the mirror.

Figure 6.22: Calculated Reflectivity spectrum for the back DBR zoomed in to show reflectivity at design mode (1.355 µm). The reflectivity is ~ 0.05 % larger at the higher wavelength.

6.3 3rd Generation VCSEL Results

Before proceeding to third generation results, we would like to acknowledge Agilent

Laboratories for their involvement in the growth, design, fabrication, and testing of

the devices. All development and measurement analysis was performed on the

Agilent premises in Palo Alto, CA.

Third generation devices employ several mirror types and cavity lengths. With

the many variations in all 1st generation and 3rd generation structures, we can draw

many conclusions about structural effects on thermal performance. Table 6.4 lists the

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5 lots of 3rd generation devices that we characterize. All devices now employ a

dielectric TiO2/SiO2 output coupler and a half-wave InP p-cladding layer. Using

dielectric material reduces the overall DBR penetration depth and effective cavity

length of the device. The inherent fr gain from this substitution is shown in Chapter

4. While both lots A and B employ 8-λ cavities and operate at 1310 nm with gain-

mode offsets of 30 nm, lot A employs a high reflectivity dielectric DBR while lot B

incorporates a semiconductor GaAs/AlAs DBR bonded at 600 °C. Lot C devices also

operate at 1310 nm with a 30 nm gain-mode offset, but the cavity length is reduced to

3-λ and the back DBR is replaced with a semiconductor GaAs/AlAs DBR grown

metamorphically at 550 °C. Both lots D and E employ 3-λ cavities operating at 1330

nm and employ 50 nm gain-mode offsets. Both lots D and E also contain a wafer-

bonded GaAs/AlAs back DBR. While lot D devices are fabricated with a bond

temperature of 580 °C, we reduce the bond temperature on lot E devices to 550 °C.

The rest of this section will focus on CW and small-signal modulation results on each

of these lots of devices.

Lot Cavity Length Operating Wavelength Back DBR A 8 λ 1310 nm (30 nm offset) Dielectric B 8 λ 1310 nm (30 nm offset) Bonded

GaAs/AlGaAs (600 °C) C 3 λ 1310 nm (30 nm offset) Metamorphic

GaAs/AlGaAs (550 °C)

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D 3 λ 1330 nm (50 nm offset) Bonded GaAs/AlGaAs (580 °C)

E 3 λ 1330 nm (50 nm offset) Bonded GaAs/AlGaAs (550 °C)

Table 6.4: Lot descriptions of the 5 different 3rd generation structures analyzed. Primary variations are cavity length, gain-mode offset, and back DBR type.

6.3.1 CW Light-Current Results and Analysis

6.3.1.1 CW Results for 30 nm gain-mode offset devices operating at 1310 nm

Lots A-C all operate with 30 nm gain mode offsets. Assuming similar thermal

characteristics, we would expect the L-I characteristics over temperature to be fairly

similar for devices from all three lots. Figs. 6.23 – 6.25 show L-I-T characteristics

for each of the three lots. Measurement equipment did not allow us to raise the

ambient temperature higher than 70 °C. All devices demonstrate SM output powers

of approximately 1.7 mW at 20 °C and between 0.8 mW and 0.9 mW at 70 °C. Lot B

devices show greater than 1.7 mW output power at 20 °C, but the output

characteristics do become MM above 1.7 mW.

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Figure 6.23: Measured L-I-T characteristics for a Lot A device. The device employs an 8-λ cavity and a 30 nm gain-mode offset and incorporates a dielectric back DBR.

Figure 6.24: Measured L-I-T characteristics for a Lot B device. The device employs an 8-λ cavity and a 30 nm gain-mode offset and incorporates a GaAs//AlGaAs back DBR bonded at 600 °C.

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Figure 6.25: Measured L-I-T characteristics for a Lot C device. The device employs a 3-λ cavity and a 30 nm gain-mode offset and incorporates a GaAs//AlGaAs back DBR grown metamorphically at 550 °C.

Lot A devices roll-over at lower current densities than Lot B and Lot C devices

due to the higher thermal impedance of the structure. By keeping an 8-λ structure and

replacing the bottom dielectric DBR with a bonded semiconductor DBR, the Rth is

reduced by 64 %. More importantly, replacing the dielectric DBR with a

metamorphic semiconductor DBR and reducing the cavity length from 8λ to 3λ

actually reduces the Rth from 2.2 °C/mW to 1.5 °C/mW. The data confirms that we

can reduce the cavity length to bring the structure within a volume region which will

enable high modulation bandwidth while not compromising output power at higher

temperatures. Moreover, we can actually increase the potential drive current of the

device yielding even higher intrinsic f3db.

6.3.1.2 CW Results for 50 nm gain-mode offset devices operating at 1330 nm

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L-I-T characteristics for a Lot D device are shown in Fig. 6.26. Compared to devices

from Lots A-C, the SM output power at 20 °C only improves from 1.7 mW to 2 mW.

While this may at first seem minimal, the improvement is significant since

conventional analysis would predict that a larger RT offset would result in lower RT

output power.

Figure 6.26: Measured L-I-T characteristics for a Lot D device. The device employs a 3-λ cavity and a 50 nm gain-mode offset and incorporates a GaAs//AlGaAs back DBR bonded at 580 °C.

The key improvement between 30 nm and 50 nm gain-mode offset devices lies in

the high ambient temperature characteristics of the device. The SM output power at

70 °C improves from a maximum of 0.9 mW for 30 nm devices to greater than 1.5

mW for 50 nm devices. Most devices in Lots D and E showed characteristics similar

to Fig. 6.26. Characteristics for a hero device are displayed in Fig. 6.27. The hero

device lay towards the edge of the VCSEL chip and for that reason included a lower

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reflectivity output coupler than the rest of the chip. While most edge devices did not

lase due to the higher gain required to compensate for DBR losses, edge devices that

did lase showed superior power characteristics to devices located close to the center

of the chip.

Figure 6.27: Measured L-I-T characteristics for a Lot E device. The device employs a 3-λ cavity and a 50 nm gain-mode offset and incorporates a GaAs//AlGaAs back DBR bonded at 550 °C.

6.3.1.3 CW Maximum Power, ηd, Rth, and Ith Analysis

Analysis of the maximum power, ηd, Rth, and Ith characteristics of third generation

devices provides significant insight into the effect of cavity length and offset on

device performance. Figure 6.28(a) shows a maximum power versus stage

temperature comparison between lots C and D, both 3-λ SM devices. While absolute

power metrics are difficult to analyze due to variations in active region growth, etc.

we do observe a larger roll-off in output power with temperature for 30 nm offset

devices than the 50 nm offset devices. Figure 6.28(b) shows maximum power versus

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temperature characteristics for lots A-C, all 1310 nm devices. All devices show

similar SM power and roll-off versus temperature, confirming that lot A structures,

incorporating two dielectric DBRs and an 8-λ cavity, efficiently extract heat from the

devices.

(a) Comparison of Lots C and D (b) Comparison of lots A, B, and C Figure 6.28: Maximimum power versus stage temperature comparison of several lots. The curves in (a) compare a 30 nm to a 50 nm device while the curves in (b) show the similarity in all 30 nm offset devices.

Figure 6.29 shows Ith versus temperature characteristics for devices from lots B-E.

Both lots operating with 50 nm offsets (D and E) show monotonic decreases in Ith as

temperature increases, while lot B devices demonstrate a monotonic increase in Ith

versus temperature and lot C devices show a local minimum. Coupled with the

maximum power plot in Figure 6.28(a), we can confirm that the larger offset and

reduction in Ith with increasing temperature allows us to design devices with more

linear output power characteristics with temperature than smaller offsets.

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Figure 6.29: Ith versus stage temperature comparison for Lots B-E. While 30 nm offset devices (B and C) show traditional threshold characteristics, 50 nm devices demonstrate a monotonic decrease in Ith with stage temperature due to the large RT offset.

Figures 6.30(a) and (b) show an interesting characteristic for the 3-λ bonded

devices (lots D and E). The data shows that Ith is higher and ηd is lower for lot E

devices over all temperatures. But Figures 6.26 and 6.27 show that the maximum

output power for lot E devices is as high, and in some cases higher than lot D. The

explanation for this behavior lies in Figure 6.31. The figure shows Rth values for lots

B-D versus various DBR mesa sizes. The mesa sizes correspond to device sizes

between approximately 7 µm and 10 µm. From the data in Figure 6.31, we realize

that the 550 °C bonded devices (lot E) extract heat more efficiently than the 580 °C

bonded devices allowing roll-over at 20 °C stage temperature to shift from 11 mA to

17 mA. Thus, although the threshold and slope characteristics of lot E devices are

worse than lot D, we can drive them to higher current levels and achieve higher

output power.

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(a) Ith versus stage temperature (b) DQE versus stage temperature Figure 6.30: Threshold and differential quantum efficiency variations with respect to stage temperature. The data is measured from Lot D and Lot E devices.

Figure 6.31 also shows Rth characteristics for devices from lots B and C. SM 8-λ

bonded devices show Rth values close to 0.8 °C/mW. All SM 3-λ devices show Rth

values of between 1.4 °C/mW and 2 °C/mW. Lot A devices show measured Rth

values larger than 2.2 °C/mW. Replacing the bottom heat spreading dielectric DBR

with a semiconductor bonded DBR reduces Rth by 64% thus quantitatively

confirming that the expected improvement in thermal properties of the device with

the inclusion of semiconductor heat spreading mirrors.

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Figure 6.31: Thermal impedance versus mesa size for Lots B-E. Lot B, which employs a thick 8-λ cavity and one semiconducctor DBR expectedly shows the lowest Rth of less than 1.0 °C/mW for all device sizes.

6.3.2 CW Current-Voltage (I-V) Characteristics and Analysis

Third generation devices show improved I-V characteristics over first and second

generation devices. Figure 6.32 compares the I-V characteristic of a lot A SM third

generation device with the optimized calculated I-V characteristics from chapter 4.

We observe strong agreement between theory and experiment. The improvement in

I-V characteristics is attributed primarily to a lower temperature TJ growth. Devices

operating SM from lot A exhibit operating voltages between 2.5 V and 2.75 V. While

this may not yet be satisfactory for driver circuit compatibility, it is a significant

improvement over the 5 V operating voltages in first generation devices.

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Figure 6.32: Comparison between 1st and 3rd generation I-V characteristics on ~ 8 µm devices and the optimized I-V curve calculated in Chapter 4 for an 8 µm device. 3rd generation I-V charactersitcs approach the theoretical characteristics of the optimized design

Figure 6.33 shows I-V characteristics for all lots. Figure 6.34(a) shows I-V

characteristics for the three bonded structures only. There is clear degradation in the

electrical performance of the devices as the bond temperature increases, likely due to

dopant out-diffusion during the temperature cycle of the bond process. Figure 6.34(b)

compares the voltage characteristics of lot C and lot E devices. Both devices have 3-

λ active regions and GaAs/AlGaAs back DBRs. Lot C incorporates a metamorphic

DBR grown at 550 °C while Lot E utilizes a DBR bonded at 550 °C. The similarity

in the I-V characteristics in Figure 6.34 confirms that the temperature cycle does have

an effect on the electrical properties of the device.

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Figure 6.33: I-V curves for all 3rd generation Lots.

(a) I-V curves for bonded structures (b) I-V curves for 3-λ structures Figure 6.34: I-V comparisons broken down into (a) bonded structure comparisons and (b) 3-λ structure comparisons. The curves indicated that high temperature processes do have an adverse effect on TJ characteristics.

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6.3.3 Small-Signal Modulation Results and Analysis

The last several sub-sections showed the improvement in high temperature output

power characteristics for third generation devices versus first and second generation

devices. Here, we present the small-signal modulation results for several third

generation devices. All data is taken on a Hewlett Packard Vector Network Analyzer.

This section is broken down into results for 8-λ devices and 3-λ devices. Section

6.3.3.1 presents modulation and MCEF data for the 8-λ lot A and B devices. Section

6.3.3.2 presents data for the 3-λ lot C, D, and E devices.

6.3.3.1 Small-Signal Modulation Results for Lots A and B

Devices from lots A and B employ 8-λ cavities and operate with a 30 nm gain-mode

offset. We do not expect breakthrough modulation results from 8-λ cavity devices.

The cavity length increase alone presents a 60 % decrease in inherent fr. Nonetheless,

we present the data primarily to serve as a comparison to 3-λ cavity device results

presented in the next section. Figure 6.35(a) shows modulation characteristics for a

lot A device operating SM and demonstrating a roll-over current of 11 mA. The data

is measured at a stage temperature of 20 °C. We measure a maximum fr of 5 GHz

and a maximum f3db of 7 GHz. The smaller peak associated with the curves at lower

current levels is due to over-modulation – the small-signal modulation level

approaches large-signal levels. Figure 6.35(b) shows MCEF characteristics for the

data in (a). We measure a MCEF slope of 1.79 GHz/mA1/2.

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(a) Modulation response (b) MCEF Figure 6.35: (a) Modulation response and (b) MCEF characteristics of a Lot A device employing an 8-λ cavity, 30 nm offset, and incorporating a back dielectric DBR. All data is measured at a stage temperature of 20 °C.

Figure 6.36 shows modulation response and MCEF data for an 8-λ cavity device

incorporating one bonded DBR. While the characteristics if Figure 6.36(a) indicate

high parasitic and damping in the device, the resonance peaks are distinct. We

measure similar maximum fr for both 8-λ structures. As with Figure 6.35(a), the

smaller peaks at low current levels are caused by over-modulation. The difference in

MCEF slope between lot A and B devices is consistent with the longer cavity length

of the bonded device due to the excess penetration depth in the semiconductor DBR,

but the bonded devices also show lower Rth and thus higher drive currents. The

ultimate fr is thus similar for both structures.

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(a) Modulation response (b) MCEF Figure 6.36: (a) Modulation response and (b) MCEF characteristics of a Lot B device employing an 8-λ cavity, 30 nm offset, and incorporating a back GaAs/AlGaAs DBR bonded at 600 °C. All data is measured at a stage temperature of 20 °C. 6.3.3.2 Small-Signal Modulation Results for Lots C, D, and E

We now present small-signal modulation results and analysis for the short-cavity,

high power devices. All devices analyzed in this section incorporate 3-λ cavities.

Recall that lot C devices employ a 30 nm gain-mode offset, while lot D and E devices

employ a 50 nm gain-mode offset.

Figure 6.37 and 6.38 present modulation curves and MCEF data for a SM lot C

device at 20 °C stage temperature. Recall that this device demonstrates maximum

powers of 1.8 mW and 0.9 mW at 20 °C and 70 °C respectively. The low frequency

damping characteristic at low drive currents in the frequency response curves of

Figure 6.37 are due to the larger RC constants at these current levels. As the drive

current increases and the RC constant decreases, the damping begins to recede and

becomes unnoticeable at the roll-over current of 15 mA. Increased damping on the

resonance peaks of several signals at low drive currents are attributed to the relatively

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large signal swing of the input sine wave. The input signal more precisely

approaches small signal conditions as the drive current increases. The curves show a

maximum fr and f3db of 8 GHz and greater than 10 GHz respectively. The 10 GHz 3-

db bandwidth should be more than sufficient for 10 Gbit/s transmission at 20 °C. The

device shows an MCEF of 2.27 GHz/mA1/2 at 20 °C. Since the thermal extraction of

lot C devices is more efficient than the dielectric devices of lot A and on the order of

lot B devices, we do not compromise on the thermal roll-off properties of the device

and receive maximum possible modulation response improvement from reducing the

cavity length.

Figure 6.37: Modulation response characteristics of a Lot C device employing a 3-λ cavity, 30 nm offset, and incorporating a back GaAs/AlGaAs DBR grown metamorphically All data is measured at a stage temperature of 20 °C.

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Figure 6.38: MCEF characteristics of a Lot C device employing a 3-λ cavity, 30 nm offset, and incorporating a back GaAs/AlGaAs DBR grown metamorphically All data is measured at a stage temperature of 20 °C.

Figures 6.39 and 6.40 shows modulation response and MCEF data for the same

device at 70 °C stage temperature. The maximum fr and f3db at 70 °C are 5 GHz and

greater than 6 GHz respectively. While the characteristics at high ambient

temperatures are not satisfactory for 10 Gbit/s transmission, they do show the

advantage of short cavity length devices operating with low Rth. The maximum fr for

the 8-λ lot A and B devices is equal to the maximum fr for 3-λ lot C devices at 70 °C.

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Figure 6.39: Modulation response characteristics of a Lot C device employing a 3-λ cavity, 30 nm offset, and incorporating a back GaAs/AlGaAs DBR grown metamorphically All data is measured at a stage temperature of 70 °C.

Figure 6.40: MCEF characteristics of a Lot C device employing a 3-λ cavity, 30 nm offset, and incorporating a back GaAs/AlGaAs DBR grown metamorphically All data is measured at a stage temperature of 70 °C.

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We have up to now considered only 30 nm gain-mode offset devices. The next

several figures will present data for the 50 nm lot D and E devices. Recall from

Chapter 4 that theoretical modulation bandwidth studies showed super-linear

characteristics on large offset devices (> 30 nm). All MCEF data must pass through

the origin to ensure that zero drive current above threshold corresponds to zero

modulation response. Figure 6.41 shows the modulation response for a 50 nm gain-

mode offset lot E device. We can immediately see that the device can be driven to

higher current levels without saturating the frequency response due to the larger gain-

mode offset. While the maximum 3-db of 8.5 GHz bandwidth is lower than the 30

nm case, we see modulation characteristics predicted in Chapter 4. The calculations

in Chapter 4 predict that the absolute maximum f3db will be lower for the large offset

devices, the local slope at peak drive currents will be higher. Figure 6.42

demonstrates the super-linear nature of the MCEF characteristics. From the curve,

we calculate a maximum local MCEF value of 4 GHz/mA1/2 at the highest drive

currents. Super-linear MCEF characteristics should manifest themselves in high

extinction ratio for communication devices.

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Figure 6.41: Modulation response characteristics of a Lot E device employing a 3-λ cavity, 50 nm offset, and incorporating a back GaAs/AlGaAs DBR bonded at 550 °C. All data is measured at a stage temperature of 20 °C.

Figure 6.42: MCEF characteristics of a Lot E device employing a 3-λ cavity, 50 nm offset, and incorporating a back GaAs/AlGaAs DBR bonded at 550 °C. All data is measured at a stage temperature of 20 °C.

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Modulation and MCEF data for the same lot E devices analyzed in the previous

two figures are shown in Figures 6.43 and 6.44 at 70 °C ambient temperature. The

maximum fr and f3db at 70 °C are equal to lot C devices: 5 GHz and 6 GHz

respectively. Although the maximum f3db for lot E devices is 1.5 GHz less than lot C

devices at room temperature, they show equal characteristics at 70 °C. This again

corresponds to the calculations from Chapter 4. The low-frequency roll-off in

Figures 6.41 and 6.43 is likely due to parasitic capacitance in the structure due to

mask and layer design.

Figure 6.43: Modulation response characteristics of a Lot E device employing a 3-λ cavity, 50 nm offset, and incorporating a back GaAs/AlGaAs DBR bonded at 550 °C. All data is measured at a stage temperature of 70 °C.

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Figure 6.44: MCEF characteristics of a Lot E device employing a 3-λ cavity, 50 nm offset, and incorporating a back GaAs/AlGaAs DBR bonded at 550 °C. All data is measured at a stage temperature of 20 °C.

Finally, we show MCEF characteristics for lot D devices. While these devices

show the highest resonance peaks, the actual characteristics are a bit peculiar and not

fully understood. Nevertheless, the MCEF data presents inherent resonance data

which shows promise for high performance devices over a large range of temperature.

The actual modulation characteristics will have to be cleaned up through bond pad

improvement and damping analysis.

Figure 6.45 shows MCEF characteristics for a lot D device at 20 °C. We again

see the super-linear response characteristic of 50 nm devices. The maximum fr

approaches 9 GHz. Figure 6.46 shows MCEF characteristics for the same device at

70 °C. Here we observe the result we have been designing for throughout this work.

The data shows a maximum fr of 8 GHz at 70 °C. If this result can be coupled with a

mask design minimizing bond capacitance, we should observe 3-db bandwidths at 70

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°C well in excess of 10 GHz. As we mentioned earlier in this chapter, 7.5 GHz

should be adequate for 10 Gbit/s operation, but larger device bandwidth will ensure

large extinction ration and compatibility with a variety of communication standards.

Figure 6.45: MCEF characteristics of a Lot B device employing a 3-λ cavity, 50 nm offset, and incorporating a back GaAs/AlGaAs DBR bonded at 580 °C. All data is measured at a stage temperature of 20 °C.

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Figure 6.46: MCEF characteristics of a Lot B device employing a 3-λ cavity, 50 nm offset, and incorporating a back GaAs/AlGaAs DBR bonded at 580 °C. All data is measured at a stage temperature of 70 °C.

6.4 Summary and Conclusions

This chapter presents the culmination of the design and process development

described in Chapters 2 – 5. First generation devices demonstrate a maximum

ambient operating temperature of 134 °C, and SM output powers of 2 mW and 1 mW

at 20 °C and 80 °C respectively. We also observe Rth values on the order of 1.3

°C/mW. The primary drawback to first generation device performance is operating

voltages greater than 5 V.

Second generation devices incorporate a more robust fabrication method based

primarily on dry etch processes. Unfortunately, the over-growth of the InP contact

layer and the inability to anneal the contacts yields sub-par device performance

compared to first generation devices. Test structures do show significant

improvement in device voltage and differential resistance.

The third generation structure replaces one semiconductor DBR with a dielectric

DBR. We achieve greater than 2 mW SM output power at 20 °C and greater than 1.5

mW SM output power at 70 °C. We also report operating voltages of 3 V. Using 50

nm offset devices, we achieve small signal 3-dB bandwidths of 8 GHz at room

temperature and 6 GHz at 70 °C. By reducing the offset to 30 nm, we improve the

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room temperature 3-dB bandwidth to 10 GHz. 50 nm offset devices also exhibit a

maximum resonance peak of 8 GHz.

156

References

[1] V. Jayaraman, M. Mehta, A. W. Jackson, S. Wu, Y. Okuno, J. Piprek, and J. E. Bowers, "High-power 1320-nm wafer-bonded VCSELs with tunnel junctions," IEEE Photonics Technology Letters, vol. 15, pp. 1495-1497, 2003.



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Chapter 7

Summary and Conclusions

LW-VCSELs operating close to 1300 nm (O-band) offer an alternative to high-cost

in-plane sources for use in access, metro-area, and storage-area networks. Recent

years have seen a remarkable improvement in LW-VCSEL performance from several

groups, including the approach described in this thesis which incorporates InP-based

MQW active regions with GaAs-based DBRs. We focus on maximizing CW and

modulation performance at high ambient temperature (70 °C – 80 °C) by

incorporating high thermal-conductivity DBRs, active regions showing minimal

leakage at high temperature, and gain-mode offset engineering. The highly-reflective

GaAs-based DBR used in all generations offers high index contrast and extract heat

more efficiently from the active region than the dielectric DBR and InP-based

counterparts. AlInGaAs MQWs provide us with a well-established active region

technology capable of operating at high performance over the entire O-band. The

gain-mode offset theory we present allows us to improve power balance and small

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signal modulation bandwidth balance between 20 °C and 80 °C. Also, the platform

flexibility afforded to us by using a wafer-bonding process allows us to incorporate

several material systems into our devices. This could in the future be used for single-

chip integration of electronics, sources, and receivers.

The contributions of this thesis to the field of LW-VCSELs are numerous.

First generation devices were the first LW-VCSELs to incorporate a buried current

aperture with a wafer bonding process. With those devices, we developed the first

1300 nm VCSELs to demonstrate 1 mW SM output power at 80 °C and lasing above

130 °C. We also presented greater than 2 mW SM output power at 20 °C, high

differential efficiency (46 %), and low thermal impedance (1.3 °C/mW). With third

generation devices, we consistently show SM output powers of 2 mW and 1.5 mW at

20 °C and 70 °C respectively. Hero devices showed greater than 2.5 mW SM output

power at 20 °C. We also demonstrate 10 GHz small signal 3-dB bandwidth at 20 °C

and 8 GHz 3-dB bandwidth at 70 °C.

7.1 Future Work

The work presented in this thesis is one of many projects showing marked

improvement in LW-VCSEL technology in recent years. But several steps need to be

taken in order for the devices to meet industry standard specifications.

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7.1.1 Voltage Performance

Devices in all generations showed voltages which are too high to be used in existing

3.3 V driver modules. Additionally, we observed a minimum Rd of 100 Ω which we

would like to reduce to 50 Ω for modulation and transmission purposes. Future

researchers can take several steps to incrementally improve voltage and resistance

characteristics of the devices.

First, the doping of the n-type contact layer can be increased to reduce the

lateral spreading resistance. This will also allow us to increase the tunnel junction

doping while not hampering single mode device performance. The net effect that

increasing the doping will have on increasing optical loss but also reducing internal

temperature for a given output power should yield higher device performance.

Second, intra-cavity contact geometries can be brought closer to the device

aperture through mask modifications. This will again result in reduced lateral

spreading resistance. An improved Cl-based GaAs DBR etch which minimizes the

isotropic nature of the dry etch described in Chapter 5 will allow us to reduce the

DBR mesa diameter to less than 20 µm and thus reduce the top ring contact diameter

to less than 24 µm. We can also reduce the diameter of the bottom intra-cavity

contact significantly if we are willing to compromise a bit of mask alignment

tolerance.

Next, we would like to incorporate the TJ modeling results developed in

Chapter 3 in experimental process runs. As mentioned in Chapter 3, we have not

performed any experimental analysis on the effect of III/V ratio or C/In ratio on

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acceptor concentration InP/AlInAs or AlInGaAs/AlInGaAs TJs. These can be easily

analyzed using TJ test structure analysis described in Chapter 3. There is also the

option of incorporating dopants in the TJ, i.e. Er, that act as mid-gap states and

improve tunneling probability. If we are able to reduce the TJ voltage significantly,

we would be wise to examine alternative methods of uniformly spreading the carriers

before they arrive at the TJ. This will allow us to incorporate a low-voltage TJ into a

SM device. Two methods to uniformly spread carriers are pumping through the top

DBR and the bonded interface and incorporating a high mobility lateral transport

layer within the top contact layer. If we pump carriers through the DBR, we incur a

voltage increase associated with transport through a 5 µm DBR and transport through

the bonded interface. Alternatively, incorporating a high mobility transport layer

allows us to bypass current conduction through the DBR and bonded interface.

7.1.2 Transmission Measurements

In this work, we present much theory and experimental analysis on the small signal

relaxation resonance and modulation bandwidth of our devices. The next step is to

perform transmission experiments in order to determine integrity of our devices for 2

km – 15 km applications. The transmission experiments should take the form of eye-

diagram analysis and bit error rate tests. Since we hope for our devices to penetrate

the 10 Gbit/s application sector, we need to qualify our devices at these data rates.

7.1.3 Full 2” and 3” Wafer Bonding Processes

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Third generation devices employed a single bond on quarters of a 2” wafer. That was

the largest size bonded for actual devices described in this thesis. For a bond process

to be a commercially viable, we must be able to perform larger scale bonding,

preferably full 2” and 3” wafer bonding. At this level, overcoming cracking due to

coefficient of thermal expansion (CTE) mismatch could be a challenge. Thus much

care must be taken to develop a bond recipe which minimizes the effects of CTE

mismatch. While developing the third generation bond process, we found that

releasing the physical pressure on the samples at the end of the bond temperature

cycle rather than after the temperature ramp-down eliminates cracking and cross

hatch mark formation. Although this experiment was performed only on quarter

wafers, it does serve as a nice starting point to developing a large scale wafer bonding

process.

7.1.4 Array Fabrication Techniques

Much of the cost savings of VCSELs over in-plane devices in Ethernet and Fiber

Channel applications arise from the ease of parallel-optic array fabrication due to the

lower cost of packaging. Due to the market for parallel optics modules, effort should

be taken to analyze the power and electrical balance of devices within a section of an

array. Wafer-bonded LW-VCSEL Wave Division Multiplexing (WDM) fabrication

techniques have been described in previous Ph.D. theses [1,2].

7.1.5 Aperture Technique Determination and Reliability

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Throughout this thesis, we describe two aperture techniques that we employ in our

devices. In the first process, we lithographically define the TJ current aperture and

bury the aperture in a re-grown InP contact layer. In the second process, we laterally

undercut the TJ aperture. While our best results come from third generation devices

which incorporate an undercut aperture, the high device performance is a function of

improved active region and DBR technology rather than the aperture technique.

Furthermore, we believe that the buried aperture process provides the most reliable

aperture solution. Mechanical stability and long term reliability concerns exist in the

undercut technique. The same questions do not arise with the buried structures.

7.2 Conclusions

The work in this thesis shows significant progress towards the commercialization of

LW-VCSELs. We show CW power results which meet most industry specifications

over the full range of temperature and small signal modulation results which show

strong promise for transmission performance over the wide range of temperature.

Operating voltage, while not optimized, improved considerable throughout the course

of this project. We believe that the results presented in this thesis point to a bright

future for LW-VCSELs for use in access and metro communication systems, storage

area networks, parallel optics, and even interconnect applications. We hope that the

contributions of this work lead to continued improvement in the field of LW-

VCSELs.

163

References

[1] A. Karim, "Wafer Bonded 1.55 um Vertical Cavity Laser Arrays for




164

Appendix A

Wafer Bonded, Double Intra-cavity Contacted VCSEL

Process Follower

.1 CLEAVE ACTIVE REGION AND DBR'S .1.1 Use 8mm squares Active region size - Output coupler size - Back mirror size - .2 DEFECT REMOVAL ON TOP DBR .2.1 Spin/Bake 4330 Spin speed: 5K ______ Bake time: 1 min ______ 2.2 Expose defects with microscope 2.3 Develop defects in 1:4 AZ400K Develop time: 1 min _______ 2.4 Etch in 1:5:15 H3PO4:H2O2:H2O Etch time: 15 min ________ 2.5 Remove PR with ACE/ISO 2.6 Soak in 80C 1165 for 3 min 2.7 Rinse in ACE/ISO 2.8 O2 descum 300mT/100W

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Descum time: 15 sec ______ 3 MODE CHECK ON ACTIVE 3.1 Remove top 4 SL on regrown contact layer, wax bond to glass, and check

mode Active region mode position: 4 SL REMOVAL ON REGROWN CONTACT LAYER 4.1 Remove appropriate number of layers on contact layer for correct mode

position Number of layers removed: 5 FIRST BOND AND InP SUBSTRATE REMOVAL (using active, output

coupler) 5.1 RC - Rinse both pieces in ACE/ISO 5.2 RC - Swab clean both pieces with ACE using 20 strokes in each direction 5.3 RC - Rinse in ISO 5.4 RC - Rinse both pieces in ACE/ISO 5.5 RC - Dip both pieces in BHF Dip time: 10 sec _______ 5.6 TC - Dip both pieces in NH4OH Dip time: 2 min _______ 5.7 TC - Transfer both pieces to methanol 5.8 TC - Place both pieces in fixture 5.9 TC - Perform bond Bond pressure: 0.37 in-oz _______ Bond temperature: 575C ______ Bond time: 30 min _______ 5.10 RC - Place in 3:1 HCL:H2O until bubbling stops (~ 1 hour) Etch time: 5.11 RC - Remove InGaAs stop etch layer w/ RT 1:1:10 H2SO4:H2O2:H2O Etch time: 12 sec ______ 6 DEFECT REMOVAL ON BACK DBR 6.1 Spin/Bake 4330 Spin speed: 5K ______ Bake time: 1 min ______ 6.2 Expose defects 6.3 Develop defects in 1:4 AZ400K

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Develop time: 1 min ______ 6.4 Etch in 1:5:15 H3PO4:H2O2:H2O Etch time: 15 min _______ 6.5 Remove PR with ACE/ISO 6.6 Soak in 80C 1165 for 3 min 6.7 Rinse in ACE/ISO 6.8 O2 descum 300mT/100W Descum time: 15 sec ______ 7 BACKSIDE SL REMOVAL AFTER FIRST BOND/SUBSTRATE

REMOVAL 7.1 Remove InP, InGaAsP using 3:1 H3PO4:HCL for InP and RT 1:1:10

H2SO4:H2O2:H2O for InGaAsP Etch time: 20 sec for each etch ______ 7.2 Record reflectivity spectrum, make sure dip is consistent with expecations

from modeling Dip placement: 8 CHANNEL ETCH ON ACTIVE REGION 8.1 Spin/Bake 4110 Spin speed: 5K _______ Bake time: 1 min _______ 8.2 Pattern 'channels' from 'VJ quick oxidation mask' displace channels from first

set Expose time: 30 sec _______ 8.3 Develop in AZ400K Develop time: 1 min _______ 8.4 Etch remaining SL layers (CHECK FROM ABOVE WHICH TO REMOVE) Etched layers: 8.5 Revove PR with ACE/ISO 8.6 Soak in 80 1165 for 3 min 8.7 Rinse in ACE/ISO 8.8 O2 descum 300mT/100W Descum time: 15 sec 9 SECOND BOND AND BACK DBR GaAs SUBSTRATE REMOVAL 9.1 RC - Rinse both pieces in ACE/ISO 9.2 RC - Swab clean both pieces with ACE using 20 strokes in each direction 9.3 RC - Rinse in ISO 9.4 RC - Rinse both pieces in ACE/ISO

167

9.5 RC - Dip both pieces in BHF Dip time: 10 sec _______ 9.6 TC - Dip both pieces in NH4OH Dip time: 2 min _______ 9.7 TC - Transfer both pieces to methanol 9.8 TC - Place both pieces in fixture 9.9 TC - Perform bond Bond pressure: 0.37 in-oz _______ Bond temperature: 570C ______ Bond time: 30 min _______ 9.10 TC - Lap top mirror substrate to about 150 um using 12 um grit lapping paper Remaining thickness: 9.11 RC - Mount sample with wax on a glass cover slip, lapped substrate up 9.12 RC - Etch substrate in 30:1 H2O2:NH4OH @ 500 RPM until surface is

colored Etch time: 9.13 RC - Remove stop-etch in 1:3 49% HF:H2O, surface should look metallic Etch time: 1 min ________ 10 FIRST MESA PATTERN AND ETCH 10.1 Use mask level 'mesa2' on Rev. 3 intra-cavity contact mask 10.2 Spin/Bake HMDS/4330 Spin speed: 5K ______ Bake time: 1 min ______ 10.3 Edge bead removal Edge exposure time: 90" _______ Corner exposure time: 120" _______ 10.4 Develop in 1:4 AZ400K "Develop time: 60"" ______" 10.5 Expose/Develop 'Mesa 1' from 'Rev 4' mask Expose time: 17" ______ Develop time: 60" ______ 10.6 O2 descum 300mT/100W Descum time: 10" ______ 10.7 Remove and DI rinse. Inspect - if more etching is necessary, repeat 10.8 Hardbake Temp: 110C ______ Time: 1 min ______ 10.9 Dip in 1:20 NH4OH:H2O Dip time: 60" _______ 10.10 BLOW DRY ONLY - NO DI RINSE 10.11 Perform etch in RIE5 Pressure: 5mT ______

168

Power: 50W ______ BCl3: 19.5 sccm ______ Cl2: 1.5 sccm _______ Electrode: 3.2 _______ Time: monitor ______ 10.12 DI Rinse after etch 11. RING CONTACT DEFINITION 11.1 Spin/bake SF11 - remove edge bead w/ razor blade Spin speed: 5K ______ Bake temperature: 190C ______ Bake time: 60" ______ 11.2 Spin/bake 4330 Spin speed: 5K ______ Bake time: 60" ______ 11.3 Edge bead removal Edge exposure time: 90" _______ Corner exposure time: 120" _______ 11.4 Align 'ring contact' pattern from 'Rev. 4' to underlying aperture pattern using

IR aligner Expose time: 18" ______ Develop time: 60" ______ 11.5 O2 descum at 300mT/100W Descum time: 10" ______ 11.6 Deep UV expose Expose time: 300" (with spin) ______ 11.7 Develop in SAL101 and DI rinse Develop time: 60" ______ 11.8 Deep UV expose (2nd time) Expose time: 300" (with spin) ______ 11.9 Develop in SAL101 and DI rinse Develop time: 60" ______ 11.10 Dip in 1BOE:10H20 Dip time: 10" ______ 11.11 Load into e-beam 1 and deposit 260/540/200/2000 Ge/Au/Ni/Au Ge: _____ Au: _____ Ni: _____ Au: _____ 11.12 Lift off in 1165 80C. Rinse in ACE/ISO. O2 descum in necessary to remove

resist residue

169

12. NITRIDE DEPOSITION FOR MESA/BOTTOM N-METAL ETCH 12.1 DI Rinse Rinse time: 2 min _____ 12.2 PECVD Nitride deposition Chamber clean (w/o sample): 30 min ______ Nitride thickness: 1500 A ______ 12.3 DI Rinse Rinse time: 2 min _____ 12.4 PECVD Nitride deposition Nitride thickness: 1500 A ______ 12.5 DI Rinse Rinse time: 2 min _____ 13. PATTERN FOR MESA/BOTTOM N-METAL ETCH 13.1 Spin/Bake 4330 Spin speed: 5K _____ Bake time: 1 min ______ 13.2 Edge bead removal Edge exposure time: 90" ______ Corner exposure time: 120" ______ 13.3 Align 'mesa1' pattern from 'Rev4' mask Expose time: 21" _____ Develop time: 1' _____ 13.4 O2 descum 300 mT/100W Descum time: 20" ______ 13.5 Dektak resist height Resist height: _______ 13.6 CF4 etch 300mT/100W Etch time: 4 min. ______ 13.7 O2 descum 300 mT/100W Descum time: 20" ______ 13.8 Strip PR in 80C 1165 13.9 Rinse in ACE/ISO 14. RIE2 ETCH FOR MESA/BOTTOM N-METAL 14.1 O2 Chamber clean (w/o sample) O2: 20 sccm _____ Pressure: 125 mT _____ Voltage: 500 V _____ Time: 30' _____ 14.2 MHA Precoat (w/o sample)

170

CH4: 4 sccm _____ H: 20 sccm _____ Ar: 10 sccm _____ Pressure: 75 mT _____ Voltage: 500 V _____ Time: 20' _____ 14.3 Load sample 14.4 MHA Etch CH4: 4 sccm _____ H: 20 sccm _____ Ar: 10 sccm _____ Pressure: 75 mT _____ Voltage: 500 V _____ Time: check log book ______ 14.5 O2 Sample clean O2: 20 sccm _____ Voltage: 300 V _____ Time: 11' ______ 14.6 Dektak etch depth Depth: ~11000 A (including SiN) ______ 15. WET ETCH FOR MESA/BOTTOM N-METAL 15.1 Remove AlInAs/AlInGaAs active layer AlInAs/AlInGaAs etch time (1:5:15 H3PO4:H2O2:H2O): 1 min ___ 15.2 Dektak etch depth Depth: ~12500 A (including SiN) ______ 15.3 CF4 etch 300mT/100W Etch time: 4 min. ______ 15.4 Dektak etch depth Depth: ~9500 A (including SiN) ______ 16. BOTTOM N-METAL DEFINITION 16.1 Spin/bake SF11 - remove edge bead w/ razor blade Spin speed: 5K ______ Bake temperature: 190C ______ Bake time: 60" ______ 16.2 Spin/bake 4330 Spin speed: 5K ______ Bake time: 60" ______ 16.3 Edge bead removal Edge exposure time: 90" _______ Corner exposure time: 120" _______

171

16.4 Align 'nm' pattern from 'Rev. 3' mask Expose time: 18" ______ Develop time: 60" ______ 16.5 O2 descum at 300mT/100W Descum time: 10" ______ 16.6 Deep UV expose Expose time: 300" (with spin) ______ 16.7 Develop in SAL101 and DI rinse Develop time: 60" ______ 16.8 Deep UV expose (2nd time) Expose time: 300" (with spin) ______ 16.9 Develop in SAL101 and DI rinse Develop time: 60" ______ 16.10 Dip in 1BOE:10H20 Dip time: 10" ______ 16.11 Load into e-beam 1 and deposit 260/540/200/2000 Ge/Au/Ni/Au Ge: _____ Au: _____ Ni: _____ Au: _____ 16.12 Lift off in 1165 80C. Rinse in ACE/ISO. O2 descum in necessary to remove

resist residue 17. PADWELL ETCH 17.1 Spin/bake 4330 Spin speed: 5K ______ Bake time: 1 min ______ 17.2 Edge bead removal Edge exposure time: 90" ______ Corner exposure time: 120" ______ 17.3 Align 'padwell' pattern from 'Rev3' mask Expose time: 18" ______ Develop time: 60" ______ 17.4 O2 descum 300mT/100W Descum time: 30" ______ 17.5 Remove InP n-cladding layer InP etch time (3:1 H3PO4:H2O2): 1 min ______ 18. NITRIDE DEPOSITION 18.1 DI Rinse Rinse time: 2 min _____ 18.2 PECVD Nitride deposition

172

Nitride thickness: 1600 A ______ 19. NITRIDE HOLE ETCH 19.1 Spin/bake 4330 Spin speed: 5K ______ Bake time: 1 min ______ 19.2 Edge bead removal Edge exposure time: 90" ______ Corner exposure time: 120" ______ 19.3 Align 'nithole' pattern from 'Rev3' mask Expose time: 18" ______ Develop time: 60" ______ 19.4 O2 descum 300mT/100W Descum time: 20" ______ 19.5 CF4 etch 300mT/100W Etch time: 4 min. ______ 19.6 Strip PR in 80C 1165 19.7 Rinse in ACE/ISO 20. AIRBRIDGE DEFINITION AND PMGI REFLOW 20.1 Spin/bake SF11 - remove edge bead w/ razor blade Spin speed: 5K ______ Bake temperature: 190C ______ Bake time: 60" ______ 20.2 Spin/bake 4330 Spin speed: 5K ______ Bake time: 60" ______ 20.3 Edge bead removal Edge exposure time: 90" _______ Corner exposure time: 120" _______ 20.4 Align 'PMGI' pattern from 'Rev4' mask Expose time: 18" ______ Develop time: 60" ______ 20.5 O2 descum 300mT/100W Descum time: 20" ______ 20.6 Deep UV expose Expose time: 300" (with spin) ______ 20.7 Develop in SAL101 and DI rinse Develop time: 60" ______ 20.8 Deep UV expose (2nd time) Expose time: 300" (with spin) ______ 20.9 Develop in SAL101 and DI rinse

173

Develop time: 60" ______ 20.10 Strip PR in ACE/ISO 20.11 Reflow PMGI at 250C Reflow time: 20" ______ 20.12 Inspect - cotinue reflow if necessary 21. PAD METAL EVAPORATION 21.1 Spin/bake 4330 Spin speed: 5K ______ Bake time: 60"______ 21.2 Edge bead removal Edge exposure time: 90" _______ Corner exposure time: 120" _______ 21.3 Align 'PAD METAL' pattern from 'Rev4' mask Expose time: 19" ______ 21.4 Toluene soak Soak time: 60" ______ 21.5 Develop, 1:4 AZ400K Develop time: 60" _______ 21.6 O2 descum 300mT/100W Descum time: 20" ______ 21.7 Dip in 1BOE:10H20 Dip time: 10" ______ 21.8 Load into e-beam 1 and deposit 200/300/5000 Ti/Pt/Au Ti: _____ Pt: _____ Au: _____ 21.9 Liftoff in ACE

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