unit / module namethe air-cooled vp780 complies with the physical dimensions given in ansi/vita 46.0...

UM025 – VP780 User Manual r1.19

UM025 www.abaco.com page 1 of 58

VP780 User Manual

Abaco Systems

This document is the property of Abaco Systems and may not be copied nor communicated to a third party without the written permission of Abaco Systems.

© Abaco Systems 2018

http://www.abaco.com/



Revision History Document

Revision

Changes Author Peer Review

Quality Approval

Date

r1.0 Release N/A N/A N/A 2013-04-08

r1.1 Fixed chapter 3.5 header typo

Updated

Table 24: REF_CLK connections

Table 25: On-board GTX/GTH reference clock connections

Table 26: FMC GTX/GTH reference clock connections

Added the BLAST H pin outs to Appendix C: BLAST pin outs

Updated Index B with new revision information

N/A N/A N/A 2013-04-19

r1.2 Added vita67 slot profiles to section 2.1

Updated Table 36 to add the H BLAST options

Updated Table 22: to add the H BLAST options

Updated figure 5: to show the H BLAST

N/A N/A N/A 2013-04-11

r1.3 Removed double mention of CKE1 in Table 39 Table 40 for the BLAST H

Removed BLAST G option, not supported for VP780 anymore

N/A N/A N/A 2013-11-04

r1.4 Added some more details about the PCIe interface and supported bit rates in section 2.1

N/A N/A N/A 2013-11-06

r1.5 Updated Table 28 to swap pin assignment of CLK2_BIDIR_n and CLK2_BIDIR_p

N/A N/A N/A 2014-02-10

r1.6 Figure 7 didn’t match table 24/25.

Table 14 had incorrect pin location for DP6_M2C_P B18 should have been B16

Added Figure 5: Power Supply Rails. All figures after 5 got incremented.

N/A N/A N/A 2014-03-19

r1.7 Reworded some descriptions and fixed typos throughout document

N/A N/A N/A 2014-03-25

r1.8 Added I/O standards to table 28 and fixed typos throughout document. Added description to section 3.1.1 about a mechanical exception made to the VITA 48.2 standard with regards to the clamshell.

N/A N/A N/A 2014-08-21

r1.9 Fixed Table 15 header N/A N/A N/A 2014-10-06

r1.10 Updated the section 3.10.1 to indicate that the external reference clock is not available at power up.

N/A N/A N/A 2014-11-13

r1.11 Updated Table 30 to reflect proper reference designators and detail the target device.

N/A N/A N/A 2014-11-19

r1.12 Updated Table 36 to show the sys_reset connection as well

N/A N/A N/A 2015-03-24

r1.13 Updated Table 7 assignments for P2_DP16+/- and P2_DP17+/-

Updated chapter 3.5.1 to indicate what DDR3 phy speeds are supported

Updated clock section to describe that the VP780 supports asynchronous PCIe clocking and that there is no GTX/GTH reference clock reference clock provided to the FMC site.

N/A N/A N/A 2015-04-29

r1.14 Added details of Si5338 output connections to FPGA pins (Table 25 and Table 26)

N/A N/A N/A 2015-06-29

r1.15 -Added front panel options to section 3.1.5.

-Added VITA 48.1 compliance to section 3.1.1.

RZA IVK IVK 2016-06-23




r1.16 -Clarified PCB thickness details in section 3.1.1 DAS Pko JDS 2016-08-08

r1.17 -Updated the picture in FLASH storage to reflect the real memory map

-Rebranded to Abaco and changed table header and footer to the specified orange

-Added more information on UART over USB

JP EBA JDS 2017/06/21

r1.18 Added Appendix D: example of flash programming in Vivado

Ivk SPF JDS 2017/10/05

r1.19 In Table 32, corrected the swapped GTHAVCC and GTHAVTT connections to AIN7 and AIN8.

Ivk JPat Ivk 2018/04/11




Table of Contents

1 Acronyms and related documents ................................................................................ 6

1.1 Acronyms ................................................................................................................... 6

1.2 Related Documents ................................................................................................... 7

2 General description ........................................................................................................ 8

2.1 OpenVPX ................................................................................................................... 9

3 Hardware Specifications ................................................................................................ 9

3.1 Physical specifications ............................................................................................... 9

3.1.1 Air-cooled ............................................................................................................ 9

3.1.2 Conduction-cooled .............................................................................................. 9

3.1.3 ITA 67.1 ............................................................................................................ 10

3.1.4 Backplane keying .............................................................................................. 11

3.1.5 Front panel layout ............................................................................................. 11

3.2 VPX P0 Connector ................................................................................................... 12

3.2.1 Power supply .................................................................................................... 12

3.2.2 Utility plane ....................................................................................................... 13

3.2.3 System reset (SYSRESET*) ............................................................................. 14

3.2.4 Bussed GPIO (GDiscrete1) .............................................................................. 14

3.2.5 P1_SE ............................................................................................................... 14

3.2.6 Battery supply (P1-VBAT) ................................................................................. 14

3.3 VPX P1 Connector ................................................................................................... 14

3.4 VPX P2 Connector ................................................................................................... 17

3.5 Virtex-7 FPGA device .............................................................................................. 20

3.5.1 VCCAUXIO ....................................................................................................... 20

3.6 Front panel I/O ......................................................................................................... 20

3.6.1 UART over USB ................................................................................................ 20

3.6.2 Status LEDs (CPLD) ......................................................................................... 21

3.6.3 Debug LEDs (FPGA) ........................................................................................ 21

3.7 FPGA Mezzanine Card (FMC) ................................................................................. 21

3.7.1 Bank A (LA, HA) connections ........................................................................... 23

3.7.2 Bank B (HB) connections .................................................................................. 26

3.7.3 Gigabit transceiver connections ........................................................................ 28

3.7.4 Miscellaneous FMC connections ...................................................................... 29

3.7.5 I/O Standard Support ........................................................................................ 29

3.7.6 VADJ Programming .......................................................................................... 29

3.8 DDR3 memory banks ............................................................................................... 30

3.9 BLAST sites ............................................................................................................. 35

3.10 Clock Tree ............................................................................................................ 37

3.10.1 AUX_CLK+/- Reference Clock.......................................................................... 37

3.10.2 On-board GTX/GTH Reference Clock .............................................................. 38

3.10.3 FMC GTX/GTH Reference Clock ..................................................................... 39

3.10.4 FMC Clock connections .................................................................................... 39

3.10.5 Miscellaneous clock connections ...................................................................... 40




3.11 Local I2C bus ........................................................................................................ 40

3.11.1 On-board Voltage and Temperature Monitoring (ADT7411) ............................ 42

3.12 Serial FLASH ........................................................................................................ 43

3.13 FPGA Configuration ............................................................................................. 43

3.13.1 JTAG chain ....................................................................................................... 44

3.13.2 FLASH storage ................................................................................................. 44

3.13.3 Configuration Controller (CPLD) ....................................................................... 46

3.13.4 User image programming ................................................................................. 47

3.13.5 Safety Configuration Jumper ............................................................................ 48

3.13.6 Master BPI configuration .................................................................................. 48

4 Environment Specifications ........................................................................................ 48

4.1 Temperature ............................................................................................................ 48

4.2 Convection cooling ................................................................................................... 48

4.3 Conduction cooling .................................................................................................. 49

5 Safety ............................................................................................................................. 49

6 EMC................................................................................................................................ 49

7 Warranty ........................................................................................................................ 49

Appendix A: FPGA Bank Mapping ...................................................................................... 50

Appendix B: Errata ............................................................................................................... 51

Appendix C: BLAST pin outs .............................................................................................. 52

Appendix D: Parallel flash programming with Vivado ...................................................... 57




1 Acronyms and related documents

1.1 Acronyms

ADC Analog-to-Digital Converter

BGA Ball Grid Array

BLAST Board Level Advanced Scalable Technology

DAC Digital-to-Analog Converter

DCI Digitally Controlled Impedance

DDR Double Data Rate

DSP Digital Signal Processing

EPROM Erasable Programmable Read-Only Memory

FBGA Fineline Ball Grid Array

FMC FPGA Mezzanine Card

FPGA Field Programmable Gate Array

GPIO General Purpose Input Output

JTAG Join Test Action Group

LEB Local Expansion Bus

LED Light Emitting Diode

LVTTL Low Voltage Transistor Logic level

LSB Least Significant Bit(s)

LVDS Low Voltage Differential Signaling

GTX/GTH Multi-Gigabit Transceiver

MSB Most Significant Bit(s)

PCB Printed Circuit Board

PCI Peripheral Component Interconnect

PCI-e PCI Express

PLL Phase-Locked Loop

QDR Quadruple Data rate

SBC Single Board Computer

SDRAM Synchronous Dynamic Random Access memory

SOC System-On-Chip

SRAM Synchronous Random Access memory

SSP Synchronous Serial Port

TTL Transistor Logic level

FMC FPGA Mezzanine Card

HPC High pin count

Table 1: Glossary




1.2 Related Documents

• VITA 65 1.0, October 16 2009

• VITA 46.0 1.2, April 2008

• VITA 67.0 January 2012

• VITA 67.1 - Draft

• VITA 57.1 February 2010

• IEEE 1101.2-1992 IEEE Standard for Mechanical Core Specifications for Conduction-Cooled Eurocards

• Xilinx Virtex-7 documentation




2 General description

The VP780 is a high-performance VITA 46 (VPX) compliant card with advanced digital signal processing capabilities. The design has been optimized for the implementation of complex FPGA algorithms with high throughput requirements. Optionally conduction-cooled, the VP780 is in the 3U VPX form factor. It offers up to 4GBytes of DDR3 SDRAM and additional memory options on 2 BLAST sites. A VITA 57 compliant FMC site makes it possible to easily integrate I/O cards with A/D, D/A, RF capabilities, and more. The VP780 is an excellent choice for high-performance applications that require the use of accelerated frequency-domain algorithms such as with FFTs. 4DSP offers many off-the-shelf Intellectual Property (IP) cores for applications that require the highest level of performance.

BLAST2

BLAST1

FFG/FLG1930

XC7VX485T

XC7VX690T

XC7VX980T

XC7VX1140T

JTAG

CPLD LED x4

FMCVITA 57

8x MGT

10Gbps

P0

CPLD

Virtex-6

1Gbit flash(FPGA

bitstreams)

128Mbit SPI flash

160 single ended

80 LVDS pairs

P1

P2

SR

IO/P

CIe

x1

6

LV

DS

x1

8

I2C

optional

4 POSITION SMPM COAX

VITA 67.1

7

OpenVPXVITA 65

FPGA LED x4

DDR31

SDRAM

DDR3SDRAM

DDR3SDRAM

DDR31

SDRAM

1: Not available on the XC7VX485T

Figure 1: VP780 block diagram




2.1 OpenVPX

The VP780 PCB has been designed to accommodate serial lane bit rates of 10 Gigabits per second between the FPGA and the P1 connector (see Table 5 and Table 4) for the detailed locations of these signals). The Virtex-7 FPGAs are capable of driving the serial lanes at 10 Gigabits per second, allowing the user to implement their own high-speed interconnect, such as Aurora, serial rapid IO, or PCI Express Generation 3.

The 4DSP reference design supports x4 PCIe Generation 1 for a XC7VX485T FPGA and Generation 2 for the XC7VX690T, XC7VX980T, and XC7VX1140T FPGAs. Therefore, they are compatible with, but not limited to the following profiles:

- MOD3-PAY-1D-16.2.6-1 (only using lane 0-1)

- MOD3-PAY-2F-16.2.7-1 (only using DP01)

- MOD3-PAY-1F4U-16.2.8-1 (only using DP01)

When ordered with VITA 67 connector:

- MOD3-PAY-1D4R-14.6.1-1 (only using lane 0-1)

- MOD3-PAY-2F4R-14.6.2-1 (only using DP01)

Due to the flexibility of the FPGA, many other profiles are supported but will require a modification to the FPGA firmware.

3 Hardware Specifications

3.1 Physical specifications

The VP780 is a 3U (100x160mm) module that can be ordered as an air-cooled module or a conduction-cooled module.

3.1.1 Air-cooled

The air-cooled VP780 complies with the physical dimensions given in ANSI/VITA 46.0 and VITA 48.1 with the exception that the expected VP780 PCB thickness is 2.14mm instead of 1.60mm. Note that PCB manufacturing tolerances can produce a final PCB thickness between 1.90 and 2.31mm. The typical weight of an air-cooled VP780, including front panel and BLASTs, but excluding the FMC, is 200 grams.

3.1.2 Conduction-cooled

The conduction-cooled VP780 is a 1.0” pitch module that complies with ANSI/VITA 48.2 with the exception that the clamshell is 4.96 mm longer than specified in the VITA 48.2 standard. The clamshell thermal solution is designed to accommodate an FMC bezel which requires extra length. If this is an issue, please contact 4DSP.The clamshell allows system integrators to use their own FMC modules and FMC bezel designs. The clamshell also provides additional VPX connector protection for 2-Level Maintenance requirements. Please contact 4DSP for full 2-Level Maintenance support. The dimensions of the conduction-cooled clamshell are depicted in the following figure.




Figure 2: Conduction-cooled clamshell dimensions (mm)

3.1.3 ITA 67.1

The VP780 implements connectors as per VITA 67.1:

- In the VITA 67.1 configuration, the 4 position Coaxial Interconnect is located in the V46.0 P2 location defined by wafer positions POS_P2.9 to POS_P2.16, as shown in Figure 3.

- POS_P0-1 to POS-P1.8 are implemented using TE Connectivity P/N 1410326-3

- POS_P1-9 thru POS_P2.8 are implemented using TE Connectivity P/N 1410187-3 3.

Figure 3: Wafer designation VITA 67.1

Connections from the VITA 67.1 daughter card coaxial connectors to an FMC board are made using coax cables. The cables are routed inside the clamshell over the top side of the center frame. These cables run all the way to the front of the FMC card, where the cable ends are soldered onto the MMCX connector footprints of the FMC card.




3.1.4 Backplane keying

Both alignment keys 1 and 2 are placed by default with the un-keyed version (1-1469492-9). Contact 4DSP if specific keying is required.

3.1.5 Front panel layout

There are two air-cooled front options: with and without the FMC bezel cut-out. The front side of the conduction-cooled module has an FMC bezel cut-out and some small holes for LED viewing. The following front panel options are available:

Air Cooled

• 0.8 inch (IEEE 1101.10 and VITA 46 compliant)

• 1 inch (IEEE 1101.10 – VITA 46)

• 1 inch – VITA 48.1 (as per VITA 65)

Conduction cooled

• 1 inch – VITA 48.2 (as per VITA 65) (Only for conduction cooled option)

FPGA LED 1

FPGA LED 2

FPGA LED 3

CPLD LED 1

CPLD LED 2

CPLD LED 3

CPLD LED 0

FPGA LED 0

Figure 4: Air-cooled front (left) and conduction-cooled front (right)




3.2 VPX P0 Connector

The connectors pin assignment tables are broken down as per the VITA 46 connector nomenclature (P0, P1, and P2). The wafer positions are also provided.

P0 connector is loaded with three power wafers, three single-ended wafers, and two differential wafers. The following table shows the OpenVPX definition for the P0 connector contacts.

Position Wafer type Row G Row F Row E Row D Row C Row B Row A

POS_P0.1 Power Vs1 Vs1 Vs1 No Pad Vs2 Vs2 Vs2



POS_P0.4 Single-ended

SM2 SM3 GND -12V_AUX GND SYSRESET* NVMRO


GAP* GA4* GND 3.3V_AUX GND SM0 SM1


GA3* GA2* GND +12V_AUX GND GA1* GA0*

POS_P0.7 Differential TCK GND TDO TDI GND TMS TRST*

POS_P0.8 Differential GND REF_CLK- REF_CLK+ GND AUX_CLK- AUX_CLK+ GND

Table 2: VPX P0 connector pin assignment

3.2.1 Power supply

Power is supplied to the VP780 on VPX P0 connector through three power supply voltages: Vs1, Vs2, and Vs3. The voltage levels are 12V, 3.3V, and 5V respectively. Several onboard DC-DC converters generate the appropriate voltage rails for the different devices and interfaces present. The maximum estimated power derived from the backplane is as follows (largest FPGA that is almost filled and all interfaces used):

• Vs1 (12V) : Max. 36 Watt

• Vs2 (3.3V) : Max. 15 Watt

• Vs3 (5V) : Max. 25 Watt

The auxiliary power supplies -12V_Aux and +12V_Aux are not connected. The auxiliary power supply 3.3V_Aux is only used to pull up signals Gdiscrete1 and MaskableReset#.




VPX 0

12V

3.3V

5V

LTM4620

12V to 1.0V(52A Max)

U31

TPS74401RGW

3.3V to 2.5V

U34

LTM4620

5V to 1.8V(13A Max) / 1.5V(13A Max)

U18

TPS74401RGW

1.8V to 1.0V (MGTAVCC)

U30

TPS74401RGW

1.8V to 1.2V (MGTAVTT)

U25

TPS74401RGW

3.3V to 1.8V (MGTAUX)

U28

EN5365QI

3.3V to VADJ (16A Max)

U45

Figure 5: Power Supply Rails

3.2.2 Utility plane

Table 3 shows the utility plane connections to the FPGA. The connections to REF_CLK+/- and AUX_CLK+/- reference clocks are described in section 0. Signals SM2 and SM3 are not connected.

FPGA Pin Net Name FPGA Bank

DIR P0, P1

Connector Pin Number Pin Name

AU33 GA0#1 13 I P0 A6 GA0*

AV33 GA1#1 13 I P0 B6 GA1*

AV34 GA2#1 13 I P0 F6 GA2*

N.C. GA3#1 n.c. I P0 G6 GA3*

N.C. GA4#1 n.c. I P0 F5 GA4*

AP32 GAP#1 13 I P0 G5 GAP*

N.C. NVMRO1 n.c. I P0 A4 NVMRO

AR22 I2C_SCL_VPX1 14 I/O P0 B5 SM0

AL24 I2C_SDA_VPX1 14 I/O P0 A5 SM1

n.c. SYSRESET_I#1 n.c. I P0 B4 SYSRESET*

N.C. GDISCRETE1_I1 n.c. I P1 G1 GDiscrete1

N.C. GDISCRETE1_O1 n.c. O

N.C. MASKABLERESET#1 n.c. I P1 G15 MaskableReset*

N.C. SYS_CON#1 n.c. I P1 G5 SYS_CON*

K3 P1_SE1_R 36 I/O P1 G9 P1_SE1

K4 P1_SE0_R 36 I/O P1 G11 P1_SE0





DIR P0, P1

Connector Pin Number Pin Name

AU22 P1_SE2_R 14 I/O P1 G13 P1_SE2

Note: These signals also connect to the CPLD.

Table 3: Utility plane connections

The I/O standard to be assigned depends on the FPGA bank the signals connect to. Refer to Table 38: BLAST VIO Matrix in Appendix A. The VP780 implements level translation when required.

3.2.3 System reset (SYSRESET*)

The system reset signal is implemented as an input to the CPLD and forwarded to the FPGA. Also, the CPLD can drive the sysreset* (SYSRESET_O#). The VP780 actively drives SYSRESET* low until FPGA configuration is finished, after which SYSRESET* is released (Hi-Z).

3.2.4 Bussed GPIO (GDiscrete1)

The general purpose I/O signal is implemented as an input (GDISCRETE1_I) and as an output (GDISCRETE1_O). When GDISCRETE1_O is driven low, the VP780 actively drives GDiscrete1 low. When GDISCRETE1_O is driven high, GDiscrete1 is placed in a high impedance state. This signal connects to the CPLD.

3.2.5 P1_SE

All three P1_SE signals are routed directly to the FPGA through a zero ohm series resistor that is mounted by default. The P1_SE1 and P1_SE0 are routed as a differential pair and connect to an LVDS input on the FPGA. Through the FPGA configuration this signal can either be a TX or RX signal. The P1_SE2 is routed as single-ended and can be used as a LVCMOS I/O pin.

3.2.6 Battery supply (P1-VBAT)

The VBATT connection on the FPGA is used for data stream encryption and needs a continuous power source. The battery supply from the VPX backplane is used to provide FPGA VBATT. A maximum of 15µA is drawn from the VPX backplane.


The P1 connector has all positions loaded with differential wafers. A total of 32 differential pairs are available configured as 16 transceiver pairs. The VP780 connects all of those signals to GTX/GTH blocks on the FPGA. Examples of possible applications are 2 x 8 lanes PCI Express or other high-speed differential protocols like Aurora or sFPDP. The single-ended signals are part of the utility plane described in section 3.2.2.




Position Wafer type

Row G Row F Row E Row D Row C Row B Row A

POS_P1.1 Differential Gdiscrete1 GND P1-TX0- P1-TX0+ GND P1-RX0- P1-RX0+

POS_P1.2 Differential GND P1-TX1- P1-TX1+ GND P1-RX1- P1-RX1+ GND

POS_P1.3 Differential P1-VBAT GND P1-TX2- P1-TX2+ GND P1-RX2- P1-RX2+


POS_P1.5 Differential SYS_CON* GND P1-TX4- P1-TX4+ GND P1-RX4- P1-RX4+


POS_P1.7 Differential Reserved GND P1-TX6- P1-TX6+ GND P1-RX6- P1-RX6+


POS_P1.9 Differential P1-SE0 GND P1-TX8- P1-TX8+ GND P1-RX8- P1-RX8+






POS_P1.15 Differential Maskable

reset* GND P1-TX14- P1-TX14+ GND P1-RX14- P1-RX14+


Table 4: VPX P1 connector pin assignment

FPGA Pin Net Name GTX/GTH

Block

P1

Pin Number Pin Name

AW5 P1_RXn00

114

B1 P1_RX0-

AW6 P1_RXp00 A1 P1_RX0+

AV3 P1_TXn00 E1 P1_TX0-

AV4 P1_TXp00 D1 P1_TX0+

AU5 P1_RXn01

114

C2 P1_RX1-

AU6 P1_RXp01 B2 P1_RX1+

AU1 P1_TXn01 F2 P1_TX1-

AU2 P1_TXp01 E2 P1_TX1+

AT3 P1_RXn02

114

B3 P1_RX2-

AT4 P1_RXp02 A3 P1_RX2+

AR1 P1_TXn02 E3 P1_TX2-

AR2 P1_TXp02 D3 P1_TX2+

AR5 P1_RXn03

114

C4 P1_RX3-

AR6 P1_RXp03 B4 P1_RX3+

AP3 P1_TXn03 F4 P1_TX3-

AP4 P1_TXp03 E4 P1_TX3+

AN5 P1_RXn04

115

B5 P1_RX4-

AN6 P1_RXp04 A5 P1_RX4+

AN1 P1_TXn04 E5 P1_TX4-





Block

P1

Pin Number Pin Name

AN2 P1_TXp04 D5 P1_TX4+

AL5 P1_RXn05

115

C6 P1_RX5-

AL6 P1_RXp05 B6 P1_RX5+

AL1 P1_TXn05 F6 P1_TX5-

AL2 P1_TXp05 E6 P1_TX5+

AM3 P1_RXn06

115

B7 P1_RX6-

AM4 P1_RXp06 A7 P1_RX6+

AK3 P1_TXn06 E7 P1_TX6-

AK4 P1_TXp06 D7 P1_TX6+

AJ5 P1_RXn07

115

C8 P1_RX7-

AJ6 P1_RXp07 B8 P1_RX7+

AJ1 P1_TXn07 F8 P1_TX7-

AJ2 P1_TXp07 E8 P1_TX7+

AD3 P1_RXn08

117

B9 P1_RX8-

AD4 P1_RXp08 A9 P1_RX8+

AB3 P1_TXn08 E9 P1_TX8-

AB4 P1_TXp08 D9 P1_TX8+

AA5 P1_RXn09

117

C10 P1_RX9-

AA6 P1_RXp09 B10 P1_RX9+

AA1 P1_TXn09 F10 P1_TX9-

AA2 P1_TXp09 E10 P1_TX9+

Y3 P1_RXn10

117

B11 P1_RX10-

Y4 P1_RXp10 A11 P1_RX10+

W1 P1_TXn10 E11 P1_TX10-

W2 P1_TXp10 D11 P1_TX10+

W5 P1_RXn11

117

C12 P1_RX11-

W6 P1_RXp11 B12 P1_RX11+

V3 P1_TXn11 F12 P1_TX11-

V4 P1_TXp11 E12 P1_TX11+

U5 P1_RXn12

118

B13 P1_RX12-

U6 P1_RXp12 A13 P1_RX12+

U1 P1_TXn12 E13 P1_TX12-

U2 P1_TXp12 D13 P1_TX12+

T3 P1_RXn13

118

C14 P1_RX13-

T4 P1_RXp13 B14 P1_RX13+

R1 P1_TXn13 F14 P1_TX13-

R2 P1_TXp13 E14 P1_TX13+

R5 P1_RXn14 118

B15 P1_RX14-

R6 P1_RXp14 A15 P1_RX14+





Block

P1

Pin Number Pin Name

P3 P1_TXn14 E15 P1_TX14-

P4 P1_TXp14 D15 P1_TX14+

N5 P1_RXn15

118

C16 P1_RX15-

N6 P1_RXp15 B16 P1_RX15+

N1 P1_TXn15 F16 P1_TX15-

N2 P1_TXp15 E16 P1_TX15+

Table 5: VPX P1 connections


The P2 connector has positions 1 to 8 loaded with differential wafers. A total of 16 differential pairs are available on the P2 connector and four single-ended signals. The VP780 connects the 16 differential signals and the single-ended signals to the LVDS pins of the FPGA. This means a total of 18 bi-directional LVDS pairs (or 36 single-ended) are available.

Position Wafer type Row G Row F Row E Row D Row C Row B Row A

POS_P2.1 Differential P2-DP16- GND P2-DP1- P2-DP1+ GND P2-DP0- P2-DP0+

POS_P2.2 Differential GND P2-DP3- P2-DP3+ GND P2-DP2- P2-DP2+ GND

POS_P2.3 Differential P2-DP16+ GND P2-DP5- P2-DP5+ GND P2-DP4- P2-DP4+


POS_P2.5 Differential P2-DP17- GND P2-DP9- P2-DP9+ GND P2-DP8- P2-DP8+


POS_P2.7 Differential P2-DP17+ GND P2-DP13- P2-DP13+ GND P2-DP12- P2-DP12+


POS_P2.9

Analo

g

4 POSITION SMPM COAX

POS_P2.10

POS_P2.11

POS_P2.12

POS_P2.13

POS_P2.14

POS_P2.15

POS_P2.16

Table 6: VPX P2 connector pin assignments

FPGA Pin Net Name P2

Pin Number Pin Name

J1 P2_DPn00 B1 P2_DP0-





Pin Number Pin Name

J2 P2_DPp00 A1 P2_DP0+

J4 P2_DPn01 E1 P2_DP1-

J5 P2_DPp01 D1 P2_DP1+

G1 P2_DPn02 C2 P2_DP2-

H2 P2_DPp02 B2 P2_DP2+

H5 P2_DPn03 F2 P2_DP3-

J6 P2_DPp03 E2 P2_DP3+

H3 P2_DPn04 B3 P2_DP4-

H4 P2_DPp04 A3 P2_DP4+

G5 P2_DPn05 E3 P2_DP5-

G6 P2_DPp05 D3 P2_DP5+

D4 P2_DPn06 C4 P2_DP6-

E4 P2_DPp06 B4 P2_DP6+

E1 P2_DPn07 F4 P2_DP7-

F1 P2_DPp07 E4 P2_DP7+

D5 P2_DPn08 B5 P2_DP8-

E6 P2_DPp08 A5 P2_DP8+

D1 P2_DPn09 E5 P2_DP9-

D2 P2_DPp09 D5 P2_DP9+

C4 P2_DPn10 C6 P2_DP10-

C5 P2_DPp10 B6 P2_DP10+

B2 P2_DPn11 F6 P2_DP11-

C2 P2_DPp11 E6 P2_DP11+

F3 P2_DPn12 B7 P2_DP12-

F4 P2_DPp12 A7 P2_DP12+

G2 P2_DPn13 E7 P2_DP13-

G3 P2_DPp13 D7 P2_DP13+

A5 P2_DPn14 C8 P2_DP14-

B5 P2_DPp14 B8 P2_DP14+

B3 P2_DPn15 F8 P2_DP15-

C3 P2_DPp15 E8 P2_DP15+

A6 P2_DPn16 G1 P2_DP16-

B6 P2_DPp16 G3 P2_DP16+





Pin Number Pin Name

A3 P2_DPn17 G5 P2_DP17-

A4 P2_DPp17 G7 P2_DP17+

Table 7: VPX P2 connections




3.5 Virtex-7 FPGA device

The Virtex-7 FPGA device is the DSP processing node of the VP780. Any Virtex-7 FPGA device FLG1930 or FFG1930 package can be ordered:

• XC7VX485T (only two of the four DDR3 banks are available)

• XC7VX690T

• XC7VX980T

• XC7VX1140T

3.5.1 VCCAUXIO

The VP780 connects the VCCAUXIO to a fixed 1.8V power supply. It is therefore not possible to run the DDR3 memory interfaces at the maximum possible frequency as indicated by the Virtex-7 data sheet (DS183 (v1.18) November 26, 2013, Table 18: Maximum Physical Interface (PHY) Rate for Memory Interfaces IP available with the Memory Interface Generator).

Below is a table shows an excerpt from this table. 4DSP has not been able to characterise the VP780 with all speed grades. Our default reference designs operate the DDR3 at 1000 Mb/s.

Memory

standard

FPGA speed grade units

-1 -2 -3

DDR3 1066 1333 1600 Mb/s

Table 8: Maximum PHY rate for memory interface IP available from Xilinx targeting the FM780

3.6 Front panel I/O

The VP780 reserves the front panel I/O area for the FMC site. In addition there is a UART over USB option for debugging purposes. The UART connects to the CPLD directly and no special function has been assigned to it. There are also some status and debug LEDs available.

3.6.1 UART over USB

One UART connection is optionally available on the front panel via a mini-USB connector (J2). Its location is depicted in Figure 11. The serial interface is made using a USB to UART Bridge (CP2102). The UART side connects to the CPLD.

CPLD Pin Net Name DIR CP2102

Pin Number Pin Name

H3 UART_TXD O 26 TXD

H4 UART_RXD I 25 RXD

Table 9: UART connections

The I/O standard to be assigned is LVCMOS 1V8. The VP780 implements level translation.

The CPLD revision 1.6 or later, allows the FPGA to use UART interface by assigning the following pins as below.


DIR

AK23 RXD 14 I

AK36 TXD 15 O




AU23 UART_ENABLE 14 O

When UART_ENABLE is asserted, the UART connections go through the CPLD, transparently, to the USB-UART chipset.

When UART_ENABLE is not asserted, the mentioned CPLD pins will perform a proprietary function, used in combination with the 4DSP host interface design.

3.6.2 Status LEDs (CPLD)

Four LEDs are connected to the CPLD for board status purposes. There is a pre-defined function for these LEDs. One LED (CPLD LED 0) is located on the component side of the VP780. The other LEDs are located on the solder side of the VP780 (see Figure 4).

OFF ON FLASHING

LED 0

(red)

Power OK VADJ not OK Power not OK

(ex. VADJ)

LED 1

(red)

FPGA configured FPGA not configured Loading from FLASH

LED 2

(red)

FLASH idle FLASH busy Safety configuration loaded into FPGA or attempted to load safety

LED 3

(red)

No CRC error during FPGA configuration

reserved CRC error during FPGA configuration

Table 10: CPLD LED board status

3.6.3 Debug LEDs (FPGA)

Four red LEDs are connected to the FPGA for debugging purposes. There is no predefined function for these LEDs. One LED (FPGA_LED0) is located on the component side of the VP780. The other LEDs are located on the solder side of the VP780 (see Figure 4).

To turn on a LED, drive the signal low. To turn a LED off, make the signal Hi-Z.


DIR

B27 FPGA_LED0 33 O

BC22 FPGA_LED1 14 O

AN24 FPGA_LED2 14 O

B28 FPGA_LED3 33 O

Table 11: LED connections

The I/O standard to be assigned depends on the FPGA bank the signals connect to. Refer to Table 38: BLAST VIO Matrix in the Appendix A. The VP780 implements level translation.

3.7 FPGA Mezzanine Card (FMC)

The Virtex-7 FPGA interfaces to an FPGA Mezzanine Card (FMC) via a high pin count (HPC) VITA 57.1 site. All the differential and control signals are connected to the Virtex-7 FPGA. Not




all of the Gigabit transceivers are connected. The VP780 only connects the 8 lower ones (DP_M2C[7..0] and DP_C2M[7..0]).

The FMC site provides flexibility for adding analog and/or digital IO via customer developed, third party, or 4DSP FMC boards. 4DSP offers a wide variety of FMC cards that can be used on the VP780: http://www.4dsp.com/fmc.php


http://www.4dsp.com/fmc.php



3.7.1 Bank A (LA, HA) connections

Differential routing is applied with matched delay on all pairs within bank A (LA, HA).

FPGA Pin Net Name FMC HPC

Pin Number Pin Name

AJ41 LA_N00_CC G7 LA00_N_CC

AJ40 LA_P00_CC G6 LA00_P_CC

AH40 LA_N01_CC D9 LA01_N_CC

AG40 LA_P01_CC D8 LA01_P_CC

AF44 LA_N02 H8 LA02_N

AE44 LA_P02 H7 LA02_P

AK44 LA_N03 G10 LA03_N

AK43 LA_P03 G9 LA03_P



AK42 LA_N05 D12 LA05_N

AJ42 LA_P05 D11 LA05_P

AD40 LA_N06 C11 LA06_N

AD39 LA_P06 C10 LA06_P

AG41 LA_N07 H14 LA07_N

AF41 LA_P07 H13 LA07_P

AE42 LA_N08 G13 LA08_N

AE41 LA_P08 G12 LA08_P

AH42 LA_N09 D15 LA09_N

AG42 LA_P09 D14 LA09_P

AG38 LA_N10 C15 LA10_N

AF38 LA_P10 C14 LA10_P

AJ44 LA_N11 H17 LA11_N

AH44 LA_P11 H16 LA11_P

AH43 LA_N12 G16 LA12_N

AG43 LA_P12 G15 LA12_P

AE37 LA_N13 D18 LA13_N

AD36 LA_P13 D17 LA13_P

AH38 LA_N14 C19 LA14_N

AG37 LA_P14 C18 LA14_P

AE39 LA_N15 H20 LA15_N


AJ37 LA_N16 G19 LA16_N

AH37 LA_P16 G18 LA16_P

AF40 LA_N17_CC D21 LA17_N_CC

AF39 LA_P17_CC D20 LA17_P_CC

AJ39 LA_N18_CC C23 LA18_N_CC

AH39 LA_P18_CC C22 LA18_P_CC

AD35 LA_N19 H23 LA19_N





Pin Number Pin Name

AD34 LA_P19 H22 LA19_P

AF34 LA_N20 G22 LA20_N

AE34 LA_P20 G21 LA20_P



AG36 LA_N22 G25 LA22_N

AF35 LA_P22 G24 LA22_P

AH35 LA_N23 D24 LA23_N

AG35 LA_P23 D23 LA23_P

AA44 LA_N24 H29 LA24_N

AA43 LA_P24 H28 LA24_P

V44 LA_N25 G28 LA25_N

V43 LA_P25 G27 LA25_P

AC44 LA_N26 D27 LA26_N

AD44 LA_P26 D26 LA26_P

W44 LA_N27 C27 LA27_N

Y44 LA_P27 C26 LA27_P

AB43 LA_N28 H32 LA28_N

AC43 LA_P28 H31 LA28_P

Y43 LA_N29 G31 LA29_N

Y42 LA_P29 G30 LA29_P

V42 LA_N30 H35 LA30_N

W42 LA_P30 H34 LA30_P

AB42 LA_N31 G34 LA31_N

AC42 LA_P31 G33 LA31_P

AA41 LA_N32 H38 LA32_N

AB41 LA_P32 H37 LA32_P

AD42 LA_N33 G37 LA33_N

AD41 LA_P33 G36 LA33_P

Table 12: FMC LA connections





Pin Number Pin Name

W41 HA_N00_CC F5 HA00_N_CC

Y41 HA_P00_CC F4 HA00_P_CC

AB40 HA_N01_CC E3 HA01_N_CC

AC40 HA_P01_CC E2 HA01_P_CC

W40 HA_N02 K8 HA02_N

Y39 HA_P02 K7 HA02_P

AA40 HA_N03 J7 HA03_N

AA39 HA_P03 J6 HA03_P

AA38 HA_N04 F8 HA04_N

AB38 HA_P04 F7 HA04_P

W37 HA_N05 E7 HA05_N

Y37 HA_P05 E6 HA05_P

AC39 HA_N06 K11 HA06_N

AC38 HA_P06 K10 HA06_P

W39 HA_N07 J10 HA07_N

Y38 HA_P07 J9 HA07_P

Y36 HA_N08 F11 HA08_N

AA36 HA_P08 F10 HA08_P

W35 HA_N09 E10 HA09_N

W34 HA_P09 E9 HA09_P

AA35 HA_N10 K14 HA10_N

AB35 HA_P10 K13 HA10_P

Y34 HA_N11 J13 HA11_N

AA34 HA_P11 J12 HA11_P

AB37 HA_N12 F14 HA12_N

AB36 HA_P12 F13 HA12_P

AC35 HA_N13 E13 HA13_N

AC34 HA_P13 E12 HA13_P

T31 HA_N14 J16 HA14_N

T30 HA_P14 J15 HA14_P

R32 HA_N15 F17 HA15_N

R31 HA_P15 F16 HA15_P

U31 HA_N16 E16 HA16_N

U30 HA_P16 E15 HA16_P

P37 HA_N17_CC K17 HA17_N_CC

R37 HA_P17_CC K16 HA17_P_CC

T38 HA_N18_CC J19 HA18_N

U38 HA_P18_CC J18 HA18_P

T34 HA_N19 F20 HA19_N

T33 HA_P19 F19 HA19_P

U37 HA_N20 E19 HA20_N





Pin Number Pin Name

U36 HA_P20 E18 HA20_P

P36 HA_N21 K20 HA21_N

R36 HA_P21 K19 HA21_P

U35 HA_N22 J22 HA22_N

V35 HA_P22 J21 HA22_P

T36 HA_N23 K23 HA23_N

T35 HA_P23 K22 HA23_P

Table 13: FMC HA connections

3.7.2 Bank B (HB) connections

Differential routing is applied with matched delay on all pairs within bank B (HB).


Pin Number Pin Name

V38 HB_N00_CC K26 HB00_N_CC

V37 HB_P00_CC K25 HB00_P_CC

R34 HB_N01 J25 HB01_N

R33 HB_P01 J24 HB01_P

U33 HB_N02 F23 HB02_N

U32 HB_P02 F22 HB02_P

T40 HB_N03 E22 HB03_N

T39 HB_P03 E21 HB03_P

P40 HB_N04 F26 HB04_N

P39 HB_P04 F25 HB04_P

V40 HB_N05 E25 HB05_N

V39 HB_P05 E24 HB05_P

R39 HB_N06_CC K29 HB06_N_CC

R38 HB_P06_CC K28 HB06_P_CC

U41 HB_N07 J28 HB07_N

U40 HB_P07 J27 HB07_P

R41 HB_N08 F29 HB08_N

T41 HB_P08 F28 HB08_P

U43 HB_N09 E28 HB09_N

U42 HB_P09 E27 HB09_P

P42 HB_N10 K32 HB10_N

P41 HB_P10 K31 HB10_P

T44 HB_N11 J31 HB11_N

T43 HB_P11 J30 HB11_P

R43 HB_N12 F32 HB12_N

R42 HB_P12 F31 HB12_P

P44 HB_N13 E31 HB13_N





Pin Number Pin Name

R44 HB_P13 E30 HB13_P

AP40 HB_N14 K35 HB14_N

AP39 HB_P14 K34 HB14_P

AL39 HB_N15 J34 HB15_N

AK39 HB_P15 J33 HB15_P

AP42 HB_N16 F35 HB16_N

AN42 HB_P16 F34 HB16_P

AL38 HB_N17_CC K38 HB17_N_CC

AK38 HB_P17_CC K37 HB17_P_CC

AM38 HB_N18 J37 HB18_N

AM37 HB_P18 J36 HB18_P

AL41 HB_N19 E34 HB19_N

AK41 HB_P19 E33 HB19_P

AN43 HB_N20 F38 HB20_N

AM43 HB_P20 F37 HB20_P

AP41 HB_N21 E37 HB21_N

AN40 HB_P21 E36 HB21_P

Table 14: FMC HB connections




3.7.3 Gigabit transceiver connections

The VP780 connects the lowest eight DP signals on the FMC connector to gigabit transceivers (GTX/GTH blocks) on the FPGA. The other DP signals are left unconnected. The reference clock connections are described in section 3.10.3.

FPGA Pin Net Name GTX/GTH Block FMC HPC

Pin Number Pin Name

AW1 DP_C2M_N0

113

C3 DP0_C2M_N

AW2 DP_C2M_P0 C2 DP0_C2M_P

AY3 DP_M2C_N0 C7 DP0_M2C_N

AY4 DP_M2C_P0 C6 DP0_M2C_P

BA1 DP_C2M_N1

113

A23 DP1_C2M_N

BA2 DP_C2M_P1 A22 DP1_C2M_P

BA5 DP_M2C_N1 A3 DP1_M2C_N

BA6 DP_M2C_P1 A2 DP1_M2C_P

BB3 DP_C2M_N2

113

A27 DP2_C2M_N

BB4 DP_C2M_P2 A26 DP2_C2M_P

BC5 DP_M2C_N2 A7 DP2_M2C_N

BC6 DP_M2C_P2 A6 DP2_M2C_P

BD3 DP_C2M_N3

113

A31 DP3_C2M_N

BD4 DP_C2M_P3 A30 DP3_C2M_P

BD7 DP_M2C_N3 A11 DP3_M2C_N

BD8 DP_M2C_P3 A10 DP3_M2C_P

AC1 DP_C2M_N4 116 A35 DP4_C2M_N

AC2 DP_C2M_P4 A34 DP4_C2M_P

AC5 DP_M2C_N4 A15 DP4_M2C_N

AC6 DP_M2C_P4 A14 DP4_M2C_P

AE1 DP_C2M_N5 116 A39 DP5_C2M_N

AE2 DP_C2M_P5 A38 DP5_C2M_P

AE5 DP_M2C_N5 A19 DP5_M2C_N

AE6 DP_M2C_P5 A18 DP5_M2C_P

AF3 DP_C2M_N6 116 B37 DP6_C2M_N

AF4 DP_C2M_P6 B36 DP6_C2M_P

AH3 DP_M2C_N6 B17 DP6_M2C_N

AH4 DP_M2C_P6 B16 DP6_M2C_P

AG1 DP_C2M_N7 116 B33 DP7_C2M_N

AG2 DP_C2M_P7 B32 DP7_C2M_P

AG5 DP_M2C_N7 B13 DP7_M2C_N

AG6 DP_M2C_P7 B12 DP7_M2C_P

Table 15: FMC GTX/GTH connections




3.7.4 Miscellaneous FMC connections

The differential clock connections are described in section 3.10.4. The global address pins (GA0 and GA1) on the FMC site are tied to ground. PG_C2M is connected to the FPGA (Please refer to the errata section for more information). Power pin 3P3VAUX is connected to 3P3V on the VP780.


DIR FMC HPC

Pin Number Pin Name

AR33 I2C_SCL_FMC 13 IO C30 SCL

AT33 I2C_SDA_FMC 13 IO C31 SDA

AL44 PG_M2C 15 I F1 PG_M2C

AN44 PRSNT_M2C_L 15 I H2 PRSNT_M2C_L

AL43 PG_C2M 15 O D1 PG_C2M

Table 16: Miscellaneous FMC connections

The I/O standard to be assigned depends on VADJ configuration. Refer to Table 38: BLAST VIO Matrix in the Appendix. The VP780 implements proper level translation.

3.7.5 I/O Standard Support

The VP780 is optimized for differential signalling, but any single-ended I/O standard supported by the FPGA can be used as well. All FMC banks connect to FPGA banks powered by VADJ.

Reference voltages from the FMC (VREF_A_M2C, VREF_B_M2C) are not connected. I/O standards that require a reference voltage should use the internal Vref features of the FPGA. The following reference voltages are supported:

• 0.60V

• 0.675V

• 0.75V

• 0.9V

Please contact 4DSP for I/O standards that require Digitally Controlled Impedance (DCI).

3.7.6 VADJ Programming

The VADJ is controlled by the CPLD. The CPLD will set the VADJ to 1V8 by default and enable it immediately on power up. Please contact 4DSP if another VADJ voltage level is required.

VADJ

1.8V (default)

1.5V

1.25V

1.2V

Table 17: Supported VADJ voltage levels

Although the VITA 57.1 standard states that VADJ can go up to 3.3V, the Virtex-7 FPGA HP banks do not support this voltage level. They are limited to 1.8V single-ended. All attached FMCs must support this requirement or the Virtex-7 may be damaged.




In order to access the flash, the Flash configuration signals on bank 15 should be LVCMOS18. Therefore, only VADJ of 1V8 is supported when the FPGA configures the flash directly.

3.8 DDR3 memory banks

A total of four dedicated DDR3 memory banks are available on the VP780. The banks are built using a single MT41J512M8 device per bank. Two of the four banks (those that connect to I/O banks 10 and 11) are not available on the XC7VX485T FPGA device because it does not bond these two I/O banks to the silicon. The other two devices connect to I/O banks 13 and 33 and are available for all supported FPGA device types.




FPGA Pin Bank Net name

AT44 13 DDR3_C0_DQ0

AV43 13 DDR3_C0_DQ1

AV44 13 DDR3_C0_DQ2

AU42 13 DDR3_C0_DQ3

AV42 13 DDR3_C0_DQ4

AR42 13 DDR3_C0_DQ5

AR43 13 DDR3_C0_DQ6

AR41 13 DDR3_C0_DQ7

AR39 13 DDR3_C0_ADDR15

AT40 13 DDR3_C0_ADDR14

AV40 13 DDR3_C0_ADDR13

AW40 13 DDR3_C0_ADDR12

AU40 13 DDR3_C0_ADDR11












AP36 13 DDR3_C0_BA2

AR37 13 DDR3_C0_BA1

AV35 13 DDR3_C0_BA0

AW35 13 DDR3_C0_RAS_N

AR36 13 DDR3_C0_CAS_N

AT36 13 DDR3_C0_WE_N

AW37 13 DDR3_C0_RESET_N

AT34 13 DDR3_C0_CKE

AU32 13 DDR3_C0_ODT

AW36 13 DDR3_C0_CS_N

AR44 13 DDR3_C0_DM

AT43 13 DDR3_C0_DQS_P

AU43 13 DDR3_C0_DQS_N

AP34 13 DDR3_C0_CK_P

AR34 13 DDR3_C0_CK_N

Table 18: DDR3 bank 1 connections





T29 33 DDR3_C1_DQ0

T26 33 DDR3_C1_DQ1

R26 33 DDR3_C1_DQ2

P26 33 DDR3_C1_DQ3

P27 33 DDR3_C1_DQ4

N27 33 DDR3_C1_DQ5

N28 33 DDR3_C1_DQ6

R27 33 DDR3_C1_DQ7

M27 33 DDR3_C1_ADDR15

M28 33 DDR3_C1_ADDR14

L28 33 DDR3_C1_ADDR13

K28 33 DDR3_C1_ADDR12

L29 33 DDR3_C1_ADDR11



J27 33 DDR3_C1_ADDR08



H29 33 DDR3_C1_ADDR05

H30 33 DDR3_C1_ADDR04

A29 33 DDR3_C1_RESET_N

C29 33 DDR3_C1_CKE

G27 33 DDR3_C1_ADDR01

G28 33 DDR3_C1_ADDR00

E27 33 DDR3_C1_BA2

D27 33 DDR3_C1_BA1

F29 33 DDR3_C1_BA0

E29 33 DDR3_C1_RAS_N

F28 33 DDR3_C1_CAS_N

E28 33 DDR3_C1_WE_N

F30 33 DDR3_C1_ADDR03

D29 33 DDR3_C1_ADDR02

A28 33 DDR3_C1_ODT

G30 33 DDR3_C1_CS_N

T28 33 DDR3_C1_DM

R29 33 DDR3_C1_DQS_P

P29 33 DDR3_C1_DQS_N

C27 33 DDR3_C1_CK_P

C28 33 DDR3_C1_CK_N






AJ31 10 DDR3_C2_DQ0

AK29 10 DDR3_C2_DQ1

AL29 10 DDR3_C2_DQ2

AH29 10 DDR3_C2_DQ3

AH30 10 DDR3_C2_DQ4

AK31 10 DDR3_C2_DQ5

AL31 10 DDR3_C2_DQ6

AN29 10 DDR3_C2_DQ7

AP31 10 DDR3_C2_ADDR15
















AW29 10 DDR3_C2_BA2

AY29 10 DDR3_C2_BA1

AY31 10 DDR3_C2_BA0

AY32 10 DDR3_C2_RAS_N

BA28 10 DDR3_C2_CAS_N

BA29 10 DDR3_C2_WE_N

BA31 10 DDR3_C2_RESET_N

BB31 10 DDR3_C2_CKE

BC32 10 DDR3_C2_ODT

BA30 10 DDR3_C2_CS_N

AJ30 10 DDR3_C2_DM

AL30 10 DDR3_C2_DQS_P

AM30 10 DDR3_C2_DQS_N

BD30 10 DDR3_C2_CK_P

BD31 10 DDR3_C2_CK_N






AY44 11 DDR3_C3_DQ0

BC42 11 DDR3_C3_DQ1

BD42 11 DDR3_C3_DQ2

BB42 11 DDR3_C3_DQ3

BC43 11 DDR3_C3_DQ4

BA43 11 DDR3_C3_DQ5

BB43 11 DDR3_C3_DQ6

AW42 11 DDR3_C3_DQ7


AY41 11 DDR3_C3_ADDR14

BB40 11 DDR3_C3_ADDR13


BA40 11 DDR3_C3_ADDR11


BC40 11 DDR3_C3_ADDR09

BD41 11 DDR3_C3_ADDR08

AY39 11 DDR3_C3_ADDR07


BC39 11 DDR3_C3_ADDR05

BD40 11 DDR3_C3_ADDR04





AY37 11 DDR3_C3_BA2

AY38 11 DDR3_C3_BA1

BC37 11 DDR3_C3_BA0

BD37 11 DDR3_C3_RAS_N

AY36 11 DDR3_C3_CAS_N

BA36 11 DDR3_C3_WE_N

BA34 11 DDR3_C3_RESET_N

BC34 11 DDR3_C3_CKE

BD34 11 DDR3_C3_ODT

BB33 11 DDR3_C3_CS_N

AW44 11 DDR3_C3_DM

AY43 11 DDR3_C3_DQS_P

BA44 11 DDR3_C3_DQS_N

BD35 11 DDR3_C3_CK_P

BD36 11 DDR3_C3_CK_N





3.9 BLAST sites

Thanks to the availability of two BLAST sites, a wide variety of memory and processing modules can be connected to the FPGA. It is possible to choose from the list of available BLAST modules for each BLAST site.

For more information about the available BLASTs on the VP780, please consult the following page: BLAST modules http://www.4dsp.com/BLAST.htm

Due to its small form factor and ease of design, the BLAST modules enable a rapid solution for custom memory or processing requirements.

BLAST Form Factor BLAST 1 BLAST 1

Single BLAST YES YES

Single Extended BLAST YES YES

Double BLAST No

Double Extended BLAST No

Table 22: BLAST Configuration options

BLAST Type BLAST 1 BLAST 1

16MB QDRII+ (F) YES YES

ADV212 JPEG2000 (C) NO NO

32GB NAND FLASH (E) YES YES

4GB DDR3 (H) YES YES

Table 23: BLAST Memory/Processing options

Power is applied depending on the BLAST type. Each BLAST site has three voltage rails:

- Vcore : 3.3V, 2.5V, 1.8V, 1.5V

- Vio : 1.8V, 1.5V

- Vref : 0.9V, 0.75V

QDRII+

GS81302QT37GE-300I

FLASH_AMT29F128G08AMCABH2-

10IT

FLASH_BMT29F128G08AMCABH2-

10IT

QDRII+ BLAST (F) FLASH BLAST (E)

MT4

1K1G

8TR

F-

125I

T

4GB DDR3 BLAST (F)

MT4

1K

1G8

TRF-

125I

T

MT4

1K1G

8TR

F-

125I

T

MT4

1K

1G8

TRF-

125I

T

Figure 6: BLAST architectures


http://www.4dsp.com/BLAST.htm



The pin out tables of the BLAST can be found in Appendix C: BLAST pin outs .




3.10 Clock Tree

The VP780 clock architecture offers an efficient distribution of low-jitter clocks to facilitate efficient implementation of fast off-chip communication with other peripherals. The VPX backplane offers two reference clock signals (AUX_CLK and REF_CLK) that can be used by plug-in modules for synchronisation between different plug-in modules in a VPX system.

P0

AUX_CLKSN65MLVD2

REF_CLKSN65MLVD2

100 MHz

oscillator

25MHz or

100MHz

GBTCLK1_M2C

16 MHz

crystal

MGTREFCLK1P/N_115Clock

Synthesizer

CDCEL925

CPLD

Differential Single ended

F6

AP21

E2/E3

AL23

FPGA

VITA 57.1FMC

FMC MGT CLK

80MHz

oscilator

200 MHz

oscilator

SN74AVC4T245

AM41/AM42AL40/AM40

MGTREFCLK0P/N_115

MGTREFCLK0P/N_116

MGTREFCLK1P/N_116

MGTREFCLK0P/N_117MGTREFCLK1P/N_117


H27/H28300 MHz

oscilator

MGTREFCLK0P/N_113

MGTREFCLK1P/N_113

MGTREFCLK0P/N_114

MGTREFCLK1P/N_114

GBTCLK0_M2C

AR32

AJ36/AK37AN38/AN39CLK1_M2C

CLK0_M2C

CLK3_BIDIR

CLK2_BIDIR

100MHz

100MHz

100MHz

100MHz

100MHz

100MHz

Si5338(alt. Si5335)

Si5338(alt. Si5335)100MHz

Figure 7: Clock architecture

3.10.1 AUX_CLK+/- Reference Clock

AUX_CLK is a 1pps timing reference. It is defined with relatively tight accuracy and stability specifications, and it is driven differentially on the backplane. This signal is typically used in OpenVPX applications to provide a high-precision hardware timing delimiter for time-based processing tasks. The VP780 buffers and translates this clock into a single-ended LVCMOS15 signal before connecting it to the FPGA.

FPGA Pin

Net Name FPGA Bank

DIR

P0

Connector Pin

Number Pin Name

AR32 AUX_CLK 13 I P0 C8 AUX_CLK-

P0 B8 AUX_CLK+

Table 24: AUX_CLK connection

The REF_CLK is a reference clock with tight accuracy and stability specifications that is driven differentially on the backplane. One of the uses of this signal is to provide a common clock to synchronize all plug-in modules. This enables the implementation of Spread Spectrum Clocking (SSC) to reduce EMI in a system (PCIe, for example, defines the use of this mechanism for SSC). It is anticipated that a plug-in module receives the reference clock and can phase lock to the desired operational frequency.

Initial revisions of the OpenVPX specifications recommend a 25 MHz clock for this signal. However, the OpenVPX work group recently suggested implementing a 100 MHz clock to be




used directly as a reference for PCI Express Gen 2/3 applications. For asynchronous PCIe clocking, refer to section 3.10.2.

The VP780 implements a clock architecture that works for both cases. First the REF_CLK is translated to LVCMOS (SN65MLVD2) and then buffered using the Si5335 where the output is differential LVDS. The differential output is capable of being PCIe Gen3 compliant with spread spectrum at 100 MHz.

The single-ended clock connects to a clock generator (Si5338) capable of creating clock frequencies in a number of standards, including Single-Ended and LVDS from 1 to 350 MHz from clock reference range of 10 to 350 MHz using a variety of clock sources. The Si5338 is factory-programmed for a default power-on image and can be updated to change the desired frequencies using the I2C interface. It supports up to four independent clocks from the same source.

The default Si5338 device that is mounted by 4DSP requires an I2C write to select the IN3 clock input as the source for the PLL. To support a spread spectrum clock, the internal PLL should be bypassed as well to directly distribute the external input clock to the output clocks. Additionally, it is possible to program a different reference clock for each output using the I2C interface.

Contact 4DSP in case you want to have the clock PLL to select the correct clock directly after power-up.

Each version of the buffered reference clock is distributed to the GTP reference clock inputs in such a way that they can be used to clock all the GTPs that connect to the P1 connector. The table below describes which GTP reference clocks are used and which GTPs can be reached.

Si5338 Output FPGA Pin Net name GTP REFCLK GTPs reached

2 V7 VPX_100M_REFCLK0N GTX/GTHREFCLK1_118 117, 118

V8 VPX_100M_REFCLK0P

3 AP7 VPX_100M_REFCLK1N GTX/GTHREFCLK1_115 114, 115, 116

AP8 VPX_100M_REFCLK1P

0 Y7 VPX_100M_REFCLK2N GTX/GTHREFCLK0_117 116, 117, 118

Y8 VPX_100M_REFCLK2P

1 AT7 VPX_100M_REFCLK3N GTX/GTHREFCLK0_114 113, 114, 115

AT8 VPX_100M_REFCLK3P

Table 25: REF_CLK connections

3.10.2 On-board GTX/GTH Reference Clock

A 100 MHz clock from a low-jitter oscillator is distributed to the FPGA using another Si5335. This clock can be used as the reference clock for the GTP signalling to the VPX backplane. The clocks are connected in such a way that all GTPs can use this reference clock. The PCIe interface to the VPX backplane supports asynchronous clocking by using this on-board reference clock.

The default configuration generates a 100MHz clock on each output clock. It is possible to choose another clock frequency for each output individually after power up. This is done through the I2C interface.




Si5338 Output

FPGA Pin Net name GTX/GTH REFCLK

GTX/GTHs reached

0 T7 LOCAL_REFCLK0N

GTX/GTHREFCLK0_118 117, 118 T8 LOCAL_REFCLK0P

1 AM7 LOCAL_REFCLK1N

GTX/GTHREFCLK0_115 114, 115, 116 AM8 LOCAL_REFCLK1P

2 BB7 LOCAL_REFCLK2N

GTX/GTHREFCLK1_113 113, 114 BB8 LOCAL_REFCLK2P

Table 26: On-board GTX/GTH reference clock connections

3.10.3 FMC GTX/GTH Reference Clock

The FMC standard defines two high-precision reference clocks that are driven from the FMC to the carrier. The VP780 connects these clocks directly to GTX/GTH reference clock inputs. The following table shows which GTX/GTHs can use these reference clocks.

FPGA Pin Net name GTX/GTH REFCLK

GTX/GTHs reached

AY7 GBTCLK0_M2C_n GTX/GTHREFCLK0_113 113, 114

AY8 GBTCLK0_M2C_p

AD7 GBTCLK1_M2C_n GTX/GTHREFCLK0_116 115, 116,117

AD8 GBTCLK1_M2C_p

Table 27: FMC GTX/GTH reference clock connections

The AV57.1 FMC standard does not define a GTX/GTH reference clock, driven from the carrier to the FMC. The VP780 complies to AV57.1 and does not provide a reference clock to the FMC.

3.10.4 FMC Clock connections

The FMC clocks are connected to LVDS capable I/O on the FPGA. CLK0 and CLK1 are connected to global clock inputs. CLK2 and CLK3 are connected to regular I/O.


Pin Number Pin Name

AJ36 CLK0_M2C_n H5 CLK0_M2C_N

AK37 CLK0_M2C_p H4 CLK0_M2C_P

AN38 CLK1_M2C_n G3 CLK1_M2C_N

AN39 CLK1_M2C_p G2 CLK1_M2C_P

AM42 CLK2_BIDIR_n K5 CLK2_BIDIR_N

AM41 CLK2_BIDIR_p K4 CLK2_BIDIR_P

AL40 CLK3_BIDIR_n J3 CLK3_BIDIR_N

AM40 CLK3_BIDIR_p J2 CLK3_BIDIR_P

Table 28: FMC clock connections




3.10.5 Miscellaneous clock connections

A low jitter programmable clock device (CDCE925) able to generate frequencies from 62.5MHz to 255.5MHz in steps of 0.5MHz is available. This device has a pre-programmed default frequency of 125MHz. Two outputs are connected to the FPGA. Additionally, there is a fixed 200 MHz differential LVDS clock and a fixed 300 Mhz differential HSTL clock.

FPGA Pin Net Name I/O Standard FPGA Bank

DIR CDCE925, ECS-LVDS25

Device Pin Number Pin Name

F6 CLK_SYNTH_0 LVCMOS18 36 I CDCE925 13 Y1

AP21 CLK_SYNTH_1 LVCMOS18 14 I CDCE925 7 Y4

E2 CLK200_N LVDS18 36 I

ECS-LVDS25 5 C-Output

E3 CLK200_P LVDS18 ECS-LVDS25 4 Output

H27 CLK300_P DIFF_HSTL_I 33 I FXO-LC726R-300

5 C-Output

H28 CLK300_N DIFF_HSTL_I FXO-LC726R-300

4 Output

Table 29: Miscellaneous clock connections

3.11 Local I2C bus

There are three separate I2C buses on the VP780 that interface to the FPGA. Since the I2C signal standard uses 3.3V, the PCA9517 is used as a voltage translation between the 3.3V and the voltage rail going to the FPGA bank being used.

The FPGA and CPLD both interface to the VPX on an isolated bus. For the FPGA, this bus goes to Bank 14 which uses an I/O voltage rail of 1.8V. Using the global address pins, it is possible to develop an I2C slave in the FPGA and/or CPLD. Its I2C address is dependent upon the geographical location in the VPX chassis.

The FPGA to FMC I2C is also isolated. The purpose of the FMC I2C interface is to allow for communication to the FMC devices by the FPGA. The FMC global address signals (GA0 and GA1) are both pulled to ground.

Finally, the more extensive I2C bus is the local bus on the VP780. The clock frequencies to the two Si5338 devices and the CDCEL925 clock synthesizer can be adjusted with this bus. It also allows for the monitoring of the voltages and onboard temperature using the ADT7411 devices. A 3-pin header (J3) is available to facilitate debugging of the I2C bus.

Device Ref Des I2C Address




ADT7411ARQ

Device #1 U32 1001000

ADT7411ARQ

Device #2 U17 1001010

Si5338A

(REF_CLK) U16 1110000

Si5338A

(On-board clk) U42 1110001

CDCEL925 U35 1100100

Table 30 : I2C_Local device slave addresses

P0REF_CLKSN65MLVD2

100 MHz

oscillator

25MHz or 100MHz

16 MHz

crystal

Clock

Synthesizer

CDCEL925

3.3V

1.8V/1.5V

25MHz

100MHz

100MHz

25MHz

100MHz

100MHz

Si5338

Si5338

PCA9517I2C_SDA_VPXI2C_SCL_VPX

I2C_SDA_VPX_3V3

I2C_SCL_VPX_3V3

FPGA

MGTREFCLK0P/N_115

F6

AP21

A30/B30

AR33/AT33

MGTREFCLK1P/N_115

MGTREFCLK1P/N_116



MGTREFCLK1P/N_113


AL24/AR22

PCA9517I2C_SDA_LOCAL_3V3

I2C_SCL_LOCAL_3V3

ADT7411

ADT7411

PCA9517

I2C_SDA_LOCAL

I2C_SCL_LOCAL

I2C_SDA_FMC

I2C_SCL_FMC

I2C_SDA_FMC_3V3

I2C_SCL_FMC_3V3

VITA 57.1FMC

FMC MGT CLK

100MHz

Pin Header

J3

CPLD

Figure 8: VP780 I2C bus architecture.




FPGA Pin Net Name FPGA

Bank DIR

B30 I2C_SCL_LOCAL 33 IO

A30 I2C_SDA_LOCAL 33 IO

Table 31: Local I2C bus connections


3.11.1 On-board Voltage and Temperature Monitoring (ADT7411)

Refer to the datasheet of the ADT7411 for detailed information. The I2C slave address is set to b’1001000’ for the first device and to b’1001010’ for the second device.

Parameter Connection Formula

On-chip temperature ADT7411 Die Temperature

On-chip AIN0 (VDD) +3.3V

External temperature FPGA A temperature

External AIN3 12V AIN3*(1/5.7)

External AIN4 GTX/GTHAVCCAUX AIN4

External AIN5 BL1_VIO AIN5*(1/2)

External AIN6 BL0_VIO AIN6*(1/2)

External AIN7 GTX/GTHAVTT AIN7

External AIN8 GTX/GTHAVCC AIN8

Table 32: Monitoring device #1 connections




Parameter Connection Formula

On-chip temperature ADT7411 Die Temperature

On-chip AIN0 (VDD) +3.3V

External AIN1 BLAST0_vcore AIN1*(1/2)

External AIN2 BLAST1_vcore AIN2*(1/2)

External AIN3 5V AIN3*(47/147)

External AIN4 1V0 AIN4

External AIN5 VADJ AIN5*(1/2)



External AIN8 2V5 AIN8*(1/2)

Table 33: Monitoring device #2 connections

3.12 Serial FLASH

A 128 Mbits serial FLASH device (S25FL128P) is available to the FPGA. This FLASH allows non-volatile storage of vital data such as processor boot code.

The FLASH is operated using a standard SPI interface that can run up to 104 MHz, allowing for a page programming speed up to 208 KB/s. Reading data from the FLASH can be done at speeds up to 13 MB/s.

Serial flash sizes of 256 Mbits and 512 Mbits are available upon customer request.


DIR S25FL128P

Pin Number Pin Name

C30 SF_nWP 33 O

AR21 SF_SI 14 O 15 SI

AT21 SF_SO 14 I 8 SO/PO7

AT23 SF_nCS 14 O

AT24 SF_SCK 14 O 16 SCK

Table 34: SPI FLASH connections


3.13 FPGA Configuration

Figure 9 shows the configuration architecture on the VP780. The architecture allows FPGA configuration through the JTAG chain and parallel configuration from FLASH memory. The FPGA can be automatically loaded from FLASH after the VP780 powers up.




JTAG

Header

VPX P0 connector

FMC

PRSNT_M2C_L

CoolRunner-II

CPLD

XC2C256FT256

Virtex-7

FPGA

3V3 JTAG

1V8 JTAGOE

OE

1Gbit Flash

S29GL01GS

LED x4

LED x4

A[25..0]

Safety configuration

switch

PGND

ctrl

D[15..0]

Figure 9: Configuration architecture

3.13.1 JTAG chain

The JTAG chain on the VP780 is available for configuration and debugging purposes. The JTAG chain is accessible from the VPX backplane and an onboard header (See Figure 11 for a Xilinx Platform USB-II cable). The JTAG chain dynamically changes in the following situations:

1. Source selection

a. When no Xilinx Platform USB-II cable is connected to the JTAG header, the pseudo ground signal (PGND) is pulled high by a resistor on the VP780 and the JTAG signals from the VPX backplane are connected to the local JTAG chain.

b. When a Xilinx Platform USB-II cable is connected to the JTAG header, the pseudo ground signal (PGND) is pulled low by the cable and the JTAG signals from the VPX backplane are disconnected from the local JTAG chain.

2. FMC included

a. When an FMC card is not present, the PRSNT_M2C_L signal is pulled high by a resistor on the VP780 and the FMC’s TDO is connected to the FMC’s TDI. The JTAG chain is as follows: CPLD FPGA.

b. When an FMC card is present, the PRSNT_M2C_L signal is pulled low by the FMC card and the FMC’s TDO is disconnected from the FMC’s TDI. The JTAG chain is as follows: FMC CPLD FPGA.

3.13.2 FLASH storage

Firmware images are stored on board in a 1Gbit FLASH device and loaded to the FPGA after power-up. By default, there is space reserved for two FPGA images; a safety image and a




user image. In addition, the FLASH stores board-specific information like serial number, FPGA type, and BLAST information. The serial number is stored in the protected area of the flash which is the upper 128KB. Also, a user can program a 32-bits value into the flash. One 128KB sector is reserved for this.

Figure 10: FLASH arrangement

Note:

• In the Board info sector, the real Board Info starts at 0x3FF0002. The first two words are reserved data.

• The PHY always starts writing at the page boundary.

FPGA Pin Net Name FPGA Bank DIR CPLD Pin Number

BD24 FLASH_A00 14 O R1

BC24 FLASH_A01 14 O N4

BC23 FLASH_A02 14 O N2

BB22 FLASH_A03 14 O M3

BB23 FLASH_A04 14 O P1

BA23 FLASH_A05 14 O L3

BD22 FLASH_A06 14 O N1

BA24 FLASH_A07 14 O L4

AY24 FLASH_A08 14 O M1

AY23 FLASH_A09 14 O L5

AY22 FLASH_A10 14 O N3

AW24 FLASH_A11 14 O P2

AV24 FLASH_A12 14 O P4

AW22 FLASH_A13 14 O P5

AV22 FLASH_A14 14 O R2

AV23 FLASH_A15 14 O T1

AM33 FLASH_A16 15 O T2

AM32 FLASH_A17 15 O N5

AJ32 FLASH_A18 15 O R4

AK33 FLASH_A19 15 O M5

AK32 FLASH_A20 15 O R5




FPGA Pin Net Name FPGA Bank DIR CPLD Pin Number

AK34 FLASH_A21 15 O K4

AJ34 FLASH_A22 15 O L2

AM36 FLASH_A23 15 O K3

AL35 FLASH_A24 15 O L1

AN34 FLASH_A25 15 O K5

AH24 FLASH_D00 14 I/O K2

AH25 FLASH_D01 14 I/O J4

AH22 FLASH_D02 14 I/O K1

AH23 FLASH_D03 14 I/O J3

AK21 FLASH_D04 14 I/O J2

AL21 FLASH_D05 14 I/O J5

AJ24 FLASH_D06 14 I/O J1

AK24 FLASH_D07 14 I/O R6

AK22 FLASH_D08 14 I/O N6

AM23 FLASH_D09 14 I/O R3

AN23 FLASH_D10 14 I/O M6

AM21 FLASH_D11 14 I/O T3

AM22 FLASH_D12 14 I/O P6

AP24 FLASH_D13 14 I/O T4

AN22 FLASH_D14 14 I/O P7

AP22 FLASH_D15 14 I/O T5

AJ22 FLASH_nCE 14 O T16

AL33 FLASH_nOE 15 O N14

AL34 FLASH_nWE 15 O N7

n.c. flash_nreset n.c. n.c. M7

n.c. flash_nwp n.c. n.c. R7

n.c. flash_ry_nby n.c. n.c. N8

Table 35: Flash connections

3.13.3 Configuration Controller (CPLD)

As shown in Figure 9, a CoolRunner-II CPLD also connects to the flash device in parallel with the FPGA. The default CPLD image implements glue logic to read the FLASH memory at power up and configure the FPGA using slave select map. In addition, the CPLD can be used to provide access to the flash form the VPX I2C bus. This is not a standard feature, however, so please contact 4DSP for more details.

After power up, the configuration controller loads the user image into the FPGA. If FPGA configuration fails (for example when no user image exists or when the user image is faulty), the configuration controller loads the safety image. FPGA configuration is performed in Slave SelectMap mode.

In addition to the dedicated configuration signals, there are 3 general purpose I/O pins available between the CPLD and the FPGA. No special function is implemented for these signals yet.




FPGA Pin Net Name FPGA

Bank DIR

XC2C256-FT256

Pin Number Power up function Function 2

AK36 FP_CP_0 15 O C13 reserved reserved

AL36 FP_CP_1 15 O A15 reserved reserved

AM35 FP_CP_2 15 O C12 reserved reserved

AL23 FP_EMCCLK 14 O E3 80 MHz clock 80 MHz clock

V11 FP_CCLK 0 O

G4 Dedicated FPGA configuration pin

reserved

AC10 FP_INIT_B

0 O A5 Dedicated FPGA

configuration pin reserved

AD11 FP_DONE

0 I A8 Dedicated FPGA


AE10 FP_PROGRAM_B

0 C7 Dedicated FPGA


AG10 FP_M2

0 E11 Dedicated FPGA


AH11 FP_M0

0 B6 Dedicated FPGA


AJ10 FP_M1

0 E8 Dedicated FPGA


AK23 FP_PUDC_B 14 G3 Configuration pin reserved

AU21 FP_RDWR_B 14 D3 Configuration pin reserved

AU23 FP_CSI_B 14 F3 Configuration pin Reserved

AJ21 SYSRESET_I# 14 I E9 Keep asserted till FPGA is configured

Forward from P0 connector SYSRESET*

Table 36: CPLD connections

3.13.4 User image programming

Programming the user image in FLASH can be done from a system host through the PCI Express interface using 4DSP’s VP780 reference firmware design and 4FM GUI Control Application. The firmware reference design is stored in the safety image space. At the factory, the firmware reference design is also programmed in the user image space.

The user image may be overwritten with an image that does not implement the FLASH update features from 4DSP’s VP780 firmware reference design. In that case, there are three ways to recover:

1) Configure the FPGA with 4DSP’s VP780 firmware reference design through the JTAG chain. Then use the 4FM GUI Control Application to program a new user image in FLASH.

2) Power down the board, place the safety configuration jumper (section 3.13.5), and power-up. Then use the 4FM GUI Control Application to program a new user image in FLASH.

3) Additionally, it is possible to configure the flash directly from JTAG using the iMPACT tools from Xilinx. If the default CPLD code is used to load the FPGA configuration at power up, the user must make sure to follow the flash address map depicted in Figure 10. Please refer to the Xilinx documentation to learn more about programming the flash with iMPACT.




3.13.5 Safety Configuration Jumper

A press fit jumper footprint (SW1) is located next to the JTAG programming connector. If the jumper is closed, the FPGA safety image is loaded from FLASH after power-up.

J2

UART over USB

SW1

Safety jumper

J4

JTAG header

J3

Local I2C

Figure 11: Connector / Jumper locations

3.13.6 Master BPI configuration

The Master BPI with asynchronous read configuration mode is supported by the VP780. This offers several advantages over the slave select map.

• Advanced FPGA designs that can load several partial reconfiguration bitstreams from the external flash are possible.

• Customers can more easily implement their own configuration scheme and are not limited to a 4DSP proprietary interface.

In order to use the flash in this mode, a specific CPLD configuration has to be loaded first. Please contact 4DSP for this option.

4 Environment Specifications

4.1 Temperature

Operating temperature

• 0°C to +70°C (Commercial)

• -40°C to +85°C (Industrial) Storage temperature:

• -40°C to +120°C

4.2 Convection cooling

The air flow provided by the chassis fans dissipates the heat generated by the onboard components. A minimum airflow of 300 LFM is recommended.




4DSP’s warranty does not cover boards that have exceeded the maximum allowed temperature.

4.3 Conduction cooling

The VP780 is designed for conduction cooling according to ANSI/VITA 48.2. The module has primary side retainers. Slot pitch is 1.00 inch.

5 Safety This module presents no hazard to the user.

6 EMC This module is designed to operate within an enclosed host system built to provide EMC shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system. This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system.

7 Warranty

Hardware Software/Firmware

Basic Warranty

(included)

1 Year from Date of Shipment 90 Days from Date of Shipment

Extended Warranty

(optional)

2 Years from Date of Shipment 1 Year from Date of Shipment




Appendix A: FPGA Bank Mapping

DDR3BLAST1BLAST0

DDR3 (not on 485T)

DDR3

FMC (Bank 15 includes

Master BPI

CPLD/Master BPI

P2 LVDSMISC

DDR3 (not on 485T)

Group Bank VCCO VREF

FMC 15, 16, 17, 18 VADJ -

Dedicated DDR3 10, 11, 13, 33 1V5 0.75V

BLAST 1 37,38 BLAST0_VIO BLAST0_VIO/2

BLAST 1 34, 35 BLAST1_VIO BLAST1_VIO/2

CPLD/Master BPI 14 1V8 -

Misc 36 1V8 -

Table 37: FPGA Bank Mapping

Configuration BLAST 1 BLAST 2 BLAST0_VIO BLAST2_VIO

NN - - 1.5V 1.5V

GN DDR3 - 1.5V 1.5V

GG DDR3 DDR3 1.5V 1.5V

FN QDRII+ - 1.8V 1.8V

FF QDRII+ QDRII+ 1.8V 1.8V

EN FLASH - 1.8V 1.8V

EE FLASH FLASH 1.8V 1.8V

GF DDR3 QDRII+ 1.5V 1.8V

GE DDR3 FLASH 1.5V 1.8V

FE QDRII+ FLASH 1.8V 1.8V

HN 4GB DDR3 - 1.5V 1.5V

HH 4GB DDR3 4GB DDR3 1.5V 1.5V

FH QDRII+ 4GB DDR3 1.8V 1.5V

EF FLASH 4GB DDR3 1.8V 1.5V

Table 38: BLAST VIO Matrix




Appendix B: Errata

PCB revision 1.0

PG_C2M errata

According to the FMC specifications, the PG_C2M should only be asserted when all FMC powers are within their proper range. The VP780, however, will assert the PG_C2M a few milliseconds before it enables the VADJ.

This is not an issue for 4DSP FMC boards and many third party FMC boards. Please contact 4DSP if you want to use the VP780 in combination with an FMC that requires the PG_C2M to wait.

Flash programming errata

In order to configure the flash from the FPGA, VADJ should be set to 1V8. If another VADJ is chosen, flash programming is not guaranteed.

PCB revision 1.1

PG_C2M errata

Fixed.

Flash programming errata

In order to configure the flash from the FPGA, VADJ should be set to 1V8. If another VADJ is chosen, flash programming is not guaranteed. The VP780 does offer the ability to switch off VADJ to the FMC while still powering the FPGA IO banks. Contact 4DSP for more information.




Appendix C: BLAST pin outs

FPGA Pin Bank QDRII+ BLAST name FLASH BLAST

name

4GB ddr3 BLAST

name

K11 37 QDRA_SA<17> RnB_B_2 CKE1

B11 37 QDRA_Q<0> nc A14

A11 37 QDRA_D<0> nc

A9 37 QDRA_D<2> ALE_B_2 A6

A8 37 QDRA_D<9> nc ODT0

B10 37 QDRA_SA<18> nCE_B_4 BA0

A10 37 QDRA_SA<20> RnB_B_1 A12

B8 37 QDRA_Q<1> ALE_B_1 A9

B7 37 QDRA_SA<1> nc A3

C10 37 QDRA_Q<11> DQ_A_8 A8

C9 37 QDRA_R_n nc WE#

C8 37 QDRA_Q<2> DQ_A_10 A13

C7 37 QDRA_SA<4> nc CS1

E11 37 QDRA_SA<11> nc CAS#

D11 37 QDRA_D<1> nc ODT1

E9 37 QDRA_SA<16> RnB_B_4 RAS#

D10 37 QDRA_Q<10> nWP_B_2

E8 37 QDRA_D<12> DQS_A_2 A11

D14 38 Nc nc DQ5

G15 38 QDRA_SA<12> DQ_B_4 DQ10

C14 38 QDRA_SA<19> DQ_B_6 DQ1

C12 38 Nc nc DQ3

G12 38 QDRA_Q<24> nc DQ14

H15 38 QDRA_W_n nc DQ8

H14 38 QDRA_Q<27> CLK_B_2 DQ13

H13 38 QDRA_SA<0> nc DM1

H12 38 QDRA_Q<16> nc DQ12

J15 38 QDRA_SA<2> nc DQ9

B12 38 QDRA_SA<5> nCE_B_3 DQ0

E12 38 QDRA_D<26> nc DQ7

D12 38 QDRA_SA<9> DQ_B_7 DQ2

C13 38 QDRA_Q<25> nc DQ4

B13 38 QDRA_SA<14> nCE_B_2 DQ6

E14 38 QDRA_Q<26> nc DM0

F15 38 QDRA_D<18> nc DQ11

G13 38 QDRA_D<27> CLK_B_1 DQ15

A14 38 QDRA_SA<8> DQ_B_14 DQS0

F14 38 QDRA_Q<18> nc DQS1

D7 37 QDRA_SA<15> DQ_B_15 A10

D9 37 QDRA_Q<9> nWP_B_1 CS0





name

4GB ddr3 BLAST

name

L1 36 QDRA_SA<7> DQ_B_13

A13 38 QDRA_SA<13> DQ_B_12 DQS#0

F13 38 QDRA_D<16> nc DQS#1

D6 37 QDRA_SA<6> DQ_B_5 BA2

F10 37 QDRA_SA<10> RnB_B_3 CKE0

F9 37 Nc nCE_B_1 A15

J14 38 QDRA_Q<12> DQS_A_1

G11 37 QDRA_D<6> DQ_A_4

F11 37 QDRA_Q<6> DQ_A_6

G8 37 QDRA_CQ nc

G7 37 QDRA_D<15> DQ_A_12 A4

J9 37 QDRA_Q<17> DQ_A_7 A5

H9 37 QDRA_Q<5> nc A2

H10 37 QDRA_Q<14> nc

G10 37 QDRA_D<7> DQ_A_14

H8 37 QDRA_D<13> CLK_A_1 A7

H7 37 QDRA_D<8> nc A0

J11 37 Nc WnR_A_2 RESET#

J10 37 QDRA_Q<7> nCE_A_1 A1

K9 37 QDRA_D<5> CLK_A_2

K8 37 QDRA_D<14> CLE_A_2

K7 37 QDRA_Q<8> DQ_A_5 BA1

J7 37 QDRA_Q<13> CLE_A_1

F8 37 Nc DQ_A_13 CK

L11 37 QDRA_D<17> nc

L14 38 QDRA_D<20> ALE_A_2 DQ26

N13 38 QDRA_Q<29> DQ_B_10 DQ16

K14 38 QDRA_D<29> DQ_B_8 DQ30

K13 38 QDRA_D<28> ALE_A_1 DQ24

R13 38 QDRA_Q<28> RnB_A_1 DQ19

R12 38 QDRA_Q<30> DQ_B_2 DQ22

T14 38 QDRA_CQ_n nWP_A_2 DQ17

T13 38 QDRA_D<30> DQ_B_11 DQ20

U15 38 QDRA_K_n RnB_A_2 DM2

T15 38 QDRA_D<22> DQ_B_9 DQ23

K12 38 QDRA_D<21> CLE_B_1 DQ28

J12 38 QDRA_D<19> RnB_A_4 DQ25

L13 38 QDRA_D<24> nc DQ29

N15 38 QDRA_Q<19> nCE_A_3 DQ27

N14 38 QDRA_Q<22> CLE_B_2 DQ31

M13 38 QDRA_SA<3> nCE_A_2 DM3

P12 38 Nc nCE_A_4 DQ18





name

4GB ddr3 BLAST

name

P11 38 QDRA_Q<21> DQ_B_0 DQ21

M15 38 QDRA_Doff_n DQ_B_3 DQS3

R14 38 Nc RnB_A_3 DQS2

L10 37 QDRA_Q<4> DQ_A_9

E7 37 QDRA_K DQ_A_15 CK#

L3 36 QDRA_D<10> DQ_A_3

L15 38 QDRA_Q<20> DQ_B_1 DQS#3

P14 38 Nc nWP_A_1 DQS#2

L9 37 QDRA_D<25> nc

L8 37 QDRA_D<11> DQ_A_1

M11 37 QDRA_D<4> DQ_A_11

M12 38 QDRA_Q<15> WnR_A_1

M10 37 QDRA_D<23> DQS_B_1

P10 37 QDRA_Q<23> DQS_B_2

K2 36 QDRA_D<31> WnR_B_2

K1 36 QDRA_Q<31> WnR_B_1

N10 37 QDRA_D<3> DQ_A_0

M8 37 QDRA_Q<3> DQ_A_2

Table 39: BLAST 1 pin mapping

FPGA Pin

Bank

QDRII+ BLAST

Name

FLASH BLAST

name

4GB ddr3 BLAST

name

T20 35 QDRA_SA<17> RnB_B_2 CKE1

T19 35 QDRA_Q<0> nc A14

T18 35 QDRA_D<0> nc

R18 35 QDRA_D<2> ALE_B_2 A6

R19 35 QDRA_D<9> nc ODT0

P19 35 QDRA_SA<18> nCE_B_4 BA0

T21 35 QDRA_SA<20> RnB_B_1 A12

R21 35 QDRA_Q<1> ALE_B_1 A9

P20 35 QDRA_SA<1> nc A3

N19 35 QDRA_Q<11> DQ_A_8 A8

N22 35 QDRA_R_n nc WE#

M22 35 QDRA_Q<2> DQ_A_10 A13

N20 35 QDRA_SA<4> nc CS1

M20 35 QDRA_SA<11> nc CAS#

L20 35 QDRA_D<1> nc ODT1

L19 35 QDRA_SA<16> RnB_B_4 RAS#

U21 35 QDRA_Q<10> nWP_B_2

L21 35 QDRA_D<12> DQS_A_2 A11

P24 34 Nc nc DQ5

L24 34 QDRA_SA<12> DQ_B_4 DQ10




FPGA Pin

Bank

QDRII+ BLAST

Name

FLASH BLAST

name

4GB ddr3 BLAST

name

N24 34 QDRA_SA<19> DQ_B_6 DQ1

T23 34 Nc nc DQ3

M23 34 QDRA_Q<24> nc DQ14

L23 34 QDRA_W_n nc DQ8

K23 34 QDRA_Q<27> CLK_B_2 DQ13

L26 34 QDRA_SA<0> nc DM1

K26 34 QDRA_Q<16> nc DQ12

K24 34 QDRA_SA<2> nc DQ9

R23 34 QDRA_SA<5> nCE_B_3 DQ0

R22 34 QDRA_D<26> nc DQ7

P22 34 QDRA_SA<9> DQ_B_7 DQ2

U25 34 QDRA_Q<25> nc DQ4

T25 34 QDRA_SA<14> nCE_B_2 DQ6

U23 34 QDRA_Q<26> nc DM0

L25 34 QDRA_D<18> nc DQ11

N23 34 QDRA_D<27> CLK_B_1 DQ15

R24 34 QDRA_SA<8> DQ_B_14 DQS0

M25 34 QDRA_Q<18> nc DQS1

M21 35 QDRA_SA<15> DQ_B_15 A10

U20 35 QDRA_Q<9> nWP_B_1 CS0

L6 36 QDRA_SA<7> DQ_B_13

P25 34 QDRA_SA<13> DQ_B_12 DQS#0

M26 34 QDRA_D<16> nc DQS#1

K22 35 QDRA_SA<6> DQ_B_5 BA2

J22 35 QDRA_SA<10> RnB_B_3 CKE0

K21 35 Nc nCE_B_1 A15

J24 34 QDRA_Q<12> DQS_A_1

G20 35 QDRA_D<6> DQ_A_4

F20 35 QDRA_Q<6> DQ_A_6

J21 35 QDRA_CQ nc

U18 35 QDRA_D<15> DQ_A_12 A4

H22 35 QDRA_Q<17> DQ_A_7 A5

G22 35 QDRA_Q<5> nc A2

E22 35 QDRA_Q<14> nc

E21 35 QDRA_D<7> DQ_A_14

G21 35 QDRA_D<13> CLK_A_1 A7

F21 35 QDRA_D<8> nc A0

E23 35 Nc WnR_A_2 RESET#

D22 35 QDRA_Q<7> nCE_A_1 A1

D21 35 QDRA_D<5> CLK_A_2

D20 35 QDRA_D<14> CLE_A_2

C20 35 QDRA_Q<8> DQ_A_5 BA1




FPGA Pin

Bank

QDRII+ BLAST

Name

FLASH BLAST

name

4GB ddr3 BLAST

name

B20 35 QDRA_Q<13> CLE_A_1

J20 35 Nc DQ_A_13 CK

C23 35 QDRA_D<17> nc

F24 34 QDRA_D<20> ALE_A_2 DQ26

E26 34 QDRA_Q<29> DQ_B_10 DQ16

H23 34 QDRA_D<29> DQ_B_8 DQ30

H24 34 QDRA_D<28> ALE_A_1 DQ24

D25 34 QDRA_Q<28> RnB_A_1 DQ19

C25 34 QDRA_Q<30> DQ_B_2 DQ22

B26 34 QDRA_CQ_n nWP_A_2 DQ17

A26 34 QDRA_D<30> DQ_B_11 DQ20

C24 34 QDRA_K_n RnB_A_2 DM2

B25 34 QDRA_D<22> DQ_B_9 DQ23

J25 34 QDRA_D<21> CLE_B_1 DQ28

J26 34 QDRA_D<19> RnB_A_4 DQ25

F25 34 QDRA_D<24> nc DQ29

G23 34 QDRA_Q<19> nCE_A_3 DQ27

F23 34 QDRA_Q<22> CLE_B_2 DQ31

G26 34 QDRA_SA<3> nCE_A_2 DM3

E24 34 Nc nCE_A_4 DQ18

D24 34 QDRA_Q<21> DQ_B_0 DQ21

H25 34 QDRA_Doff_n DQ_B_3 DQS3

A24 34 Nc RnB_A_3 DQS2

A20 35 QDRA_Q<4> DQ_A_9

H20 35 QDRA_K DQ_A_15 CK#

L4 36 QDRA_D<10> DQ_A_3

G25 34 QDRA_Q<20> DQ_B_1 DQS#3

A25 34 Nc nWP_A_1 DQS#2

B21 35 QDRA_D<25> nc

B23 35 QDRA_D<11> DQ_A_1

P21 35 QDRA_D<4> DQ_A_11

F26 34 QDRA_Q<15> WnR_A_1

B22 35 QDRA_D<23> DQS_B_1

C22 35 QDRA_Q<23> DQS_B_2

K6 36 QDRA_D<31> WnR_B_2

L5 36 QDRA_Q<31> WnR_B_1

A23 35 QDRA_D<3> DQ_A_0

A21 35 QDRA_Q<3> DQ_A_2

Table 40: BLAST 2 pin mapping




Appendix D: Parallel flash programming with Vivado The VP780 supports programming of the FPGA configuration flash though the board support package and PCIe. Additionally it supports flash programming using the Vivado tool. This appendix provides a step-by-step procedure to program the flash with Vivado.

It is highly recommended to program the flash using the Board Support package through PCIe to program a .hex file in the User Image flash memory location. However, if this is not possible, follow the steps below:

1. Open Vivado and open the Hardware Manager 2. Run Auto-Connect to connect to targets on the VP780 3. Now add the .. as memory configuration device:

4. When prompted, click OK to configure the memory configuration device 5. You need a .mcs file to program the flash. Use the following tcl command to generate

the .mcs file: “write_cfgmem -format mcs -interface BPIx16 -size 128 -loadbit "up 0x02000000 <user image>.bit" -file <user_image>.mcs -force” The address of 0x02000000 selects the upper half of the flash where the user image should be located Make sure the settings are as below and click OK to start programming:

Note that programming the flash with Vivado can erase important information from the flash which voids warranty. Refer to the memory allocation description in section 3.13.2.




6. Programming takes a while and ends with:
