IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 8, AUGUST 1996 1291

Unified Physical I-V Model Including Self-Heating Effect for Fully Depleted SOIMOSFET’ s

Yuhua Cheng, Member, IEEE, and Tor A. Fjeldly, Senior Member, IEEE

Abstruct- A physically based analytical I-V model that includes self-heating effect (SHE) is presented for fully depleted SOVMOSFET’s. The incorporation of SHE is done self-consistently in a fully closed form, making the model very suitable for use in circuit simulators. The model also accounts for the drain induced conductivity enhancement (DICE) and drain induced barrier lowering (DIBL), channel length modulation (CLM), as well as parasitic series resistances (PSR). Another advantage is the unified form of the model that allows us to describe the subthreshold, the near-threshold and the above- threshold regimes of operation in one continuous expression. A continuous transition of current and conductance from the linear to the saturation regimes is also assured. The model shows good agreement with measured data for a wide range of channel lengths (down to 0.28 pm) and film thicknesses (94 nm-162 nm).

I. INTRODUCTION HIN-film SO1 (silicon-on-insulator) MOSFET’s are ex- T pected to become competitive with bulk MOSFET’s

in sub-micrometer CMOS applications owing to attractive performance advantages in terms of radiation hardness, small parasitic capacitances, high speed, and immunity to latch- up [l]. These advantages arise from the use of a buried silicon dioxide layer in the SO1 structure. But the low thermal conductivity of this buried oxide inhibits an efficient cooling of the active devices, which may cause a significant self- heating effect (SHE) [2]. SHE manifests itself as a reduced drain current and even a negative differential conductance at high power inputs [ 3 ] . Hence, for reliable analysis and design of SO1 circuits, accurate, physically based I-V models that include SHE are needed for use in circuit simulators. Up to now, the influence of SHE on the electrical characteristics of SO1 devices has been simulated with two-dimensional (2-D) device simulators incorporating heat flow [4], or by combining a temperature ( T ) rise model with I-V expres- sions through an iteration procedure [5]. However, in circuit computer aided design (CAD), the use of efficient, analytical models with fully closed expressions are essential in order to reduce the computation time. A step in this direction was recently suggested by Su et al. [6]. But they used a

Manuscript received September 18, 1995; revised March 20, 1996. The review of this paper was arranged by Editor G. W. Neudeck. This work was supported by the Research Council of Norway.

Y. Cheng is with the Department of Physical Electronics, Norwegian Institute of Technology, Trondheim, N-7034 Norway, and the Institute of Microelectronics, Peking University, Beijing 100871, China.

T. A. Fjeldly is with the Department of Physical Electronics, Norwegian Institute of Technology, Trondheim, N-7034 Norway,

Publisher Item Identifier S 0018-9383(96)05547-5.

description based on an I-V model for bulk MOSFET’s, which is different from that of SO1 devices in several aspects. Moreover, the influence of SHE on the temperature-dependent parameters cannot be determined self-consistently through their I-V model, so an extra optimization step is needed (in addition to the normal parameter extraction routine) in ordler to obtain suitable parameters to fit the measured data. Hence, this model also tends to be time consuming and inconvenient for use in SOIMOSFET circuit simulation.

Previously, we presented a unified SOIMOSFET model that accounts for drain induced conductivity enhancement (DICE), drain induced barrier lowering (DIBL), channel length modulation (CLM), and parasitic series resistances (PSR) [‘7], [SI. However, the present paper is a first full account of our unified SOIMOSFET I-V model, including the fully cloazd form expressions describing SHE. This analytical and self- consistent model is in good agreement with measured data for devices with a wide range of channel lengths (down to 0.28 pm and film thicknesses in all regions of device operation, and is very well suited for implementation in circuit simulators such as SPICE.

11. TEMPERATURE RISE MODEL AND TEMPERATURE DEPENDENT PARAMETERS

A. Temperature Rise Model

ture can be described by the following expression [3]: The temperature increase induced by SHE in an SO1 struc-

where T, is the new operating temperature, To is the ambient (room) temperature, I d is the drain current, v& is the drain- source voltage, and &, = nt,b/(XWL) is the thermal resistance. Here, tob is the thickness of the buried oxide layer, W is the channel width, L is the channel length and X is the thermal conductivity of the buried oxide. The parameter ~f. is a parameter to account for effects ignored by this simple modd, obtainable from thermal resistance measurements. This param- eter can be expected to be significantly less than unity because of heat flow through the gate and the interconnect [2], and the two-dimensionality of the heat flow in the semiconductor.

The use of (1) implies that only stationary conditioiis are considered in the present analysis. For general transient analyzes, a self-consistent thermal and electrical iteration procedure seems more suitable. However, for the important

0018-9383/96$05.00 0 1996 IEEE

1292 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 8, AUGUST 1996

CMOS class of logic, the switching transients between noncon- ducting states are normally very short compared to the thermal time constants, in which case the results from a stationary analysis are applicable [6].

B. Temperature Dependent Parameters

To determine the influence of the SHE on the characteristics of SO1 devices, the temperature dependencies of physical pa- rameters are needed. The important parameters in this respect are the threshold voltage VT, the mobility pn , and the impact ionization parameter Pi (see below) [ 5 ] , [12]. The dependence on temperature of these parameters are well-known from literature [9]-[ 131. Here, simplified, empirical versions of these relationships are needed in order to establish the analytical I-V model in a fully closed form. We have shown elsewhere [14] that a linearization of the above parameters can be used with reasonable accuracy of up to T, - To zz 100 OC.

The variation of the threshold voltage with temperature can be described reasonably well by the following empirical linear relationship [9]:

VT = VTo - r(Tc - To) (2)

where VT and V,, are the threshold voltage at the temperature T, and To, respectively, and y is the temperature coefficient of the threshold voltage.

The temperature dependence of the channel electron mobil- ity can be modeled as [l 11

where E,ff (the effective vertical electric field), b,y,, and n (in the range 1.5-1.7 [5], [lo]) are fitting parameters that can be extracted from room temperature measurements. The linearized form to the right in (4) is valid when the temperature rise is much less than To. In this approximation, we have Tp M To/n, and the temperature variation of E,E was ignored. However the effect of E e ~ is contained in the room temperature mobility pne which can be expressed in terms of the sheet charge density n, of channel electrons as [B]

Pno Pne = ~ 1 + dun, (4)

Here, ,uno and 0 are constants determined from experiments and a = q/Cof , where Cof = E,,/(to,+Ad,) is the front gate capacitance per unit area, E,, and to f are the dielectric constant and the thickness of the front gate insulator, respectively, and Ad, is a correction to the insulator layer thickness [ 5 ] .

It is well known that the impact ionization process can be described in terms of the impact ionization factor M given in the following form for a device in saturation [9]:

where L is the gate length, L, is point in the channel corresponding to the onset of velocity saturation, ai and Pi are ionization parameters, and E, is the lateral electric field in the channel.

An analytical expression for the impact ionization factor M can be obtained using a three-point Simpson integration method [SI. Several authors have shown that the temperature dependence of M is dominated by that of ,LIZ. Hence we consider a, to be independent of temperature and use the following linearized form for ,LIZ [12]:

P z = Pm + A,(T, - T o ) (6)

where the room temperature value Pzo and the constant hp are determined from experiments.

We also considered the temperature dependence of the saturation velocity U, [lo], but found this to have negligible impact on the overall simulation results.

In the above expressions, ?,Tp and hp are the relevant temperature parameters for threshold voltage, mobility, and impact ionization coefficient, respectively, all extractable from experiments.

111. I-V MODEL

A. Intrinsic I-V Model

This discussion is based on the unified I-V model for SOI/MOSFET's developed previously [7], [SI, in which the unified charge control model (UCCM) [15] and a quasi-two- dimensional analysis are used together with the consideration of velocity saturation, DIBL and DICE, CLM, and gate bias dependent mobility. In particular, we emphasize the use of proper boundary conditions for the saturated part of the channel, where a self-consistent channel potential V p is used at the onset point of velocity saturation in the channel instead of the saturation voltage Vs,.

An implicit, self-consistent, expression for the I-V char- acteristics (including SHE) is obtained by substituting tem- perature dependencies of the previous section into the basic I-V model [SI, and eliminating the temperature T, everywhere using the temperature rise model of (1). Rearranging this expression and ignoring the influence of power terms of high order than (corresponding to the assumption that RthIdVds << To), we obtain in a straightforward manner the following intrinsic I-V characteristics in the below-saturation regime:

(7) IDL~

I D L 1 1 + XRthIDLoVDS

where

Here IDL~ is the current and nso is the electron sheet charge density at the source side of the channel, both at the ambient temperature (T, = To) [8]. Furthermore, TV = Y / V T ~ , VDS is the intrinsic drain-source voltage (intrinsic voltages indicated by capitalized subscripts) and Vb, = (an,, + 277k~T, /q) /a , where a (body factor), (ideality factor) and a (see previous section) are parameters of the unified charge control model [15], q is the elementary charge, and k g is the Boltzmann constant.

CHENG AND FJELDLY UNIFIED PHYSICAL I-V MODEL 1293

The expression for the intrinsic saturation voltage (including SHE) becomes

where

(9)

- ans~VTo/(a~v:~TV) + 2 q k B / ( q a ) 2vbo/vSATo - 1

(10)

Here, VSAT~ and 1 s ~ ~ ~ are the saturation voltage and current at the room temperature.

Similarly, we can derive the I-V characteristics including SHE in the saturation regime by incorporating the temperature rise model and the temperature dependencies of the physical parameters into the basic model for saturation regime [8]

(1 1) ~ ( V D S - VSAT)FC

FA f z / F j + ~ F B ( ~ D s - VSAT) IDS = ISAT +

where

F c = l -

In addition, we have go = qWnsous/Vbo, cb = CobcSi/ ( c o b csi), and

In the above expressions, ESAT~ = 2v,/pno is the room temperature critical field for the onset of saturation (VDS = VSAT), Cob and Csi are the back (buried) and silicon film capacitances per unit area, t , is an average depth over which the mobile electrons are spread in the saturation region, tsi is the thickness of the silicon film, N c h is the doping density in the silicon film, and E S ~ is the dielectric permittivity of silicon.

In saturation, the potential Vp at the point of velocity saturation in the channel and the length L d = L - of the saturated part of the channel, can be expressed as [8]

V P VSAT - ( IDS - ISAT)/go (16)

(17) Ld = qwhonsovbo

2

The added drain current caused by the floating body effect can be expressed as [121, [13]: IFFB = ( M - ~ ) I D s / [ ~ -

~ T Y T - ( M - ~ ) K c Y T ~ T ] . Here, the impact ionization factor M includes the influence of the thermal effect described by ( (5) and (6), and QT and 7~ are the emitter efficiency and the base transport factor, respectively, of an effective parasitic bipolar transistor between drain and source through the body.

B. Extrinsic I-V Model The basic extrinsic I-V model [8] can also be extended to

include SHE. A tedious but straightforward calculation leads to the following expression for the extrinsic below-saturation current (again assuming that the the temperature rise is riot too large):

(18) 2gcheo vds

61 + z/s; - 4RdsgchcoVds& Id1

where Rds is the sum of the source and drain parasitic resistances, V& is the extrinsic drain-source voltage, and

Here, pEo and n:, are the mobility and the carrier sheet density near source adjusted for the effects of the parasitic resistances V I .

The extrinsic saturation voltage can be expressed as

VSAT = ~ V S A T ( ~ + Rcisgcileo)

X e + z/xz - 4(1 f Rdz9~heo)XRthgcheoVS2A~ (22)

where x e has the same form as x in (IQ), except that all intrinsic quantities have been replaced by their extrinsic counterparts.

By a similar procedure, the extrinsic I-V characteristics in saturation can be shown to have the same form as (1 I ) , except that all intrinsic quantities have to be replaced by their extrinsic counterparts.

Iv . MODEL VERIFICATION AND DISCUSSION

In this section, we compare the present model with exper- imental dc characteristics obtained from three fully depleted SOI/NMOS devices representing a wide range in device pa- rameters.

Device A: W / L = 10/1, tof = 27 nm, ts; = 150 nm, to,, = 440 nm, Rds = 40 R, N c h = 3.2 x

Device B: W / L = 7.65/0.61, t,f = 7 nm, ts; = 162 nm,

Device C: W / L = 7.83/0.28, to f = 10 nm, ts; = 94 nrn, tob = 347 nm, R d s = 140 R, Nch = 1 x 1016 cm-3 [17]. Other device parameters, including the thermal parameters used in the model calculations, are given in Tables I and 11.

Measured and modeled I-V characteristics of SOIMOSFET's are shown in Figs. 14 . With SHE included

cmP3 [16].

tob = 380 nm, Rds = 60 0, Nch = 1 X C111-3 [17].

1294

-" vu Vot n:

I

V 0.2 0.2 0.2 V 1.2 1.2 1.2

llcm 2.28~106 1.75~106 1.75~106

EEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 8, AUGUST 1996

-1 1 I I

pi0 1 V/cm I 1.61~106 1 2.71~106 I 2.71~106 3 .098 0.0 9

TABLE I DEVICE PARAMETERS USED IN THE MODEL CALCULATIONS (SEE [SI)

U I I m I 0.025 0.05 0.05

n- 0.9 I 0.9 I 0.9 ~

ta nm [ 1 - 1 , I I I

0.89 0.91 0.93 PT I ~ K 0. 5 0.85

Parameters Tlr Units K

Values 170

,j h K K K WIcmK

I O 0 0 4760 o.014 0.04-0.17

4 I I

Tsi =I 50nm

3 U E - 2.5

g 2 a .c 1.5

1

0.5

0

g

0 1 2 3 4 5 6 Drain Voltage ( V)

Fig. 1 , Measured (open circles) and modeled (solid and dashed lines: with and without SHE) I-V curves of n-SOUMOSFET. (Data from J. R. Davis et al. [16]). Major model parameters are: R d s = 40 R, p n o = 706 cm2/Vs. 6' = 0.09. vs = 8.8 X 10' c d s , 1) = 1.46, Nch = 3 .2 X cmP3, threshold voltage parameters: uo = 0.015, V, = 0.2 V, V,t = 1.2 V [15].

in the model, an excellent agreement was found for all devices in all regions of device operation. On the other hand, the results predicted by the model without SHE (letting Rth = 0 in the present model) show significant deviation from the measured data at large current and bias levels, where SHE is important [17]. In Fig. 1, we emphasize the additional influence of the floating body effect in saturation. We notice that the associated breakdown region of the characteristics at high drain-source voltages i s well described by the present model. Likewise, in Figs. 2 and 3, we demonstrate a good correspondence between measured and modeled results in cases where serious SHE leads to a negative differential resistance in saturation [3] , [5]. Fig. 4, which emphasizes the subthreshold regime of operation, shows an excellent agreement between measured and modeled transfer

0 0.5 1 1.5 2 2.5 3

Drain Voltage (V)

Fig. 2. Measured (open circles) and modeled (solid and dashed lines: with and without SHE) I-V curves of n-SOWOSFET. (Data from T. C. Hsiao et al. [17]). Major model parameters are: p n o = 462 cm2/Vs, 0 = 0.19. v, = 9.6 x l o6 c d s , 1) = 1.016, Nch = 1 x ~ m - ~ , threshold voltage parameters: uo = 0.03, V, = 0.2 V, V,t = 1.2 V [15].

0 05 1 1.5 2 2.5 3 Drain Voltage ( V)

Fig. 3. Measured (open circles) and modeled (solid and dashed lines: with and without SHE) I-V curves of n-SOIIMOSFET. (Data from T. C. Hsiao et al. [17]). Major model parameters are: p n o = 612 cm2/Vs. 0 = 0.14. 1) = 1.026, ws = 8.3 x 106 c d s , Nch = 1 X 1016 ~ m - ~ , threshold voltage parameters: uo = 0.06, Vm = 0.2 V, V,t = V [15].

characteristics for a device with a 1.5-pm channel length at two different values of substrate bias.

Using the parameter values of Table 111, we find that the maximum temperature rise in the devices considered here is about 100 "C, which is within the range of validity of the present model.

With the present model, the influence of SHE on physical parameters such as V&T, Vp, the CLM factor Ld, and the ion impact factor M , were also analyzed, using the parameters given in Table 111. The results are shown in Figs. 5-8. As indicated in Fig. 5, V&T is increased as a result of SHE, and more so with reduced channel length. This effect can be explained by an expected increase in the critical electrical field E ~ A T at elevated temperatures (owing to a reduction in mobility). SHE also affects the dependence of the channel potential Vp on VDS, as indicated in Fig. 6. When SHE is

~

CHENG AND FJELDLY UNIFIED PHYSICAL I-V MODEL

0.8

0.6 - - h

L

0.4 ~~

>"

0.2

I295

' Parameters w L hb tsi

Units pm hm $A nm nm Values 8 0.3 8 350 90

Parameters Nch V. I,"^ A K

WL-lo0/1.5

m = 150nm

Units Values

Parameters

10 -14 1 1 1 -1 -0.5 0 0.5 1 1.5 2 2.5 3

Front Gate Voltage ( V)

Fig. 4. Measured (open circles) and modeled transfer characteristics of n-SOVMOSFET. (Data from J. R. Davis et al. [16]). Major model parameters are: Eds = 20 a, p n o = 706 cm2/Vs, = 0.09, vs = 8.8 x l o6 c d s , 7 = 1.46, Nch = 3.2 x 1016 cmP3, threshold voltage parameters: 0, = 0.015. Vu = 0.2 V, Vut = 1.2 V [15].

?.I" I - cm-3 c d s cm2Ns 1 1N 1x1016 6.3~106 612 I 0 .14 0.102 T,, v A n I 1

0.2 I

1 - 1 Units I K I I; i K i WlcmK '" i

Values I 170 I loo0 I 1650 I 0.014 I I

0.15 - 5.

2 0.1 :: 9

0 c

c

> 0.05

/

0 0.5 1 1.5 2 2.5 3 3.5 Front Gate Voltage (V)

Fig. 5. Modeled results of SHE induced increase in saturation voltage (&AT - V ~ A T ~ ) for devices with different channel lengths. (Model pa- rameters are given in Table 111.)

negligible, Vp decreases with increasing V& [7] , [8], but with significant SHE, this effect is reduced (owing to the increase in ESAT). The observed changes in ESAT and Vp indicate that adjustments of the channel electric field Ey and of the channel potential V, take place in the presence of self heating. Hence, the CLM factor L d will also be strongly influenced by SHE, as

vgs= 0.5V

0 0.5 1 1.5 2 2.5 3 Vds (V)

Fig. 6. Modeled channel potential V p at the saturation point versus 15s at different gate biases (solid and dashed lines: with and without SHE). Saturation voltages VSAT~ arc shown by symbols. (Model parameters are given in Table 111.)

0.16 1 1

0.12 0.14 I

E -2 0.08 U

-I 0.06 1 0.02 0.04 1

O J 0 0.5 1 1.5 2 2.5 3

Drain Voltage (V)

Fig. 7. Modeled curves of channel length modulation factor Ld versus VDS at different gate biases (solid and dashed lines: with and without SHE). (Made1 parameters are given in Table 111.)

1.05

1.04

- b 1.03 0 2 1.02

1.01

1

LL

va=0.5V , 7 .' I

0 1 2 3 4

Drain Vdtage (V)

Fig. 8. Modeled curves of ion impact factor M versus VDS at different gate biases (solid and dashed lines: with and without SHE). (Model Parameters are given in Table 111.)

shown in Fig. 7. The observed reduction in L d can be directly explained by the increase in E s a ~ . Finally, we show in Fig. 8

1296 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 43, NO. 8, AUGUST 1996

that SHE also causes a reduction in the ion impact factor M for a given V&,, as can also be seen in Fig. 1. This effect is caused by a redistribution of the lateral channel electric field in the channel, with a reduction in the maximum field near drain, as the temperature rises.

V. SUMMARY

We have presented a physically based, unified I-V model for fully depleted SOIMOSFET’s with self-heating effect (SHE). Besides SHE, the model incorporates several important physical mechanisms related to short channel and thin-film phenomena, to parasitic resistances, and to drain breakdown, ensuring a precise description of device operation in all regimes of operation. Comparisons between the modeled and measured data have demonstrated that the present model accurately reproduces measured I-V characteristics of devices with a wide range of geometric and process parameters. The model is being implemented in the circuit simulator AIM- Spice [15] for use in SO1 circuit and device CAD.

REFERENCES

J. P. Colinge, Silicon-on-Insulator Technology: Materials to VLSI. Boston, MA: Kluwer, 1991. K. E. Goodson and M. I. Flik, “Effects of microscale thermal conduction on packing limit of silicon-on-insulator electronic devices,” IEEE Trans. Comp., Hybrids, Munuf Technol., vol. 15, pp. 715-722, 1992. L. J. McDaid, S. Hall, P. H. Mellor, and W. Eccleston, “Physical origin of negative differential resistance in SO1 transistors,” Electron. Lett., vol. 25, pp. 827-828, 1989. M. Koyanagi, H. Kiba, H. Kurino, T. Hashimoto, H. Mori, and K. Yamaguchi, “Coupled Monte Carlo energy transport simulation with quasi-three-dimensional temperature analysis for SO1 MOSFET,” IEEE Trans. Electron Devices, vol. 39, p. 2640, 1992. N. Yasuda, S. Ueno, K. Taniguchi, C. Hamaguchi, Y. Yamaguchi, and T. Nishimura, “Analytical device model of SO1 MOSFET’s including self-heating,’’ Jpn. J. Appl. Phys., vol. 30, pp. 3677-3684, 1991. L. T. Su, D. A. Antoniadis, N. D. Arora, B. S. Doyel, and D. B. Krakauer, “SPICE model and parameters for fully-depleted SO1 MOSFET’s including self-heating,’’ IEEE Electron Device Lett.. vol. 15, pp. 374-376, 1994. Y. H. Cheng and T. A. Fjeldly, “Unified submicrometer SOIMOSFET model for circuit simulation,” in Proc. 1994 IEEE SO1 Int. Con$, Nantucket Island, MA, Oct. 1994, pp. 11-12. ~, “Unified physical I-V model of fully depleted SOUMOSFET’s for analog/digital circuit simulation,” Solid State Electron., vol. 39, no. 5 , pp. 721-730, 1996.. S. M. Sze, Physics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981. D. S. Jeon and D. E. Burk, “A temperature-dependent SO1 MOSFET model for high-temperature application (27 O- 300 “C),” IEEE Trans. Electron Devices, vol. 36, pp. 2101-2111, 1991. -, “MOSFET electron inversion layer mobilities-A physically based semi-empirical model for a wide temperature range,” IEEE Trans. Electron Devices, vol. 36, pp. 1456-1463, 1989. R. Howes, W. Redman-White, K. G. Nichols, P. J. Mole, M. J. Robinson, and S. Bird, “An SOS MOSFET model based on calculation of the surface potential,” IEEE Trans. Computer-Aided Design, vol. 13, pp. 494-505, 1994.

T. Rang, “The impact ionization coefficients of carriers and their temperature dependence in silicon,” Radioelectron.Commun. Syst., vol. 28, pp. 91-93, 1985. Y. H. Cheng and T. A. Fjeldly, in Proc. 1995 Int. Semiconductor Device Research Symp., Charlottesville, VA, Dec. 1995, pp. 793-796. K. Lee, M. Shur, T. A. Fjeldly, and T. Ytterdal, Semiconductor Device Modeling for VLSI. J. R. Davis, G. A. Armstrong, N. J. Thomas, and A. Doyel, “Thin- film SO1 MOSFET transistors with p+-polysilicon gates,” IEEE Trans. Electron Devices, vol. 38, pp. 32-38, 1991. T. C. Hsiao, N. A. Kistler, and J. C. S. Woo, “Modeling the I-V characteristics of fully depleted submicrometer SO1 MOSFET’s,” IEEE Electron Device Lett., vol. 15, pp. 4 5 4 7 , 1994.

Englewood Cliffs, N J Prentice-Hall, 1993.

Yuhua Cheng (M’96) received the B.S. degree in electrical engineering from Shandong Polytechnic University, Jinan, China, in 1982, the M.S. degree in electrical engineering from Tianjin University, Tian- jin, China, in 1985, and the Ph.D. degree in electri- cal engineering from Tsinghua University, Bejing, China, in 1989

In March 1990, he joined in the Institute of Microelectronics, Peking University, China, as a Postdoctoral Research Fellow. From August 1992 to March 1996, he was an Associate Professor in

the Department of Computer Science and Technology, Peking University. From January 1994 to January 1995, he worked as a Visiting Professor at the University of Trondheim, Norway, and as a Research Fellow of the Norwegian Research Council. Since February 1995, he has been a Research Scientist at the Department of Electrical Engineering and Computer Sciences, University of California, Berkeley. His research areas include bulk and silicon-on-insulator (SOI) CMOS device physics, modeling, reliability, and technologies. Curently, he is working on the BSIM3 model project, and offering technical support to the BSIM3 users from both industry and academics. He has authored and coauthored over 35 research papers.

Tor A. Fjeldly (M’85-SM’SS) received the M.Sc. degree in physics from the Norwegian Institute of Technology, University o f Trondheim, in 1967, and the Ph D degree in physics from Brown University, Providence, RI, in 1972

From 1972 to 1974, he was with the Max-Planck- Institute for Solid State Physics, Stuttgart, Germany From 1974 to 1983, he worked as a Senior Scien- tist at SINTEF-DELAB, a research organization in Trondheim, Norway. Since 1983, he has been on the faculty of the Norwegian Institute of Technology,

University of Trondheim, where he is a Professor of Electrical Engineering. From 1989 to 1992, he was Head of the Department of Physical, and he also served as an Associate Dean of the Faculty of Electrical Engineering and Computer Science In 1988 and 1989, he had summer research engagements with the University of Minnesota, Minneapolis, and since 1990, he has held the position of Visiting Professor at the Department of Electrical Engineering, University of Virginia, Charlottesville His research has included fundamental studies of semiconductors and other solids, development of solid- state chemical sensors, electron transport in semiconductora, and modeling and simulation of semiconductor devices He has written more than 100 scientific papers and is a coauthor of the book Semiconductor Device Modeling for VLSI (Englewood Cliffs, NJ Prentice-Hall, 1993).

Dr Fjeldly is a member of the Norwegian Academy of Technical Sciences, the American Physical Society, the European Physical Society, and the Electrochemical Society