understanding adc specifications september 2005. 2 definition of terms 000 analogue input voltage...
TRANSCRIPT
Understanding ADC Specifications
September 2005
2
Definition of Terms
000
Analogue Input Voltage
001
010
011
100
101
110
111
DigitalOutputCode
FS1/2 FS 3/4 FS1/4 FS0
codewidth
Transition point is where the output code changes from one code to an adjacent code with respect to an analogue input voltage
VREF = Full-Scale (FS) + 1LSB Voltage
Ideal code Width = 1LSB
1 LSB = VREF / 2n
ie: VREF = 4.096V,
for a 12-bit ADC
LSB size = 4.096/212 = 1mV
TransitionPoints
Ideal transfer functionfor a 3-bit A/D
3
ADC Specifications: Resolution
For an ADC, Resolution is simply a measure of how many segments the input analogue range can be divided into.
Resolution IS NOT THE SAME AS ACCURACY! You could have a 16-bit ADC that is less accurate than an 8-bit ADC Why? Monotonicity, A/D converter noise, etc
4
ADC Specs: Quantisation Error
000
Analogue Input Voltage
001
010
011
100
101
110
111
DigitalOutputCode
FS1/2 FS 3/4 FS1/4 FS0
The difference between the actual input voltage and the digital code representation of the input voltage.
Even in the case of a perfect ADC, quantisation error will be ± 1/2 LSB.
Increasing bits reduces the error
5
Sampling and Quantisation
4-bit (16 level) ADC sampling a sinewave input, time domain
Input Sinewave
ADC Output
Quantisation Error
TIME
OUTPUTDIGITALWORD
0000000100100011010001010110011110001001101010111100110111101111
2 3 4 5 6 7 8 9 10 11 12 13
6
ADC Specs: Offset Error
000
Analog Input Voltage
001
010
011
100
101
110
111
DigitalOutputCode
FS1/2 FS 3/4 FS1/4 FS0
Offset Error
Offset Error is the difference between the first transition point and the ideal first transition point. (Measured in LSBs)
Digital Code Out = A + Vin where A is the analogue offset error
Offset Errors can be corrected in Firmware Correction for offset error can be made by adding (or subtracting) the correction from each code.
Ideal transferfunction
Actualtransferfunction
7
ADC Specs: Gain Error (full scale error)
000
Actual full scale range
001
010
011
100
101
110
111
DigitalOutputCode
Full scale range is the difference between the first and last code transition points.
The ideal full scale range minusthe actual full scale range equalsGain Error. (Measured in LSBs)
Digital Code = B VIN
where B is the gain error
Gain Errors can be corrected in firmware Corrections for gain error can be made by multiplying each code by the ratio of ideal to actual full scale range.
Ideal transferfunction
Actualtransferfunction
Ideal full scale range
8
ADC Specs: A/D Converter with Offset and Gain Error
000
001
010
011
100
101
110
111
DigitalOutputCode
With most ADCs, you will have to deal with both Gain and offset Errors!
Digital Code = A + B VIN
where A is the Offset Error and B is the Gain Error
Ideal transferfunction
Actualtransferfunction
FS1/2 FS 3/4 FS1/4 FS0
9
ADC Specs: Differential Nonlinearity (DNL)
000
001
010
011
100
101
110
111
DigitalOutputCode
DNL is a measure of variations in code widths from the ideal code width.
A DNL of ±½ LSB implies that: ½ LSB < all code widths < 1½LSB
A missing code means DNL = -1 LSBIdeal transferfunction
Actualtransferfunction
Narrow code, <1 LSB
Wide code, >1 LSB
10
DNL Plot for 12bit ADC
DNL vs Code, 100kHz, VDD = 5V, VREF = 5V
-1.00
-0.80
-0.60
-0.40
-0.20
0.00
0.20
0.40
0.60
0.80
1.00
Code
DN
L (
LS
B)
0 4095
This DNL plot shows the variation of code widths for each code for a 12 bit ADC
11
ADC Specs: Missing Codes
000
001
010
011
100
101
110
111
DigitalOutputCode
If the DNL spec goes beyond -1LSB, then missing codes will appear. The term ‘No Missing Codes’ means that no digital output codes are skipped asthe analog input is swept from zero to full scale.
Most ADCs today will include the specification ‘No missing codes’
1/2 FS 3/4 FS1/4 FS0
Analogue Input Voltage
The 100 Codeis ‘Missing’
12
ADC Specs: Monotinicity
000
001
010
011
100
101
110
111
DigitalOutputCode
If the output code of an ADC is guaranteed to output increasing codes as long as the input signal is increasing, it is called Monotonic
If at some point in the transfer function the digital output code decreases as the analog input increases, then it is non-monotonic. Almost all ADCs on the market today are guaranteed monotonic
1/2 FS 3/4 FS1/4 FS0
Analog Input Voltage
Non-monotonicity
13
ADC Specs: Integral Nonlinearity (INL)
000
001
010
011
100
101
110
111
Ideal transferfunction
Actualtransferfunction
INL < 0
INL is the maximum deviation between an actual code transition point and its corresponding ideal transition point.
Measured in LSBs, and calculated after offset and gain error have been compensated for.
This is a measure of the transferfunction’s deviation from linearity.
A positive INL indicates transition(s)occurring later than ideal. NegativeINL means transition(s) earlier than ideal
INL < 0
DigitalOutputCode
14
ADC Specs: Integral Nonlinearity (INL)
000
001
010
011
100
101
110
111Ideal transferfunction
Actualtransferfunction
INL > 0
INL > 0
DigitalOutputCode
This diagram shows an INL error greater than zero whereas the previous diagram showed INL errors of less than zero.
As you may have guessed, INL and DNL are very closely related; if you have one you also always have the other
15
INL Plot for a (poor, non Silabs) 12bit ADC
0 4095
This INL plot shows the variation of code transition points for each code for a 12 bit ADC
16
But First, a quick look at FFTs……
AC Specs
17
Fast Fourier Transforms (FFT)
10 20 30 40 50-120
-100
-80
-60
-40
-20
0In
put S
igna
l A
mpl
itud
e (d
B)
Frequency (Hz)
4096 points, fin = 10.2kHz, -0.5dB
Number of points taken
Input Signal Frequency
Input Signal Headroom
1/2 of Sampling Rate
18
Fast Fourier Transforms (FFT)
10 20 30 40 50-120
-100
-80
-60
-40
-20
0
Am
plit
ude
(dB
)
Frequency (Hz)
4096 points, fin = 10.2kHz, -0.5dBFundamental or Primary Frequency (The input signal)
Harmonic or Secondary Frequencies (Distortion caused by the part
Average Noise Floor
19
ADC Specs: Total Harmonic Distortion (THD)
A frequency domain spec evaluated using an input sinewave and FFT analysis
Calculated as the ratio of the RMS sum of the number of harmonics (usually the first 5) to the RMS value of the input. It is always specified at a particular frequency and is measured in dB.
In layman’s terms, it is a measure of the amount of signal energy distributed in harmonics vs amount in primary
It is caused by A/D converter nonlinearities, which generate harmonics of the input signal which to appear in the output
Typical values are -78dB to -85dB.
20
THD Plot
10
20
30
40
50
-120
-100
-80
-60
-40
-20
0
Am
plit
ude
(dB
)
Frequency (Hz)
10
20
30
40
50
-120
-100
-80
-60
-40
-20
0
Am
plit
ude
(dB
)Frequency (Hz)
Good THD Bad THD
THD(-dB) = 20LOG (V2)2 + (V3)2 + … + (Vn)2
V1
V1 (Fundamental)
V2 V4V3 V5
21
ADC Specs: Signal to Noise Ratio (SNR)
SNR is a frequency domain spec measured using a sinewave input and FFT analysis
It is the ratio of RMS signal amplitude to the RMS output noise for a specific input frequency and amplitude,excluding harmonic noise
In laymans terms, it’s a measure of how much noise is present with respect to the actual signal
It is expressed in dB Ideal SNR is equal to (6.02n + 1.76 dB) where “n” is the
number of bits For 12-bit A/D, ideal SNR = 74dB
22
ADC Specs: Signal to Noise and Distortion Ratio (SINAD)
SINAD is a frequency domain spec measured using a sinewave input and FFT analysis
It is the ratio of RMS signal amplitude to the RMS sum of the noise and distortion products for a specific input frequency and amplitude
In laymans terms, it’s a measure of noise generated by the part itself
It is expressed in dB
23
Effective Number of Bits vs Noise-Free Bits
Assuming that system noise is Gaussian, histogram will approximate a Normal Distribution
Nu
mb
er
of
Sa
mp
les
ADC Codes
"Bin" that has highestnumber of samples
and is closest to inputsignal
Other "bins" receivesamples due to noise
......
Histogram has a shapethat approximates a
Gaussian PDF (shownas dashed line) due towhite noise mixed withdc input signal voltage
0 2^N102410231022102110201019 1025 1026 1027 1028 1029
24
Noise-Free Resolution
“Effective Noise” is the specification that is used for dynamic signals “Noise-Free Resolution” is the specification that is used for DC
signals involving a display
Nu
mb
er
of
Sa
mp
les
Effective Noise: rms noise isone standard deviation (sigma)
......0 2^N
Noise-Free Resolution:6.6*sigma for 99.9% of
all output codes
25
Example F350 calculation
Out of 1024 samples: Min code = -33 Max code = 32 Average code = -0.5 Variance = 123
1 sigma = sqrt Variance = sqrt (123) = 11 LSBs RMS Noise = +/- 11 LSBs Effective Bits = Log2(223/1 sigma) = 19.5 bits
Noise-Free bits = Log2(2^23/6.6*sigma) = 17 bits 2^17 is 131,072, which equates to 5 ½ digits on the scale
display
26
ADC Specs: Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution of the ADC and is directly related to Signal to Noise+Distortion (SINAD)
ENOB = [SINAD - 1.76]/6.02
For ideal SNR (74dB) and no distortion,
ENOB = [74-1.76]/6.02 = 12 bits!
27
ADC Specs: Spurious Free Dynamic Range (SFDR)
SFDR is a frequency domain measurement that is evaluated using a sine wave input and FFT analysis
The SFDR is always given at a particular frequency SFDR is the difference of Fundamental minus highest spur
in dB. In laymans terms, it’s a measure of the size of the biggest
spike compared to the next biggest spike. In a perfect world, there would be only one big spike
The larger the number the better. SFDR specs range from 80 - 90 dB.
28
SFDR Plot
10 20 30 40 50-120
-100
-80
-60
-40
-20
0
Am
plit
ude
(dB
)
Frequency (Hz)
4096 points, fin = 10.2kHz, -0.5dB
Spurious Free Dynamic Range (SFDR) is the difference between primary and next highest spur
SFDR
29
ADC Specifications: Sample Time and Conversion Time
Every A/D conversion is made up of a sample or tracking period and a conversion period
The terms ‘track and hold’ and ‘sample and hold’ are sometimes interchanged, although most serial ADCs are ‘track and hold’ devices
The period of time when the input signal is sampled or tracked is the Sample Time. Can be measured in time or number of clock cycles
Conversion Time is the time required to convert the sampled input signal to a digital word. Can also be measured in time or number of clock cycles
30
ADC Specifications: Throughput Rate
Throughput rate is the number of times you can do a sample + conversion in a period of time Usually specified in ksps or Msps
Example: A fictitious SAR ADC with sample time of 2 clock cycles and 13 clocks required for a 12 bit word. (Fclk=1Mhz)
15 clocks * 1uS = 15us CS time = 600ns Period = 15us + 600ns = 15.6us
ft = 1/15.6uS = 64 ksps
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