1 2

ThecounterparttoaDACistheADC,whichisgenerallyamorecomplicatedcircuit.OneofthemostpopularADCcircuitisthesuccessiveapproxima>onconverter.

3 4

TheideaofsamplingisfullycoveredintheSignalandLinearSystemscourse.Essen>allywequan>zeananaloguesignalin>meandinamplitude.Quan>zingin>medoesnotlooseinforma>onaslongasthesamplingfrequencyisatleasttwicethemaximumfrequencycomponentofthesignalyouaresampling.Quan>singinamplitudeisachievedthroughaADCandinforma>onislost.Thedifferencebetweentheoriginalanaloguesignalandthedigi>zedsignalisthequan>sa>onnoise.

5

TakeasignalV_IN,digi>zethisusingaADCtoproduceX[N-1:0]andthenconvertthisbacktoanalogueusingaDACtoproduceV_OUT.IfyounowsubtractV_INfromV_OUT,youhavethequan>za>onoise.Thisnoisesignalhasanamplitudeof+/-½aLSB.Ifyouassumethattheinputsignalisrandomandthereforetheamplitudeofthequan>sa>onnoiseisequallylikelytotakeonavaluebetween-½LSBand+½LSB,theRMSvalueofthenoiseiseasilyshowntobearound0.3LSB.WhatistheSignal-to-Noisera>oofann-bitconverter?Thiscanalsobecalculatedeasily.Considerasinewavewithanamplitudeof+/-2^(n-1).Wechoosethisamplitudebecausethisiscentredaround0(nodccomponent)and1LSB=1V,makingthiseasiertoexpresseverythinginLSB.TheRMSvalueofthissinewaveiseasilyshowntobe0.71x2^(n-1)or0.35x2^n.Thereforeforsuchasinewave,theSNRis1.8+6ndB.Inotherwords,foreveryextrabitofADC/DACresolu>on,weaddanextra6dBtotheSNR.

6

Every ADC contains a DAC converter, which provides many threshold voltages. The ADC compares the input voltage to be converter V_IN to these threshold voltages and determine what the converter digital value should be.

Each converter value X therefore corresponds to a range of values of V_IN. This range defines the threshold voltages which is X +/- ½ LSB.

7

ThesimplestADCistheflashADC.Weareconver>ngfromtherangeof0Vto4Vtoadigitalrangeof0to7inbinary.AvoltagedividerwithastringofresistorsR(whichistheDACcircuit)isusedtoprovideallthethresholdvoltagesneeded–i.e.0,0.5,…3.5.7analoguecomparatorsareusedtodeterminewhichvoltageintervalV_INlies.Forexample,ifV_IN=1.75V,thenG1toG3arelogic‘1’andG4toG7are‘0’.ThisproducesthethermometercodewhichisdecodedintoabinarynumberX[2:0].

8

Thedecoderthatmapsthethermometercodetobinarycodeisverysimple–justatruthtable,whichcanbeimplementedinVerilogasacasestatement(similartothe7-segmentdecoderexampleweusedbefore).

9

ThisisasimpleADCusingaDAC.TheSTARTsignalisashortpulsethatasynchronouslyresetthecountertozero.ThisstartstheADCconversion.IfVINisabovethelowestvaluefromDAC,thecounterisenable(HIGHER=1).Thecounterthencountsupun>lVINisnowlowerthantheDACoutput,andcounterisdisabled,andtheDONEsignalgoeshigh.X3:0showsthevalueofthecounterthatmakestheDACjustovertheV_INvalue.Thedisadvantageofthisconverteristhatthe>meittakestoperformaconversionisdependentonthevalueofVIN.Furthermore,ifthisisa16-bitconverter,itcouldtakeover65,000clockcycles–thereforetheconversion>mecanbeverylong.

Wewillnextconsideradifferentschemeusingthesuccessiveapproxima>onalgorithm.

10

Letusassumethattheinputvoltageis2.85VasshownastheREDline.WefirstsettheDACinputX3:0to4’b1000(i.e.assumeMSBtobe‘1’),andcompareV_INtothisthreshold.Youareeffec>velydividingthewhilevoltagerangeintotwohalves:thelowerBLUErange,andtheupperREDrange.V_INbelongstothelowerBLUErange,soweknowserngMSBto‘1’istoohigh.WethereforecleartheMSB.

11

Nextwedividethelowerrangefrom0to4VintotwoequalhalvesagainbyserngX3:0=4’b0100.Thethresholdisnow2.0V.Wearenowtes>ngthesecondmostsignificantbittoseeifthisshouldbe‘1’or‘0’.NowVINbelongstotheupperhalf,thereforewekeepthe‘1’bitwhichwetestedfor.

12

WenowtestthenextbitbyserngX3:0=4’b0110,tes>ngX1.Wearenowdividingtherangefrom2.0Vto4.0Vintotwohalves.VINbelongstothelowerhalf,thereforeweCLEARX1.

13

Finallywetestforthelastbit.VINisintheupperrange,henceLSBis‘1’.Wehavethefinalconverteddigitalvalue:X3:0=4’b0101.

14

ThehardwarearchitectureforaSA-DACisshownhere.WeneedtodesignaFSMtoimplementthealgorithm.ItissimilartothecounterbasedADCwelookatearlier,butthecounterisnowreplacedbyastatemachinethatmakesdecisiononwhethertoresetthe‘1’-bitwhichwastested,andwhatthenextDACvaluetotry.

15

ThestatediagramfortheFSMtoimplementthesuccessiveapproxima>onalgorithmisshownhere.Youshouldbeabletowalkthroughthiseasily.Thelesmostbubbleisthestar>ngpoint,itisini>atedwhenSTARTgoeshigh.WesetX3:0=4’b1000,i.e.theMSB.IfV_INishigherthantheDACvalue,itbelongstotheupperhalf,sowetakethetoptransi>ononthenextclockcycle.Otherwisewetakethebotomtransi>on.Forthetoptransi>on,wekeepX3=1,andsetX2to1forthenextsuccessivetest.Forthebotomtransi>on,weresetX3backto0(becauseX3=1putDACoutputinthewrongrange),andsetX2to1.

Inthisway,wetraceapathallthewaytooneofthestatesintherightmostcolumn.ThestateoutputprovidesthefinalconvertedresultX3:0,andasserttheDONEsignal(high).

16

SofarweassumethatwhiletheADCisperformingconversion,theinputsignalisheldatafixedvoltagelevel.Iftheinputsignalisinfactchanging,theconverteddigitalvaluewillnotbeanaccuratemeasureofVINatthe>meofsampling.ToensurethattheADCinputisheldatafixedvoltage,weusuallyincludefollow-and-holdcircuit.AnanalogueswitchisnormallyturnON,sothatVINiscon>nuouslychargingthecapacitorC.WhentheSTARTpulseac>vatestheADCtotakeasample,theDONEsignalimmediatelygoeslow.ThisshouldopentheswitchandholdtheVINvalueatthe>metheconversionstarted.

17

Aprac>calsample/holdorfollow/holdcircuitisshownhereusingtwoopera>onamplifier.Thishastheadvantagethattheleakagecurrentfromthecapacitorcanbemadeverylow.Duringthesamplingorfollowingmode,therightmostopampprovidesstrongchargingcurrenttochargethecapcitor.

18

Thereisanotherclassofconvertersknownasoversamplingconverters.Theseuseasigma-deltamodulatorcircuitwhichsampletheinputsignalatamuchhighfrequencythantheNyquistfrequencydemands.Normallyitproducesa1-bitdigitalsignalwhichisthandownsampledandfilteredtoproduceanaccurateanalogueoutputforaDAC,andamul>-bitdigitalvalueforaADC.Forexample,CDplayersuseanoversampleDACwithsamplingrateof6.4MHz.Thisisthendownsampledtoproduceanoutputsamplerateof50KHz–aoversamplingra>oof128>mes.

19