IET Power Electronics

Research Article

Modified modulation scheme for three-leveldiode-clamped matrix converter underunbalanced input conditions

ISSN 1755-4535Received on 18th July 2017Revised 18th December 2017Accepted on 17th February 2018doi: 10.1049/iet-pel.2017.0512www.ietdl.org

Mei Su1, Ziyi Zhao1, Hanbing Dan1 , Tao Peng1, Yao Sun1, Ruyu Che1, Fan Zhang1, Qi Zhu1, PatrickWheeler2

1School of Information Science and Engineering, Central South University, Changsha, Hunan 410083, People's Republic of China2Department of Electrical and Electronic Engineering, University of Nottingham, Nottingham NG7 2RD, UK

E-mail: daniel698@sina.cn

Abstract: The three-level diode-clamped matrix converter (TLDCMC) topology has outstanding performance under idealoperating conditions. However, input disturbance can influence the waveforms at the output side of the converter due to thedirect coupling between the input and output. This study proposes a modified modulation scheme for TLDCMC during operationwith unbalanced input voltages and when different transformer turns ratios are used for an isolation transformer at the input.With this modulation technique, sinusoidal and balanced output voltages are guaranteed and the input current harmonics areminimised. Experimental results are presented to demonstrate the feasibility and effectiveness of the proposed modulationscheme.

1 IntroductionMultilevel power converters [1, 2] have a number of advantagesincluding lower output voltage distortion and semiconductor devicevoltage stress. These features make them very suitable for high-power, high-voltage applications, such as large variable-speedmotor drives, high-voltage dc transmission, railway traction andmanufacturing [3–7]. Matrix converters (MCs) also haveadvantages such as four-quadrant operation, sinusoidal input andoutput currents and no large energy storage elements. Bycombining the advantages of multilevel converters and MCs, themultilevel MCs [8–20] are receiving a lot of attention.

Lots of multilevel MC topologies have been studied, consistingof multi-modular MCs [8–12], diode-clamped MCs [13–17], andcapacitor-clamped (flying capacitor) MCs [18–20]. The three-leveldiode-clamped matrix converter (TLDCMC) [16, 17] inherits thefeatures of the conventional multilevel inverter and the indirectmatrix converter (IMC). The phase opposite disposition (POD)modulation method and phase disposition modulation method canboth be applied to the TLDCMC under the assuming ideal inputvoltages [16, 17]. However, in practice, the input voltages arelikely to be unbalanced. Due to the lack of dc-link energy storage,the input disturbance will be transferred directly to the load,thereby influence the quality of the output waveform. Meanwhile,the input current will also become distorted.

Several strategies have been proposed to suppress the problemsassociated with unbalanced input voltages for low voltage MCs.The feed-forward compensation strategy was proposed in [21]. Thefluctuation of virtual dc-link voltage is compensated by modifyingthe modulation index of inverter stage. As a result, balancedsinusoidal output currents are obtained, but the input currentdistortion is not considered. Casadei et al. [22] divide theunbalanced input voltage into positive and negative sequencecomponents and modify the input power factor angle. Experimentalresults were presented in [23] with nearly sinusoidal input andoutput currents under unbalanced input voltage. Lei et al. [24]simplify the implementation of the method in [22], and use a notchfilter to obtain the expected input power factor angle. Yan et al.[25] propose two improved double line voltage synthesis strategiesfor MC to eliminate the input current harmonic under unbalancedcondition. Li et al. [26] propose three modulation strategies toeliminate the weak input current of MC based on a mathematicconstruction. Rojas et al. [27] also proposed three control schemes

based on the predictive control algorithms to compensate for theinput voltage unbalance producing good quality input and outputcurrent waveforms. Lei et al. [28] utilise a feedback controlstrategy to modify input reference current. Resonant controllers areused to regulate input current and instantaneous active power, so asto directly eliminate the input current harmonics and meanwhileensure the load absorbing constant active power under unbalancedinput voltage.

For high-voltage applications, the large power exaggerates thenegative effects introduced by unbalanced input voltages. In three-phase systems, the harmonics will degrade the power quality andalso cause disturbance to other consumers and communicationequipment [29]. Obviously, the option adding large extra activepower filter is often uneconomical. Satisfying load command byadopting a modified modulation scheme is a good way to eliminatethe harmonics at the output of the converter. Similar to the indirectMC, this paper proposes a modified modulation scheme for theTLDCMC during operation with unbalanced input voltages andwhen different transformer turns ratios are used for an isolationtransformer at the input. The modified modulation scheme canachieve good performance in both the input currents and outputvoltages. This paper contributes significant details, a full analysisand experimental results to the basic principles of this modulationmethod [30].

This paper is organised as follows: the converter topology isintroduced in Section 2. Then, Section 3 presents the modifiedmodulation scheme for TLDCMC during operation withunbalanced input voltages and when different transformer turnsratios are used for an isolation transformer at the input. Finally, theeffectiveness of the modified modulation scheme is verified byexperimental results in Section 4.

2 Topology of TLDCMCThe topology of TLDCMC is shown in Fig. 1, which consists of asecond-order inductive-capacitor high-frequency input filter, athree-phase three-winding isolation transformer, a cascaded-rectifier and a three-level diode-clamped inverter.

The cascade rectifier consists of two bidirectional, three-phasecurrent source rectifiers (CSRs) modules connected in series. Thesetwo CSR modules are composed of six bidirectional switch units(S1–S6 and S7–S12). Each bidirectional switch is realised by twoinsulated-gate bipolar transistors (IGBTs) with anti-parallel diode

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pairs connected to a common emitter configuration. The rectifierstage provides three output terminals, P, O and N. The inverterstage is a three-level diode-clamped voltage source inverter, thevalue of dc-link voltage is time-varying.

This topology has the following advantages:

• This topology can be extended to a general multilevel diode-clamped MC easily as shown in Fig. 2. If (n − 1) bidirectionalCSR modules are cascaded to construct a cascaded-rectifier thatcan provide n output terminals, the cascaded rectifier would beconnected to an n-level diode clamped inverter.

• Similar to the IMC, the rectifier stage and the inverter stage canbe controlled independently. A similar modulation scheme canbe used for TLDCMC.

• The TLDCMC can overcome the voltage rating limits of thepower semiconductors for high-voltage applications and avoidthe voltage balance issue associated with conventionalmultilevel topologies. The corresponding derivation is shown inSection 3.2.

3 Modified modulation scheme under unbalancedinput conditionsModulation schemes for the TLDCMC operating under balancedinput voltage conditions have been studied in [16, 17]. In practice,the unbalanced input voltage is a potential problem. In this part, themodified modulation scheme for TLDCMC during operation withunbalanced input voltages and same transformer turns ratios ispresented, firstly. The main idea of the modified modulation

scheme is as follows: a modified modulation matrix for rectifierstage is given to maintain the constant average dc-link voltage, andthe balanced output voltage is obtained by the normal PODmethod. The TLDCMC can avoid voltage balance issue associatedwith conventional multilevel topologies. By modifying themodulation signals in the inverter stage, the modified modulationscheme is extended to fit the TLDCMC during operation withunbalanced input voltages and when different transformer turnsratios are used for an isolation transformer at the input.

3.1 Unbalanced input voltages condition under sametransformer turns ratios

Assume the primary-to-secondary turns ratios of the isolationtransformer are same, the modified modulation method ispresented. In addition, the sinusoidal input current is derived andmaximum output voltage is analysed.

3.1.1 Modified modulation matrix for rectifier stage: For theconvenience, the variables in the three-phase system arerepresented by space vector as

x = 23 xa + xbej2π /3 + xcej4π /3 (1)

For the space vectors x and y, if the space vector x satisfyxa + xb + xc = 0, the following formulation can be established as

Fig. 1  Topology of TLDCMC

Fig. 2  Topology of the general multilevel diode-clamped MC

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32 x ⋅ y =

xa

xb

xc

T ya

yb

yc

(2)

Considering the unbalanced grid, the input voltage vector can berepresented as

Vin = Vpej(ωit + θp) + Vnej( − ωit + θn) (3)

where Vp and Vn are the amplitudes of positive and negativesequence input phase voltage vectors, respectively. θp and θn arethe initial angle of positive and negative sequence input phasevoltage vectors, respectively. ωi is the angular frequency of theinput phase voltage.

The balanced output voltage vector and output current vectorare assumed to be:

Vout = Vomej ωot + θo

iout = Iomej(ωot + θo − ψo)(4)

where ψo is the angle that the load current lags the output voltage.Vom and Iom are the amplitudes of output voltage and output currentvectors. θo is the initial angle of output phase voltage vectors. ωo isthe angular frequency of the output phase voltage.

Then the output power can be calculated as

Po = 32Vout ⋅ iout (5)

In addition, the input power can be expressed as

Pin = 32Vin ⋅ iin (6)

According to active power balance

Po = Pin (7)

The rectifier modulation matrix is defined as MREC for CSR.Assume the MREC as

MREC = Mpej(ωit + θp − ψp) + Mnej( − ωit + θn − ψn) (8)

where ψp and ψn are the power factor angle of positive andnegative sequence input voltage vectors, respectively. Mp and Mnare the modulation factors of positive and negative sequence inputvoltage vectors, respectively.

The average dc-link voltage Vdc of the cascaded-rectifier can begiven as

Vdc = 2Vpo = 2Von = 3NsNp

Vin ⋅ MREC (9)

where Vpo and Von are the average dc-link voltage of rectifier 1 andrectifier 2, respectively. Np/Ns is the primary-to-secondary turnsratios of the isolation transformer. It meetsNp/Ns1 = Np/Ns2 = Np/Ns.

Combining (3), (8) and (9), the average dc-link voltage ofcascaded-rectifier can be expressed as

Vdc = 3NsNp

VpMpcos ψp + VnMncos ψn

+VpMncos(2ωit + θp − θn + ψn)+VnMpcos( − 2ωit + θn − θp + ψp)

(10)

As shown in (10), the value of average dc-link voltage consists of adc term and a second-order harmonic. Since the second-order term

brings low-order harmonics to both sides of the converter, themodulation matrix has to be carefully selected for purposes ofelimination. The following equations can be obtained as

MpVn = MnVp

ψp = π − ψn = φi(11)

where φi is the power factor angle of the unbalanced input voltage.Then, the modified modulation matrix can be described as

MREC = Mp ej(ωit + θp − φi) − VnVp

ej( − ωit + θn + φi) (12)

To make full use of the input voltage and meet MREC < 1, themodified modulation matrix is chosen as follows:

MREC = Vpej(ωit + θp − φi) − Vnej( − ωit + θn + φi)

Vp + Vn(13)

Then the average dc-link voltage can be calculated as

Vdc = 2Vpo = 2Von = 3NsNp

(Vp − Vn)cos φi (14)

The modified rectifier modulation matrix can also be used in all n − 1 CSR modules of general multilevel diode-clamped MC. As aresult, it will yield n levels for the dc-link voltage.

3.1.2 Modulation for inverter stage: When the number ofinverter levels increases, it is more difficult to realise themodulation of the inverter stage using the space vector pulse widthmodulation (SVPWM). Thus, the carrier modulation scheme isconsidered for inverter stage due to the simple implement scheme.For simplicity, the POD method is adopted in this paper, but thetechnique can be applied to other modulation methods.

Assume that the desired output phase voltages are

uA = 2UoRMScos φA

uB = 2UoRMScos φB

uC = 2UoRMScos φC

(15)

where UoRMS is the root mean square (RMS) of the output phasevoltage, respectively. φA, φB and φC denote the phase angle ofoutput voltages, respectively.

To maximise the utilisation of dc-link voltage, the zero-sequence uNO is considered, the modulation signals uiO are asfollows:

uio = ui + uNO, i ∈ A, B, C (16)

where the zero-sequence uNO is chosen as

uNO = − min uA, uB, uC + max uA, uB, uC2 (17)

Normalising the uio, the modulation signals are obtained as

uio = 2 uioVdc

(18)

The modulation signals can be normalised as

dip =uioVpo

when uio ≥ 0

0 when uio ≤ 0, i ∈ A, B, C (19)

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din =0 when uio ≥ 0

−uioVon

when uio ≤ 0, i ∈ A, B, C (20)

where dip denotes the duty cycle of the switching state P (Qi1 andQi2 are ON, while Qi3 and Qi4 are OFF.); din denotes the duty cycleof the switching state N (Qi1 and Qi2 are OFF, while Qi3 and Qi4 areON.).

Assume that the input line-to-line voltage of rectifier stage isuab and uac during the modulation period Ts. The duty ratio of theactive vector uab is dα. The POD method for the inverter stage canbe implemented as shown in Fig. 3.

By adjusting the rectifier modulation matrix, the method cansuppress the effect introduced by unbalanced inputs, which is asimple and easy way to implement. Since the limitation of invertermodulation index, the maximum amplitude of output phase voltageis

Uom max = 3NsNp

(Vp − Vn)cos φi (21)

Thus, the greater the input voltage unbalance, the smaller theoutput voltage capability. If the input voltage is seriouslyunbalanced and the amplitudes of positive and negative sequenceinput phase voltage vectors are equal, the maximum amplitude ofoutput voltage will be zero and the desired output voltage cannotbe synthesised. The proposed modulation scheme is suitable for thecase that input voltage unbalance is relatively small.

For the n-level inverter, the multicarrier-based method with n − 1 carriers should be applied as shown in Fig. 4.

3.1.3 Input current derivations: As for the unbalanced inputvoltage, the input currents can be derived as

ii = NsNp

MREC iP − iN (22)

Fig. 3  POD method for inverter stage

Fig. 4  Multicarrier-based method for n-level inverter

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where ii is the space vectors of source current ii.The average dc-link current in a switching period can be

expressed as follows:

iP = dApiA + dBpiB + dCpiCiN = dAniA + dBniB + dCniCiO = − iP + iN

(23)

The neutral point current iO equals zero when the dc-link voltage isbalanced. Then, after some manipulations with (14), (19), (20), and(23), the following equation can be obtained as

iP − iN = 2PoNp3Ns(Vp − Vn)cos φi

(24)

where Po = uAiA + uBiB + uCiC represents the output active power.Combining (13), (22) and (24), the input current space vector

can be derived as

ii =2Po Vpej(ωit + θp − φi) − Vnej( − ωit + θn + φi)

3cos φi Vp2 − Vn

2 (25)

If Po is constant, the input current ii is sinusoidal and unbalancedwith the proposed modulation scheme under unbalanced inputvoltages according to (25).

3.2 Unbalanced input voltages condition under differenttransformer turns ratios

The TLDCMC does not require balance of the dc-link voltage. Infact, there is no constraint for same transformer turns ratios of theisolation transformer. The modified modulation scheme for sametransformer turns ratios in Section 3.1 is extended in this part. Bymodifying the modulation signals of the inverter stage, themodified modulation scheme is extended to fit the TLDCMCduring operation with unbalanced input voltages and whendifferent transformer turns ratios are used for an isolationtransformer at the input. The desired output voltage and inputcurrent are obtained.

3.2.1 Output voltage derivations: Considering the samemodulation matrix as (13) at rectifier stage and differenttransformer turns ratios for an isolation transformer at the input(Np/Ns1 ≠ Np/Ns2), the average dc-link voltage of the two rectifierscan be calculated as

Vpo = 3Ns1

2Np(Vp − Vn)cos φi

Von = 3Ns2

2Np(Vp − Vn)cos φi

(26)

The average dc-link voltages of the two rectifiers are unequal. Inorder to get the balanced output voltage, the load side switchingfunction is adjusted to compensate dc-link voltage.

To maximise the utilisation of dc-link voltage, the modulationsignals are given as

uio = ui + uNO1 + uNO2, i ∈ A, B, C (27)

where uio is the modulation signals and uNO1, uNO2 are the zero-sequence signals, respectively. The zero-sequence signals areselected as follows:

uNO1 = Vpo − Von2

uNO2 = − min uA, uB, uC + max uA, uB, uC2

(28)

The modulation signals can be normalised as (19) and (20). Then,the balanced output voltage can be obtained. By adding additionalzero sequence components uNO1 to the inverter modulation signals,the method can suppress the effect introduced by differenttransformer turns ratios of the isolation transformer and obtain thedesired output voltage as the equal situation.

From (26) and (28), when the transformer turns ratios are same,the zero-sequence signal uNO1 equals zero and the modulationsignals become exactly same as (16).

Due to the limitation of inverter modulation index, themaximum amplitude of output phase voltage is

Uom max = 3 Ns1 + Ns2

2NpVp − Vn cos φi (29)

when the transformer turns ratios are equal, (29) becomes (21).

3.2.2 Input current derivations: As for the different transformerturns ratios, the average dc-link current in a switching period canbe expressed as follows:

iP = dApiA + dBpiB + dCpiCiN = dAniA + dBniB + dCniC

iO = − uAOVpo

− uAOVon

iA + uBOVpo

− uBOVon

iB

+ uCOVpo

− uCOVon

iC

(30)

The neutral point current iO is not zero when the dc-link voltageVpo is not equal to Von. Then, after some manipulations with (15),(19), (20), (26)–(28) and (30), the following equation could beobtained as

Ns1

NpiP − Ns2

NpiN = 2Po

3(Vp − Vn)cos φi(31)

where Po = uAiA + uBiB + uCiC represents the output active power.The input current space vectorii could be expressed as follows:

ii = MRECNs1

NpiP − Ns2

NpiN (32)

After some manipulations with (13), (31) and (32), the inputcurrent can be written as

ii =2Po Vpej(ωit + θp − φi) − Vnej( − ωit + θn + φi)

3cos φi Vp2 − Vn

2 (33)

Compared (33) with (25), the input current is same and not affectedby the different transformer turns ratios.

Through the analysis of this section, the TLDCMC can workunder the situation that Vpo is not equal to Von. The desired outputvoltage and input current can also be obtained. The modifiedmodulation scheme is fit for TLDCMC during operation withunbalanced input voltages and when different transformer turnsratios are used for an isolation transformer at the input.

4 Experimental resultsTo verify the modified modulation scheme, a low-voltageexperimental prototype is implemented as shown in Fig. 5. Therelated component parameters are listed in Table 1. The cascaded-rectifier uses the SVPWM method and the POD method isemployed in the three-level diode-clamped inverter. In addition,with an appropriate switching sequence, the zero currentcommutation is implemented. The transformer secondary windingsare all in star connections. It is also feasible for the transformersecondary windings in star + delta connections under somemodification of the inverter modulation. In the cascaded-rectifier,

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the IGBT module FF300R12KT3_E is used for the four quadrantpower switches. The IGBT module F3300R12ME4_B23 andF3300R12ME4_B23 are connected in series as the one phase leg ofthe three-level diode-clamped inverter. The voltage stresses of theswitches are related to the input line-to-line peak voltage ofsecondary transformer. The input voltage and the output currentcan be measured through the sensor circuits. A floating-pointdigital signal processor (DSP, TMS320F28335) and a fieldprogrammable gate array (FPGA, EP2C8J144C8N) are equippedwith the controller board. The desired duty ratios of the switchesare calculated in DSP and transmitted to FPGA. Then, the desiredswitching sequences and commutation process are implemented inFPGA.

The following three conditions are experimentally tested toverify the modified modulation scheme. Condition I isexperimentally tested to verify that the TLDCMC can avoid thevoltage balance issue associated with conventional multileveltopologies. In practical application, to maintain the same voltagestress for the semiconductor device at inverter stage, thetransformer turns ratios of the isolation transformer are usuallysame. Thus, Condition II and Condition III with same transformerturns ratios are considered.

Condition I: The converter is fed by balanced input voltage 220 V/50 Hz (RMS). The transformer used for experiments has a fixedprimary-to-secondary ratio of 380:200 and 380:100, respectively.Condition II: The converter is fed by balanced input voltage 115 V/50 Hz (RMS). The phase shifts among three input phase voltagesare 120°. The transformer used for experiments has a fixed primaryto secondary ratio of 380:200.Condition III: The a-phase and b-phase input voltages are 115 V/50 Hz (RMS), while c-phase input voltage is 81 V/50 Hz (RMS).The phase shifts among three input phase voltages are 120°. Thetransformer used for experiments has a fixed primary to secondaryratio of 380:200.

Fig. 6 shows the experimental waveforms under Condition I,when the amplitude and frequency of desired output phase voltageare set to 140 V/30 Hz. As seen, the nearly sinusoidal inputcurrents are achieved when the isolation transformer has differenttransformer turns ratios. As for the conventional three-level diodeclamped inverter, the voltages of the two dc-link capacitors shouldbe controlled to achieve equal voltage. However, the TLDCMCcan avoid the voltage balance issue. As seen in Fig. 6a, the dc-linkvoltages of two rectifiers are different because of the differenttransformer turns ratios of the isolation transformer. However, thebalanced output currents are obtained as seen in Fig. 6c. The outputline-to-line voltage is characterised by five levels.

Figs. 7 and 8 show the experimental waveforms underCondition II, when the amplitude and frequency of desired outputphase voltage is set to 80 V/30 Hz and 80 V/60 Hz, respectively.As seen, the balanced input currents and output currents areachieved when the input voltages are balanced. The input andoutput currents are nearly sinusoidal. The distortion of inputcurrents is mainly caused by the dead-time, device voltage drop,distorted no-load current in the transformer and so on. The relatedtotal harmonic distortion (THD) values of input and output currentsare listed in Table 2.

Figs. 9 and 10 show the experimental waveforms underCondition III, when the amplitude and frequency of desired outputphase voltage are set to 80 V/30 Hz and 80 V/60 Hz, respectively.As seen, the nearly sinusoidal input currents and output currentsare achieved when the input voltages are unbalanced. The relatedTHD values of input and output currents are listed in Table 2.Comparing the output current waveforms under Condition II andCondition III, there is no obvious difference between them. Themodified modulation scheme is verified by the experimentalresults.

5 ConclusionThis paper has presented the implementation of a modifiedmodulation scheme for the TLDCMC during operation withunbalanced input voltages and when different transformer turnsratios are used for an isolation transformer at the input. The goodperformance of input and output currents is obtained. The modifiedmodulation scheme is also applicable to the generalised multileveldiode-clamped MC under unbalanced input voltage. Theexperimental results validate the correctness and feasibility of theproposed modulation method and the feature that the TLDCMCcan avoid the voltage balance issue associated with multileveltopologies. Moreover, the modified modulation scheme can also beused under ideal operating conditions.

6 AcknowledgmentsThis work was supported in part by the National Natural ScienceFoundation of China under Grant 61573382, 61622311 and51677195, in part by the Fundamental Research Funds for theCentral Universities of Central South University under Grant2017zzts466, and in part by the Wasion Group in Changsha, China.

Table 1 Component parameters of experimental prototypeParameters Valueswitching frequency (fs) 5 kHzinput filter inductor (Ls) 0.6 mHinput filter capacitor (Cf1, Cf2) 22 μFdamping resistor (Rs) 9 Ωload resistor (R) 13.33 Ωload inductor (Lo) 6 mHcurrent sensor LT308-S7

Fig. 5  Experimental prototype of TLDCMC

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Fig. 6  Experimental waveforms with a reference output phase voltage of 140 V/30 Hz under Condition I(a) Ch1: the a1-phase input voltage of the secondary transformer winding 1 Va1, Ch2: the a2-phase input voltage of the secondary transformer winding 2 Va2, Ch3: the average dc-link voltage of rectifier 1 Vpo, Ch4: the average dc-link voltage of rectifier 2 Von, (b) Ch1: the dc-link voltage Vdc, Ch2: the a-phase input current, Ch3: the b-phase input current,Ch4: the c-phase input current, (c) Ch1: the output line-to-line voltage UAB, Ch2: the A-phase output current, Ch3: the B-phase output current, Ch4: the C-phase output current

Fig. 7  Experimental waveforms with a reference output phase voltage of 80 V/30 Hz under Condition II(a) Ch1: the input phase voltage Va, Ch2: the input phase voltage Vb, Ch3: the input phase voltage Vc, (b) Ch1: the dc-link voltage Vdc, Ch2: the a-phase input current, Ch3: the b-phase input current, Ch4: the c-phase input current, (c) Ch1: the output line-to-line voltage UAB, Ch2: the A-phase output current, Ch3: the B-phase output current, Ch4: the C-phaseoutput current

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Fig. 8  Experimental waveforms with a reference output phase voltage of 80 V/60 Hz under Condition II(a) Ch1: the dc-link voltage Vdc, Ch2: the a-phase input current, Ch3: the b-phase input current, Ch4: the c-phase input current, (b) Ch1: the output line-to-line voltage UAB, Ch2: theA-phase output current, Ch3: the B-phase output current, Ch4: the C-phase output current

Table 2 THD values of the input and output currents under Conditions II and IIICondition, % ia ib ic iA iB iCII-80 V/30 Hz 12.32 12.25 12.37 4.49 4.52 4.54II-80 V/60 Hz 12.12 12.58 13.50 2.90 3.05 2.94III-80 V/30 Hz 13.00 11.92 8.87 4.87 4.93 4.80III-80 V/60 Hz 13.03 11.50 8.65 3.82 3.80 3.73

Fig. 9  Experimental waveforms with a reference output phase voltage of 80 V/30 Hz under Condition III(a) Ch1: the input phase voltage Va, Ch2: the input phase voltage Vb, Ch3: the input phase voltage Vc, (b) Ch1: the dc-link voltage Vdc, Ch2: the a-phase input current, Ch3: the b-phase input current, Ch4: the c-phase input current, (c) Ch1: the output line-to-line voltage UAB, Ch2: the A-phase output current, Ch3: the B-phase output current, Ch4: the C-phaseoutput current

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Fig. 10  Experimental waveforms with a reference output phase voltage of 80 V/60 Hz under Condition III(a) Ch1: the dc-link voltage Vdc, Ch2: the a-phase input current, Ch3: the b-phase input current, Ch4: the c-phase input current, (b) Ch1: the output line-to-line voltage UAB, Ch2: theA-phase output current, Ch3: the B-phase output current, Ch4: the C-phase output current

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