ULTRASPARC 2005 INTRODUCTION AND ISA

BY JAMES MURITHI

OVERVIEW

HYPERVISOR DESIGN SCALABILITY IS KEY COMPATIBILITY

PROCESSOR ARCHITECTURE INTEGER UNIT FLOATING POINT UNIT

IMPLICATIONS

NEED FOR MORE INSTRUCTIONS THESE NEED SPECIAL REGISTERS

WHATS NEW

VIS HYPERPRIVILEDGED MODE CMT

ISA

RISC PROCESSOR 64 BIT ARCHITECTURE 32 BIT INSTRUCTIONS LOAD STORE ARCHITECTURE INTS, FLOATS, SIMDS BYTE(8BITS), HALF,DOUBLE,QUAD

ADDRESSING MODES

REGISTER DIRECT AND INDIRECT IMMEDIATE

INSTRUCTION FORMATS

ENCODED IN 32 BITS IMPLEMENTS SEVERAL MINOR FORMATS TWO ADDRESS THREE ADDRESS NO ADDRESS - CALLS

ENCODING

00 rd Op rs1 Set bit

Immediate asi? rs2

Class code Branch/Call/Arithmetic/Logical

10 rd Op rs1 Set bit Immediate?

asi?

rs2

When 0 value is in rs2 when 1 use immediate

DATA TYPES

FLOATS , INTS SIMD – DEFINES THREE TYPES

INSTRUCTIONS

REGISTER WINDOW MGT PRIVILEDGED REGISTER ACCESS MEMORY SYNC IMPLEMENTATION DEPENDENT

REGISTERS

GPR REGISTER WINDOW

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THANK YOU