Sun Microsystems’UltraSPARC-IIi

a Stunt-Free Presentation

by

Christine Munson

Amanda Peters

Carl Sadler

Overview

• Scalable Processor ARChitecture– allows “scalable” range of price and

performance options

– different numbers of CPU registers can be implemented

• RISC Processor

• Introduced in 1987

• Now primarily used by multiple-processor Unix workstations

Specifications

• 64-bit memory addresses

• 64-bit integer operations

• 4-way SuperScalar design

• Available in speeds of 270, 300, 333 or 360 MHz

• Nine-stage processor pipeline

• VIS instruction set for multimedia performance

Basic Architecture

• Integer Unit (IU)– basic processing and integer arithmetic

• Floating Point Unit (FPU)– floating-point arithmetic

– processes concurrently with IU

• PCI Bus Module (PBM)– provides a direct interface between the

CPU and PCI bus, maximizing data transfer efficiency

Other Units

• Load/Store Buffer Units (LSU)– handles loads and stores

• Graphics Unit (GRU)– utilizes VIS graphics instructions for

high-performance multimedia processing

• Prefetch and Dispatch Unit (PDU)– manages instructions to minimize

execution units’ downtime

Block Diagram - Typical Setup

IU Control/Status Registers

• Program Counter (PC)– contains address of current instruction

• Next PC (nPC)– contains address of next instruction

• Processor State Register (PSR)– processor status

– condition code flags

– five-bit Current Window Pointer (CWP)

IU Control/Status Registers Cont’d

• Window Invalid Mask (WIM)– 32-bits, representing windows

– bit values represent invalid windows

• Trap Base Register (TBR)– points to trap handler

– contains trap type code

• Y Register– allows creation of 64-bit products

General-Purpose Registers

• 8 Window Registers, 8 Global Registers

• Window Registers overlap in circular fashion

• Overflows and underflows are trapped by WIM so that they can be accommodated by software

Circular 8-Window Implementation

Instruction Set

• ~140 Standard SPARC-V9 Instructions

• Six categories:– Load/Store

– Arithmetic/Logical/Shift

– Control Transfer

– Read/Write Control Registers

– Floating Point

– Coprocessor

Instruction Formats

• 32-bit instructions

• Bits 30 and 31 specify format

• Immediate/Implied Addressing

Memory

• 64-bit addresses

• Upper 32 bits can be masked with zero for backwards compatibility

• Location expressed by typical register offset scheme

Memory Controller Unit (MCU)

• Controls all memory accesses

• External transceivers allow DRAM data to be double the width of the processor’s memory pins:– Processor: 72 bits

• 64 bits + 8-bits for Error Control Code

– With MCU: 144 bits• 128 bits + 16-bit ECC

• Significant to both performance and compatibility

Typical Memory Configuration

Processor Pipeline

• Most instructions occur over nine stages

• Instructions are considered terminated after the last stage (write)

Pipeline Stages

• Stage 1: Fetch Stage (F)– up to four instructions retrieved from

Instruction Cache

• Stage 2: Decode Stage (D)– instructions are pre-decoded and sent to

the Instruction Buffer

• Stage 3: Group Stage (G)– up to four instructions are received

from the PDU

– instructions are grouped, weighted, and dispatched to the appropriate units

Pipeline Stages Continued

• Stage 4: Execution Stage (E)– instructions are executed and a virtual

memory address of the instruction is calculated

• Stage 5: Cache Access Stage (C)– the virtual memory address is verified

and converted to a physical address

• Stage 6: N1 Stage– cache misses are handled

– physical address is sent to the Store Buffer

Pipeline Stages Continued

• Stage 7: N2 Stage– most floating-point instructions

complete at this stage

• Stage 8: N3 Stage– traps are resolved

• Stage 9: Write Stage (W)– final results written to register files

– instruction is considered terminated

VIS Instruction Set

• Specialized extension to the standard SPARC instruction set

• ~50 instructions

• Utilizes a Graphics Status Register (GSR)

• Provides high-performance graphics data manipulation

• Allows variable partitioning of 64-bit registers for numerical processing, reminiscent of saturation arithmetic

VIS Data Formats

• Standard partitioning formats accommodate common graphics representations

VIS Instruction Format

• Standard instruction format accommodates implementation-specific opcodes

Role in the Marketplace

• Scalable architecture makes SPARC family highly marketable

• Open Architecture - manufacturers can buy licenses to produce SPARC-compliant systems

• Increasing speed– 1.5 GHz by 2002

• Overall, high-performance modules, single-chip solution

End