Gujarat Power Engineering & Research Institute

TOPIC:- Types of Flip Flops

Prepared by:- VIRAJ SHAH

Types of Flip Flops

Edge-Triggered Flip-flopsS-R Flip-flopD Flip-flopJ-K Flip-flopT Flip-flop

Edge-Triggered Flip-flops 3CS1104-11

Edge-Triggered Flip-flops S-R, D and J-K edge-triggered flip-flops. Note the “>”

symbol at the clock input.

S CR

Q

Q'

S CR

Q

Q'

D C

Q

Q'

D C

Q

Q'

J CK

Q

Q'

J CK

Q

Q'

Positive edge-triggered flip-flops

Negative edge-triggered flip-flops

SR Flip-flop 4CS1104-11

S-R Flip-flop S-R flip-flop: on the triggering edge of the clock pulse,

S=HIGH (and R=LOW) a SET stateR=HIGH (and S=LOW) a RESET stateboth inputs LOW a no changeboth inputs HIGH a invalid

Characteristic table of positive edge-triggered S-R flip-flop:

X = irrelevant (“don’t care”) = clock transition LOW to HIGH

S R CLK Q(t+1) Comments

0 0 X Q(t) No change0 1 0 Reset1 0 1 Set1 1 ? Invalid

SR Flip-flop 5CS1104-11

S-R Flip-flopThe pulse transition detector.

SQ

Q'CLK

Pulse transitio

n detector R

Positive-going transition(rising edge)

CLKCLK'

CLK*

CLK'

CLK

CLK*

Negative-going transition(falling edge)

CLK'

CLK

CLK*

CLKCLK'

CLK*

SR Flip-flop 6CS1104-11

S-R Flip-flopThe pulse transition detector.

SQ

Q'CLK

Pulse transitio

n detector R

Positive-going transition(rising edge)

CLKCLK'

CLK*

CLK'

CLK

CLK*

Negative-going transition(falling edge)

CLK'

CLK

CLK*

CLKCLK'

CLK*

D Flip-flop 7CS1104-11

D Flip-flop D flip-flop: single input D (data)

D=HIGH a SET state D=LOW a RESET state

Q follows D at the clock edge. Convert S-R flip-flop into a D flip-flop: add an inverter.

A positive edge-triggered D flip-flop formed with an S-R flip-flop.

S CR

Q

Q'CLK

D D CLK Q(t+1) Comments

1 1 Set0 0 Reset

= clock transition LOW to HIGH

D Flip-flop 8CS1104-11

D Flip-flop Application: Parallel data transfer.

To transfer logic-circuit outputs X, Y, Z to flip-flops Q1, Q2 and Q3 for storage.

* After occurrence of negative-going transition

Q1 = X*

D

CLK

Q

Q'

Q2 = Y*

D

CLK

Q

Q'

Q3 = Z*

D

CLK

Q

Q'

Combinational logic circuit

Transfer

X

Y

Z

J-K Flip-Ffop 9CS1104-11

J-K Flip-flop J-K flip-flop: Q and Q' are fed back to the pulse-steering

NAND gates. No invalid state. Include a toggle state.

J=HIGH (and K=LOW) a SET stateK=HIGH (and J=LOW) a RESET stateboth inputs LOW a no changeboth inputs HIGH a toggle

J-K Flip-flop 10CS1104-11

J-K Flip-flop J-K flip-flop.

Characteristic table.

JQ

Q'CLK

Pulse transitio

n detectorK

J K CLK Q(t+1) Comments

0 0 Q(t) No change0 1 0 Reset1 0 1 Set1 1 Q(t)' Toggle

Q J K Q(t+1)

0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 0

Q(t+1) = J.Q' + K'.Q

T Flip-flop 11CS1104-11

T Flip-flop T flip-flop: single-input version of the J-K flip

flop, formed by tying both inputs together.

Characteristic table.T CLK Q(t+1) Comments

0 Q(t) No change1 Q(t)' Toggle

Q T Q(t+1)

0 0 00 1 11 0 11 1 0

Q(t+1) = T.Q' + T'.Q

TQ

Q'CLK

Pulse transitio

n detector

J CK

Q

Q'CLK

T

T Flip-flop 12CS1104-11

T Flip-flop Application: Frequency division.

Application: Counter (to be covered in Lecture 13.)

J

C

K

QCLK

High

CLK

Q

Divide clock frequency by 2.

J

C

K

QA

CLK

High

J

C

K

QBHigh

CLK

QA

QB

Divide clock frequency by 4.