tuesday, june 6 · increase the capacity of bdd-based model checking. the first paper investigates...

Tuesday, June 6

Exhibit Hours 10:00AM – 6:00PM / Demo Suite Hours 8:00AM – 9:00PM

9:00 to

10:15

General Session and Keynote Speaker (no badge is required) Room: Concourse Hall

First-Time-Right Si but to the Right SpecificationTheo Claasen - Chief Technical Officer

Philips Semiconductors, Eindhoven, The NetherlandsOpening Remarks • Awards • Keynote Address

10:30 to

12:00

2:00 to

4:00

4:30 to

6:00

6:00 to

7:00

BREAK

LUNCH 12:00 - 2:00

New Techniquesfor Synthesis and

Mapping

Formal Verification Test Issues forDeep-SubmicronSystem-on-Chips

2 EmbeddedTutorials

Panel : DesignClosure: Hope

or Hype?

Session 6 Session 7 Session 8 Session 10

Algorithms for RFSimulation and

Model Reduction

Verification andDebugging

Methodologies

Design Methodsfor EmergingTechnologies

Panel : EDA Meets.Com: How E-Services will

Change the EDABusiness Model


BREAK

DAC Cocktail Party at the Los Angeles Convention Center6:00PM - 7:00PM

Analog and RF BDD-Based ModelChecking

Test Generationand Diagnosis

InterconnectModeling

Room 404AB Room 408A Room 406AB Room 408B Room 403


Life at the End ofCMOS Scaling(And Beyond)

Session 5

Clock and PowerGrid Analysis for

High PerformanceDesigns

Signal Integrity

Session 9

Session 14

All Design Methods Sessions are shaded blue, Embedded Systems Sessions are shaded grey.1

conferenceat a glance

Presenters will be available in designated rooms for an additional 20-minute question and answer sessions.

indicatesvideoedsession

Wednesday, June 7

37th Dac Party 7:30PM - 10:00PM at the Westin Bonaventure

Timing Analysisand Verification

Logic/Physical Co-Design

Power Analysisand Optimization for

EmbeddedSoftware

EmbeddedCompilationTechniques

Panel : FutureSystems-on-

Chip: Software orHardware Design?


Session 16 Session 17 Session 18 Session 19 Session 20

BREAK

Embedded Systems Plenary Panel:

Embedded Systems Design in the New Millennium

Room: Concourse Hall

Plenary Panel

LUNCH 12:00 - 2:00

New Techniques inPower Estimationand Performance

Improvement

Combined GlobalRouting, Buffering

and Wiresizing

Advances inSystem Modeling

and Synthesis

Designing Systemson a Chip

Embedded TutorialIncluded

Panel : The Futureof System Design

Languages


BREAK

Mixed SignalDesign and

Analysis

Floorplanning &Placement

System LevelScheduling

Architectures forEmbeddedSystems

Panel: EmbeddedSystems Education


Exhibit Hours 10:00AM – 6:00PM / Demo Suite Hours 8:00AM – 9:00PM

2

8:30 to

10:00

10:30 to

12:00

2:00 to

4:00

4:30 to

6:00


All Design Methods Sessions are shaded blue, Embedded Systems Sessions are shaded grey.



Thursday, June

3

BREAK

InterconnectAnalysis

High LevelSynthesis forDSPs: Data

IntensiveApplications

Embedded Tutorial:MOSFET Modelingand Circuit Design:Re-Establishing aLost Connection

ReconfigurableComputingSystems

Panel : SurvivalStrategies forMixed-Signal

Systems-On-Chip



IntellectualProperty Protection

& Re-use

Correctness Issuesin High Level

Synthesis

SoC TestMethodologies andDefect Modelling

EmbeddedTutorial: Bridgingthe Gap BetweenFull Custom and

ASIC Design

Panel : CaseStudies: ChipDesign on theBleeding Edge


LayoutOptimization

DecisionProcedures forCAD Problems

Embedded TutorialIncluded

New Frameworksfor the EDA FieldPanel: Web-BasedFrameworks to

Enable CAD R&D

High PerformanceMicroprocessor

Design

Panel : When BadThings Happen to

Good ChipsEmbedded Tutorial

Included


BREAK

Large-ScaleParasitic Analysis

Advances in HighLevel Synthesis

Fault Simulationand Extraction ofLow-Level Effects

Low Power DesignTechniques and

Estimation


Demo Suite Hours 8:00AM – 5:00PM

Panel : EmergingCompanies:

Acquiring MindsWant to Know

Session 50

8:30 to

10:00

10:30 to

12:00

2:00 to

4:00

4:30 to

6:00

KEYNOTE 1:00 - 1:45 (Lunch Not Included) Room: Concourse HallSystem Design Challenges in the Post-PC Era

Hugo De Man - Senior Research Fellow of IMEC, Professor, Katholieke Univ., Leuven, Belgium





Tutorials Friday, June 9

4

Tutorials will be held at the Los Angeles Convention Center in the Second Level meeting rooms.

8:00 AM - Tutorial Registration Opens (Second Level) 12:00 Noon - Lunch - Rm. 515AB8:30 AM - Continental Breakfast - Rm. 515AB 5:00 PM - Tutorials End9:00 AM - Tutorials Begin

Tutorial 1 Room 403ATutorial 1 Room 403AThe Quest for Synthesis and Layout Timing ClosureOrganizers: Jason Cong - Univ. of California, Los Angeles, CA

Patrick Groeneveld - Magma Design Automation, Inc., Cupertino, CA

Tutorial 2 Room 404ATutorial 2 Room 404A

Static Timing Analysis and Optimization for High-Performance Digital SuccessOrganizers: Tim Burks - Magma Design Automation, Inc., Cupertino, CA

David Blaauw - Motorola, Inc., Austin, TX

Tutorial 3 Room 403BTutorial 3 Room 403B

System Level Design with Embedded PlatformsOrganizers: Kees Vissers - Phillips Research Labs., Briarcliff Manor, NY

Bart Kienhuis - Univ. of California, Berkeley, CA

Tutorial 4 Room 408ATutorial 4 Room 408A

Signal Integrity in Deep Submicron DesignsOrganizer: Chung-Kuan Cheng - Univ. of California, San Diego, CA

Tutorial 5 Room 408BTutorial 5 Room 408B

Design Technology for Building Wireless Systems-on-ChipOrganizer: Rajesh Gupta - Univ. of California, Irvine, CA

Tutorial 6 Room 406ABTutorial 6 Room 406AB

Low Power System Design: Applications, Architectures, andDesign MethodologiesOrganizer: Anand Raghunathan - NEC USA, C&C Research Labs., Princeton, NJ


Topics and Related Sessions

5


Embedded Systems: Sessions: 18, 19, 20, 23, 24, 25, 28, 29, 30, Tutorial: 3

System Design & Optimization: Sessions: 21, 23, 25, 28, 34, 44, 45, Tutorials: 5 & 6

Logic & High Level Synthesis & Optimization: Sessions: 6, 10, 17, 32, 37, 42, 47, Tutorials: 1 & 2

Logic & Functional Verification & Simulation: Sessions: 2, 7, 12, 37, 42, Tutorial: 2

Electrical Modeling & Simulation: Sessions: 4, 9, 11, 14, 46, Tutorial: 2

Physical Design: Sessions: 9, 10, 17, 22, 27, 39, 41, Tutorials: 1 & 2

Validation & Test: Sessions: 2, 3, 7, 8, 12, 16, 38, 45, 48, Tutorial 2

Impacts of Advancing Technology: Sessions: 5, 13, 40

Device & Interconnect Modeling: Sessions: 4, 9, 10 14, 22, 31, 33, 46, Tutorials: 1, 2 & 4

Analog and Mixed Signal Design: Sessions: 1, 11, 26, 35

Low Power Design: Sessions: 18, 21, 39, 49, Tutorial: 6

Design Re-use, IP and SoC Issues: Sessions: 8, 15, 20, 24, 34, 36, 38, 43, Tutorial: 5

If you are interested in the following topics please see the related sessions below.

Opening Session - Tuesday, June 6

6

Opening Remarks : Giovanni DeMicheli - General Chair, 37th DAC

Awards presented by : Steven P. Levitan - ACM/SIGDA RepresentativeMichael Lightner - IEEE/CAS Representative

Opening Keynote Address :

Theo Claasen - Chief Technical Officer, Philips Semiconductors, Eindhoven, The Netherlands

Awards/Scholarships

ASCEE Undergraduate Scholarships

Scholarships will be awarded to four high school students who will be pursuing a degree in Electrical Engineering orComputer Science from under-represented minorities.

Graduate Scholarships

Scholarships will be awarded to four graduate students to support research in Design Automation. Student Design Contest Award

Award will be presented to the school sponsoring the best entry to the contest.

Best Paper Awards

Best Paper Awards will be given in the following areas:

1. Design Synthesis, Test and Validation 3. Design Methodology2. Analog/RF/Electrical Modeling and Simulation 4. Embedded Systems

Individual Awards

IEEE/CAS Industrial Pioneer Award2000 IEEE FellowsCAD Transactions Best Paper AwardVLSI Transactions Best Paper AwardOutstanding Young Author AwardACM Outstanding Ph.D Dissertation Award in Electronic Design AutomationIEEE Third Millenium MedalsIEEE/CAS Golden Jubilee Medals

technicalprogram

Tuesday, June 6

7

10:30to

12:00

chnical program

All speakers aredenoted in Bold

S - denotes shortpaper

§ - denotes bestpaper

SSeessssiioonn 22ROOM: 408A

BDD-BASED MODEL CHECKINGCHAIR: Andreas Kuehlmann - IBM Corp.,

Yorktown Heights, NYORGANIZERS: Limor Fix, Timothy KamThis session presents four novel approaches toincrease the capacity of BDD-based modelchecking. The first paper investigates the transition-function-based and transition-relation-basedmethods to compute the image during statetraversal and describes a new approach to combineboth. The second paper presents the application ofuser-provided hints to guide the state traversal forCTL model checking. The following presentationdescribes a technique to optimize the modelchecking process by dynamically excludingirrelevant parts of the design from it. The last paperpresents an alternative heuristic to prioritize thestate traversal in order to boost its capacity.

2.1 To Split or to Conjoin: The Question inImage ComputationIn-Ho Moon - Univ. of Colorado, Boulder, COJames Kukula - Synopsys, Inc., Beaverton, ORKavita Ravi - Cadence Design Systems, Inc., New Providence, NJFabio Somenzi - Univ. of Colorado, Boulder, CO2.2 Symbolic Guided Search for CTLModel CheckingRoderick Bloem - Univ. of Colorado, Boulder, COKavita Ravi - Cadence Design Systems, Inc., New Providence, NJFabio Somenzi - Univ. of Colorado, Boulder, CO2.3S Lazy Symbolic Model CheckingJin Yang - Intel Corp., Hillsboro, ORAndreas Tiemeyer - Intel Corp., Swindon, UK2.4S Distance Driven Finite State MachineTraversalAndreas Hett, Christoph Scholl, Bernd Becker - Univ. ofFreiburg, Freiburg, Germany

SSeessssiioonn 11ROOM: 404AB

ANALOG AND RFCHAIR: Joel R. Phillips - Cadence Design Systems, Inc.,

San Jose, CAORGANIZERS: Hidetoshi Onodera, Joel PhillipsThis session surveys progress in synthesis, symbolicanalysis, and statistical analysis of analog circuits.

1.1 A Case Study of Synthesis for IndustrialScale Analog IP: Redesign of the Equalizer/FilterFrontend for an ADSL CodecRodney Phelps, Michael Krasnicki, Rob A. Rutenbar, L. RichardCarley - Carnegie Mellon Univ., Pittsburgh, PAJames R. Hellums - Texas Instruments, Dallas, TX1.2S Optimal RF Design Using SmartEvolutionary HardwarePeter Vancorenland, Carl Deranter, Michiel Steyaert -Katholieke Univ., Leuven, Belgium1.3S Cyclone: Automated Design and Layout ofRF LC-OscillatorsCarl De Ranter, Bram De Muer, Geert van der Plas, PeterVancorenland - Katholieke Univ., Leuven, BelgiumMichiel Steyaert, Georges Gielen, Willy Sansen - KatholiekeUniv., Leuven, Belgium1.4S An Asymptotically Constant, LinearlyBounded Methodology for the StatisticalSimulation of Analog Circuits IncludingComponent Mismatch EffectsCarlo Guardiani - - PDF Solutions, San Jose, CASharad Saxena - - PDF Solutions, Richardson, TXPatrick McNamara, Philip Schumaker, Dale Coder - PDFSolutions, San Jose, CA1.5S Multi-Terminal Determinant DecisionDiagram: A New Approach to Symbolic/NumericAnalysis of Large Analog Integrated CircuitsTao Pi, C.-J. Richard Shi - Univ. of Washington, Seattle, WA


§

Tuesday, June 6

8


TEST GENERATION ANDDIAGNOSISCHAIR: Robert Aitken - Hewlett-Packard Co.,

Palo Alto, CAORGANIZER: Kwang-Ting (Tim) ChengThis session includes test generationand diagnosis techniques for a variety offault models and circuits described atdifferent levels of abstraction. The firstpaper deals with RTL test generation.The second paper presents a BISTmethod for FPGAs. The third paperdescribes a diagnosis technique forscan-based BIST. The fourth paperintroduces an enhanced delay faultmodel and a diagnosis technique for it.

3.1 Automatic Test PatternGeneration for Functional RTL CircuitsUsing Assignment Decision DiagramsIndradeep Ghosh, Masahiro Fujita - FujitsuLabs. of America, Sunnyvale, CA3.2 Interconnect Testing in Cluster-Based FPGA ArchitecturesIan G. Harris, Russell Tessier - Univ. ofMassachusetts, Amherst, MA3.3S Improved Fault Diagnosis inScan-Based Bist via SuperpositionIsmet Bayraktaroglu, Alex Orailoglu - Univ. ofCalifornia at San Diego, La Jolla, CA3.4S On Diagnosis of Pattern-Dependent Delay FaultsIrith Pomeranz, Sudhakar M. Reddy - Univ. ofIowa, Iowa City, IA

SSeessssiioonn 44ROOM: 408B

INTERCONNECTMODELINGCHAIR: Nick P. van der Meijs - Delft Univ. of

Tech., Delft, The NetherlandsORGANIZERS: Ralph H.J.M. Otten, Anantha

ChandrakashanFast and accurate analysis of interconnectis increasingly important for performanceestimation of deep submicron circuits.Inductance, conveniently neglected in thepast, can no longer be ignored. The firstpaper addresses that point. The secondpaper presents a wealth of practical dataon this issue. The two final papers aremore general in nature: efficienttechniques in model reduction and areevaluation for the so-called miller effecton interconnect capacitance.

4.1 On-Chip Inductance Modelingand AnalysisKaushik Gala, Vladimir Zolotov, Rajendran V.Panda, Brian Young, Junfeng Wang, David Blaauw -Motorola, Inc. Austin, TX4.2 A Practical Approach to ParasiticExtraction for Design of Multimillion-Transistor Integrated CircuitsEileen You, Lakshminarasimh Varadadesikan,John Macdonald, Weize Xie - Sun Microsystems,Palo Alto, CA4.3S A Rank-One Update Method forEfficient Processing of InterconnectParasitics in Timing AnalysisHarold Levy, William Scott, Don MacMillan -Synopsys, Inc., Mountain View, CAJacob K. White - Massachusetts Instittute ofTechnology, Cambridge, MA4.4S Revisiting the Switch FactorBased Analysis Methodology forCoupled RC InterconnectsSudhakar Muddu, Egino Sarto - SGI, MountainView, CA

SSeessssiioonn 55ROOM: 403

LIFE AT THE END OFCMOS SCALING (ANDBEYOND)CHAIR: Rob A. Rutenbar - Carnegie Mellon

Univ., Pittsburgh, PAORGANIZER: Rob A. RutenbarIt is clear by now that CMOSscaling cannot continue forever, andthat we will soon require a radicaltechnology change. And yet,exceedingly small MOS devices arebeing created today, devices about ahundred atoms wide. Will we really beable to scale this far down? What are theobstacles to making such aggressivelyscaled devices usable as circuits? Andwhat might come after CMOS? Ourinvited speakers will fearlessly speculateon these problems.

5.1 INVITED PAPER: CMOSTransistor Scaling LimitChenming Hu - Univ. of California, Berkeley, CA5.2 INVITED PAPER: Circuits andInterconnect in Aggressively ScaledMOSMark Horowitz - Stanford Univ., Stanford, CA5.3 INVITED PAPER: Single ElectronSwitches and Memory: Devices,Technology and Design IssuesSteve Chou - Princeton Univ., Princeton, NJ

technicalprogram

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Tuesday, June 6

9

2:00to

4:00

chnical program




FORMAL VERIFICATIONCHAIR: Limor Fix - Intel Semiconductors Ltd., Haifa, IsraelORGANIZERS: Timothy Kam, Andreas KuehlmannFormal verification is scaling up in many dimensions.From the application point of view, it is scaling upfrom RTL verification to micro-architecture andsoftware verification. From the technology point ofview, it is scaling up from BDD-based algorithms toATPG and constraint solving techniques. The papersin this session reflect this trend.

7.1 Formal Verification of SuperscalarMicroprocessors with Multicycle Functional Units,Exceptions, and Branch PredictionMiroslav N. Velev, Randal E. Bryant - Carnegie Mellon Univ.,Pittsburgh, PA7.2 Assertion Checking by Combined Word-Level ATPG and Modular ArithmeticConstraint-Solving TechniquesRic Chung-Yang Huang, Kwang-Ting (Tim) Cheng - Univ. ofCalifornia, Santa Barbara, CA7.3 Reliable Verification Using SymbolicSimulation with Scalar ValuesChris Wilson, David L. Dill - Stanford Univ., Stanford, CA7.4 Automatic Formal Verification of DSP SoftwareDavid W. Currie - Mentor Graphics Corp., Billerica, MAAlan J. Hu - Univ. of British Columbia, Vancouver, BC, CanadaSreeranga P. Rajan, Masahiro Fujita - Fujitsu Labs. of America,Sunnyvale, CA


NEW TECHNIQUES FORSYNTHESIS AND MAPPINGCHAIR: Leon Stok - IBM Corp., Yorktown Heights, NYORGANIZERS: Jason Cong,

Malgorzata Marek-SadowskaThis session presents progress in synthesis andtechnology mapping, including combined mappingwith gate-decomposition considering area-delaytrade-off, BDD-based logic synthesis, fine-grainedarithmetic optimization in data path synthesis, XOR-based decomposition, and watermarking ofsynthesis solutions.

6.1 Area Control and Search Space Limitationsfor Technology MappingDirk-Jan Jongeneel - Delft Univ. of Tech., Delft, The NetherlandsRobert K. Brayton - Univ. of California, Berkeley, CARalph H.J.M. Otten - Delft Univ. of Tech., Delft, The NetherlandsYosinori Watanabe - Cadence European Labs., Roma, Italy6.2 BDS: A BDD-Based Logic Optimization SystemCongguang Yang, Maciej Ciesielski - Univ. of Massachusetts,Amherst, MAVigyan Singhal - Cadence Berkeley Labs., Berkeley, CA6.3 A Fine-Grained Arithmetic Optimization forHigh-Performance/Low-Power Data Path SynthesisJunhyung Um, Taewhan Kim - Korea Advanced Institute ofScience, Taejon, KoreaC.L. Liu - National Tsing Hua Univ., Hsinchu, Taiwan ROC6.4S Optimal Low Power XOR GateDecompositionHai Zhou - Synopsys, Inc, Mountain View, CAD. F. Wong - Univ. of Texas, Austin, TX6.5S Watermarking while Preserving the CriticalPathSeapahn Meguerdichian, Miodrag Potkonjak - Univ. ofCalifornia, Los Angeles, CA


Tuesday, June 6

10

SSeessssiioonn ROOM: 406AB

TEST ISSUES FOR DEEP-SUBMICRON SYSTEM-ON-CHIPSCHAIR: Janusz Rajski - Mentor Graphics Corp.,

Wilsonville, ORORGANIZERS: Kwang-Ting (Tim) Cheng,

Anand RaghunathanThis session includes two embedded tutorials onimportant emerging issues in manufacturing test.The first presentation covers test challenges andsolutions for core-based SOC designs.Thesecond presentation discusses the impact ofdeep sub-micron technology trends on teststrategies and summarizes recent research onaddressing theses problems.8.1 Embedded Tutorial: System-ChipTest: How will it Impact Your Design?A major challenge in realizing core-based system-on-chip is in adopting and designing-in adequatetest and diagnosis strategies. This embeddedtutorial focuses on the current industrial practices indesigning SOC test. It discusses the challenges intesting deeply embedded cores supplied bydiverse providers, often using different hardwaredescription level and mixed technologies, anddescribes the state-of-the-art practices that addressthese challenges, such as system level test re-useand integrating test for complex system-on-chips.In addition, this tutorial covers the currentstandardization efforts for embedded core testinterface mechanisms.Yervant Zorian - LogicVision, Inc., San Jose, CAErik Jan Marinissen - Philips Research Labs.,Eindhoven, The Netherlands8.2 Embedded Tutorial: TestChallenges for Deep Sub-MicronTechnologiesThe use of deep submicron process technologiespresents several new challenges in the area ofmanufacturing test. While a significant body ofwork has been devoted to identifying andinvestigating design challenges in nanometertechnologies, the impact on test strategies andmethodologies is still not well understood.This embedded tutorial will highlight thechallenges to current test methodologies arisingfrom technology driven trends, and will presentan overview of emerging techniques thataddress deep submicron test challenges.Kwang-Ting (Tim) Cheng - Univ. of California,Santa Barbara, CASujit Dey - Univ. of California, San Diego, CAMike Rodgers - Intel Corp., Santa Clara, CAKaushik Roy - Purdue Univ., West Lafayette, IN


CLOCK AND POWER GRIDANALYSIS FOR HIGHPERFORMANCE DESIGNSCHAIR: Vivek Tiwari - Intel Corp., Santa Clara,

CAORGANIZERS: Ingrid Verbauwhede,

Mojy ChianHigher levels of integration of modern chips havesignificantly increased the size and complexity of thepower and clocking networks. The first paper in thissession focuses on hierarchical analysis of powernetworks. The second paper demonstrates anefficient reduction method. The third paper presentsa novel approach for fast vector compression for IR-drop analysis. The final two papers analyze theimpact of process variation on clock skew.

9.1 Hierarchical Analysis of PowerDistribution NetworksMin Zhao - Univ. of Minnesota, Minneapolis, MNRajendran V. Panda - Motorola, Inc., Austin, TXSachin S. Sapatnekar - Univ. of Minnesota,Minneapolis, MNTim Edwards, Rajat Chaudhry, David Blaauw -Motorola, Inc., Austin, TX9.2 Fast Power Grid SimulationSani R. Nassif - IBM Austin Research Lab., Austin, TXJoseph N. Kozhaya - Univ. of Illinois, Urbana, IL9.3 Current Signature Compressionfor IR-Drop AnalysisRajat Chaudhry, David Blaauw, Rajendran V.Panda, Tim Edwards - Motorola, Inc., Austin, TX9.4S Impact of Interconnect Variationson the Clock Skew of a GigahertzMicroprocessorYing Liu - Carnegie Mellon Univ., Pittsburgh, PASani R. Nassif - IBM Austin Research Lab., Austin, TXLawrence T. Pileggi, Andrzej J. Strojwas - CarnegieMellon Univ., Pittsburgh, PA9.5S A Methodology for Modeling theEffects of Systematic Within-DieInterconnect and Device Variation onCircuit PerformanceVikas Mehrotra, Shiou Lin Sam, Duane Boning,Anantha Chandrakasan - Massachusetts Institute ofTechnology, Cambridge, MARakesh Vallishayee - PDF Solutions, San Jose, CASani R. Nassif - IBM Austin Research Lab., Austin, TX


PANEL: DESIGNCLOSURE: HOPE OR HYPE?CHAIR: Kurt Keutzer - Univ. of California,

Berkeley, CAORGANIZERS: Andrew Kahng,

Gloria Nichols, VicKulkarni

It’s been one year since RichardGoering told us that the EDA RTL-to-GDSII world was about to change.What have we learned? Who’swinning, and who’s not? This panel,consisting of the leading large andupcoming players in this space, willdeliver concrete data to differentiateleading approaches to achievingdesign closure. Does the solution lie inraw speed and RTL optimization, withthe synthesis-place-route back end justa commodity? Does the solution lie innew metrics for design convergence,and symmetric multiprocessingplatforms for efficiency? Does thesolution lie in a holistic, unifiedarchitecture of data model and tools?Or does the solution lie in extensionsand unifications of existing production-proven logic, timing, and layoutoptimization technologies? A hard-hitting panel session will reveal theanswers!

PANELISTS:Raul Camposano - Synopsys, Inc.,Mountain View, CAJacob Greidinger - Aristo Technology,Cupertino, CAPatrick Groeneveld - Magma DesignAutomation, Cupertino, CAMichael Jackson - Avant! Corp., Fremont,CALarry Pileggi - Monterey Design Systems,Sunnyvale, CALou Scheffer - Cadence Design Systems,Inc., San Jose, CAMartin Walker - Frequency Technology,Santa Clara, CA

technicalprogram

Tuesday, June 6

11

4:30to

6:00

chnical program


VERIFICATION AND DEBUGGINGMETHODOLOGIESCHAIR: Ivo Bolsens - IMEC, Leuven, BelgiumORGANIZER: Ivo BolsensThe first two papers present case studies onthe application of formal verif icationtechniques to an on-chip bus arbiter core anditerative circuits in microprocessors. The lastpaper talks about a technique to supportincremental FPGA based emulation.

12.1 Formal Verification of an IBM Coreconnect™Processor Local Bus Arbiter CoreAmit Goel - Carnegie Mellon Univ., Pittsburgh, PAWilliam Lee - IBM Microelectronics, Research Triangle Park, NC12.2 Formal Verification of Iterative Algorithms inMicroprocessorsMark D. Aagaard, Robert B. Jones, Roope Kaivola, KatherineKohatsu, Carl-Johan H. Seger - Intel Corp., Hillsboro, OR12.3 Efficient Error Detection, Localization, andCorrection for FPGA-Based DebuggingJohn Lach, William H. Mangione-Smith, Miodrag Potkonjak -Univ. of California, Los Angeles, CA


ALGORITHMS FOR RFSIMULATION AND MODEL REDUCTIONCHAIR: Alan Mantooth - Univ. of Arkansas, Fayetteville, ARORGANIZERS: Hidetoshi Onodera, Alan MantoothA multi-interval Chebyshev method is described thatdiscretizes the circuit equations by dividing thesimulation domain into intervals and represents thesolution using Chebyshev polynomials. This methodis applied to nonlinear RF circuits. The remainingtwo papers involve model reduction. The first paperis on weakly nonlinear systems, which is ageneralization of popular linear techniques. Thesecond paper describes a novel driving point modelfor on-chip interconnect including inductance.

11.1A Multi-Interval Chebyshev CollocationMethod for Efficient High-Accuracy RF CircuitSimulationBaolin Yang, Joel R. Phillips - Cadence Design Systems, Inc. San Jose, CA11.2 Projection Frameworks for Model Reductionof Weakly Nonlinear SystemsJoel R. Phillips - Cadence Design Systems Inc., San Jose, CA11.3 A Realizable Driving Point Model for On-Chip Interconnect with InductanceChandramouli Kashyap, Byron Krauter - IBM Corp., Austin, TX


§




Tuesday, June 6

12


DESIGN METHODS FOREMERGINGTECHNOLOGIESCHAIR: Ingrid Verbauwhede - Univ. of

California, Los Angeles, CAORGANIZERS: Tadahiro Kuroda,

Telle WhitneyThe future IC will include very differenttechnologies. This session includespapers that suggest some of them. The first paper describes designimplementation and performanceevaluation of 3-D IC’s. The secondpaper gives a strategy to design andmodel optical interconnects. The thirdpaper describes the design of aquantum DOT based microprocessor.

13.1 Multiple SI Layer ICs: Motivation,Performance Analysis, and DesignImplicationsShukri Souri, Kaustav Banerjee - StanfordUniv., Stanford, CAAmit Mehrotra - Univ. of Illinois, Urbana, ILKrishna C. Saraswat - Stanford Univ., Stanford, CA13.2 High-Level Model of a WDMA Passive Optical Bus for a Reconfigurable MultiprocessorSystemVince Boros - Univ. of Queensland, St Lucia, Australia13.3 DESIGN CONTEST: A Design ofand Design Tools for a Novel QuantumDot Based MicroprocessorMichael Niemier, Michael Kontz, Peter Kogge -Univ. of Notre Dame, Notre Dame, IN


SIGNAL INTEGRITYCHAIR: Luis Miguel Silveira - INESC/IST,

Lisboa, PortugalORGANIZERS: Joel Phillips,

Lou SchefferControlling noise on signals is of criticalimportance in deep submicron chips.The first paper describes a tool and flowfor noise analysis and control. Thesecond and third papers describe theextensions needed for SOI and dynamiclogic. The fourth paper contains a newapproach to reduced models intended tomake multiport analysis faster withoutsacrificing too much accuracy.

14.1 Clarinet: A Noise Analysis Toolfor Deep-Submicron DesignRafi Levy - Motorola, Tel Aviv, IsraelDavid Blaauw - Motorola, Austin, TXGabi Braca - Motorola, Tel Aviv, IsraelAurobindo Dasgupta - Motorola, Austin, TX

Amir Grinshpon - Motorola, Tel Aviv, IsraelChanhee Oh - Motorola, Austin, TXBoaz Orshav - Motorola, Tel Aviv, IsraelSupamas Sirichotiyakul, Vladimir Zolotov -Motorola, Austin, TX14.2S Static Noise Analysis for DigitalIntegrated Circuits in Partially-DepletedSilicon-on-Insulator TechnologyKenneth L. Shepard, Dae-Jin Kim - ColumbiaUniv., New York, NY14.3S Dynamic Noise Analysis inPrecharge-Evaluate CircuitsDinesh Somasekhar, Seung Hoon Choi, KaushikRoy - Purdue Univ., West Lafayette, INYibin Ye, Vivek De - Intel Corp., Hillsboro, OR14.4 Extended Krylov SubspaceMethod for Reduced Order Analysis ofLinear Circuits with Multiple SourcesTuyen V. Nguyen - IBM Austin Research Lab.,Austin, TXJanet M. L. Wang - Univ. of California, Berkeley, CA


PANEL: EDAMEETS .COM: HOW E-SERVICES WILLCHANGE THE EDABUSINESS MODELCHAIR: Jennifer Smith -

Dain Rauscher Wessels, SanFrancisco, CA

ORGANIZERS: Bill Alexander,Andrew Kahng

The skyrocketing complexities of SOCdesign have led to such design bottlenecksas iterations, poor scaling of tools, andinadequate computational power ofdesktop workstations and servers. At thesame time, many organizations face longcapital budgeting cycles for new hardwareand software, and increased total cost ofownership (software, maintenance,integration, training, etc.) for their designcapability. This panel addresses the "dot.com" phenomenon and its associatedtechnology and infrastructure -- e-services-- which offer the promise of new designcapabilities for chip designers and newbusiness models for EDA companies.Issues include (1) for EDA, how will e-services transform sales channels, thepush to interoperability, or how customerneeds are addressed? (2) for ASICvendors, will e-services change how endusers design, and how vendors deploytheir services? (3) for e-services providersand investors, what's real, what's themarket, and how does this affect valuationsand business strategy?

PANELISTS:Jacques Benkoski - Monterey DesignSystems, Sunnyvale, CADavid Dick - Fujitsu Microelectronics, SanJose, CAAdriaan Ligtenberg - Cadence DesignSystems, Inc., San Jose, CAMike Schuh - Foundation Capital, Palo Alto, CAGreg Spirakis - Intel Corp., Santa Clara, CABruce Toal - Hewlett-Packard Co.,Richardson, TX

technicalprogram

Wednesday, June 7

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chnical program




LOGIC/PHYSICAL CO-DESIGNCHAIR: Massoud Pedram - Univ. of Southern California, Los

Angeles, CAORGANIZERS: Jason Cong,

Malgorzata Marek-SadowskaThis session presents novel techniques that linklogical and physical designs. The first paperpresents and efficient technique for performance-driven circuit partitioning with retiming to minimizeglobal interconnect delays. The second paperproposes an interesting concept called the crosstalkimmunity set in the logic domain which can helpnoise-avoidance layout. The third paper exploresthe use of functional symmetry in post-layoutoptimization. The last paper presents a fastincremental FPGA mapping algorithm whichsupports an efficient iterative design methodology.

17.1 Performance Driven Multi-Level andMultiway Partitioning with RetimingJason Cong, Sung Kyu Lim - Univ. of California, Los Angeles, CAChang Wu - Aplus Design Technologies, Inc., Los Angeles, CA17.2 Domino Logic Synthesis MinimizingCrosstalkKi-Wook Kim - Univ. of Illinois, Urbana, ILUnni K. Narayanan - Intel Corp., Santa Clara, CASung-Mo Kang - Univ. of Illinois, Urbana, IL17.3S Fast Post-Placement Rewiring Using EasilyDetectable Functional SymmetriesChih-Wei (Jim) Chang - Univ. of California, Santa Barbara, CAChung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CAPeter R. Suaris - Mentor Graphics Corp., Wilsonville, ORMalgorzata Marek-Sadowska - Univ. of California, Santa Barbara, CA17.4S Depth Optimal Incremental Mapping forField Programmable Gate ArraysJason Cong - Univ. of California, Los Angeles, CAHui Huang - Stanford Univ., Stanford, CA


TIMING ANALYSIS ANDVERIFICATIONCHAIR: Hidetoshi Onodera - Kyoto Univ.,

Kyoto, JapanORGANIZERS: Srinivas Devadas, Hidetoshi OnoderaThe first paper shows a symbolic simulation methodfor transister-level simulation. The second paperpresents a novel dynamic delay model to take intoaccount capacitive coupling, while the next papertakes into account coupling effects during timinganalysis. The last paper presents an algorithm toremove false paths in a timing graph model.

16.1 Symbolic Timing Simulation Using ClusterSchedulingClayton B. McDonald, Randal E. Bryant - Carnegie MellonUniv., Pittsburgh, PA16.2 Critical Path Analysis Using a DynamicallyBounded Delay ModelSoha Hassoun - Tufts Univ., Medford, MA16.3S TACO: Timing Analysis with CouplingRavishankar Arunachalam - Carnegie Mellon Univ.,Pittsburgh, PAKarthik Rajagopal - Intel Corp., Santa Clara, CALawrence T. Pileggi - Carnegie Mellon Univ., Pittsburgh, PA16.4S Removing User-Specified False Paths fromTiming GraphsRajendran V. Panda, David Blaauw - Motorola, Inc., Austin, TX


* Please be advised that the two Keynotes and some of the Technical Sessions will be video taped duringthe conference.

Wednesday, June 7

14


POWER ANALYSIS ANDOPTIMIZATION FOREMBEDDED SOFTWARECHAIR: Diana Marculescu - Carnegie Mellon

Univ, Pittsburgh, PA.ORGANIZERS: John Glossner,

Luciano LavagnoThis session deals with several levels at whichthe problem of software power consumptioncan be handled. The first paper discusses howbus and memory activity can be minimized bycompressing the code. The next paperdiscusses how part of the data cache can behardwired and optimized for power. The nexttwo papers deal with compiler optimizations.Finally the impact of the real-time operatingsystem is discussed, consideringcommunication and scheduling primitives.18.1 Code Compression for LowPower Embedded System DesignHaris Lekatsas - Princeton Univ., Princeton, NJJoerg Henkel - NEC USA, C&C Research Labs.,Princeton, NJWayne Wolf - Princeton Univ., Princeton, NJ18.2S Synthesis of Application-SpecificMemories for Power Optimization inEmbedded SystemsLuca Benini - Univ. of Bologna, Bologna, ItalyAlberto Macii, Enrico Macii, Massimo Poncino -Politecnico di Torino, Torino, Italy18.3S Influence of CompilerOptimizations on System PowerMahmut Kandemir, Vijaykrishnan Narayanan,Mary Jane Irwin, Wu Ye - Penn State Univ.,University Park, PA18.4S Power Minimization Derived fromArchitectural-Usage of VLIWProcessorsCatherine H. Gebotys - Univ. of Waterloo,Waterloo, ON, CanadaRobert Gebotys - Wilfrid Laurier Univ.,Waterloo, ON, CanadaShanila Wiratunga - Univ. of Waterloo, Waterloo, ON, Canada18.5S Power Analysis of EmbeddedOperating SystemsRobert Dick - Princeton Univ., Princeton, NJGanesh Lakshminarayana, Anand Raghunathan - NECUSA, C&C Research Labs., Princeton, NJNiraj K. Jha - Princeton Univ., Princeton, NJ


EMBEDDEDCOMPILATIONTECHNIQUESCHAIR: John Glossner - IBM Corp., Yorktown

Heights, NYORGANIZERS: Kees Vissers,

Luciano LavagnoThis session explores compilationtechniques for embedded systems.Memory latency is an important issue. Acompiler that reorders code to hidememory latency for DSP and multimediaapplications is discussed. The secondpaper shows how to compile a languagewith concurrency and timing constraintsinto fast sequential code. Two shorterpapers discuss minimizing memorybandwidth in telecom applications andusing compilers to predict theperformance of a program as an aid forhand-optimization.

19.1 Memory Aware Compilationthrough Accurate Timing ExtractionPeter Grun, Nikil D. Dutt, Alexandru Nicolau -Univ. of California, Irvine, CA19.2 Compiling Esterel intoSequential CodeStephen A. Edwards - Synopsys, Inc.,Mountain View, CA19.3S Interactive Algorithms forMinimizing Memory Bandwidth in HighThroughput Telecom and MultimediaOmnes Thierry - IMEC VZW - Desics, Leuven,Belgium19.4S Predicting Performance Potentialof Modern DSPsNaji S. Ghazal, A. Richard Newton, Jan M.Rabaey - Univ. of California, Berkeley, CA

SSeessssiioonn 2200Room: ROOM: 403

PANEL: FUTURESYSTEMS-ON-CHIP:SOFTWARE ORHARDWARE DESIGN? CHAIR: Brian Dipert - EDN,

Sacramento, CAORGANIZERS: Shishpal Rawat,

Sylvia Tam Advances in device technology have led toan era where entire systems can beimplemented on a single component,commonly referred to as system-on-chip.With shrinking product life cycles placingsevere time to market demands onmanufacturers, coupled with their need toquickly change a product's feature set toaddress evolving customer requirements,programmability will emerge as a corner-stone for all chips implemented in thefuture. The Internet, communications,consumer electronics, and computingmarkets are first to take advantage ofsystem-on-chip technology. What are thebenefits of programmability to these andother markets and are there potentialpitfalls? What architectures andprogrammability (or reconfigurability) aregoing to be the likely winners and at whatcost? Are these architectures likely toconverge or diverge? The panelists willdebate the merits of their existingapproaches and how they are likely to beshaped in the future.

PANELISTS:Barry Britton - Lucent Technologies, Allentown,PABob Broderson - Univ. of California, Berkeley,CABob Colwell - Intel Corp., Hillsboro, ORBrian Dipert - EDN Magazine, Sacramento, CABill Harris - Cisco Systems, Research TrianglePark, NCShishpal Rawat - Intel Corp., Folsom, CAChris Rowen - Tensilica, Santa Clara, CASylvia Tam -Triscend Corp., Mountain View, CADanesh Tavana -Triscend Corp., MountainView, CA

Wednesday, June 7

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EEmmbbeeddddeedd SSyysstteemmss PPlleennaarryy PPaanneellROOM: Concourse Hall

PANEL: EMBEDDED SYSTEMS DESIGN IN THE NEWMILLENNIUMCHAIR: A. Richard Newton, Univ. of California, Berkeley, CAORGANIZER: Randolph E. Harr

As we turn the corner into the new century, design is increasingly focused on single integrated circuit implementationsof complete systems. Similar to alchemy in the middle ages, the design of a complex system onto an IC is an art andpossibly an illusion understood by a very few. It is a complex search for an optimal answer which requiresunderstanding the application, the system domain, digital function and control, and the fundamentals of circuits and ICfabrication technology. Due to the complexity of standards and processing, no one company understands or owns allof the needed technologies.

This plenary panel draws on leaders from companies that are successfully addressing embedded system designproblems in the new millennium. The panelists will discuss what they perceive as the biggest problems today and downthe road, and outline solutions they will have a part in bringing about. They will collectively address the challenges ofauthoring and integrating major components such as microprocessors, memory, custom digital logic and software intoa single design. Questions that arise in the design of complex embedded systems are:

• How does one refine an application problem to a solution in the face of IC technology limitations? Are there thatmany tall, thin designers or are they not really needed?

• Do they face the same DSM issues as custom designers: problems induced by the physics of the sub-micronstructures and by the shear number of components?

• How does one trade-off the power savings and performance gains of custom hardware with the flexibility,reusability, and time-to-market advantages of programmable solutions?

• Will growing design cost and shrinking time to market and market lifetime windows force everything to beimplemented on a reusable architectural platform?

• Can anything significant we have learned from board/subsystem design be carried down to embedded systemon a chip design?

• How do we achieve and exploit the most transistors? Homogeneous parallelism or heterogeneous 'board-on-a-chip'? Does it matter?

The group will compare the challenges they have faced in implementing embedded systems as well as the solutionsthat have come to fruition. They will consider whether complex embedded system-on-a-chip design is the dawn ofa new industry, the natural progression of the existing semiconductor integrated circuit market, or the seeminglyunreachable goal of turning lead into gold.

PANEL MEMBERS:

Tudor Brown - ARM Ltd., Cambridge, UKSönke Mehrgardt - Infineon Technologies AG, Munich, GermanyWalden C. Rhines - Mentor Graphics Corp., Wilsonville, ORHenry Samueli - Broadcom Corp., Irvine, CAGeoff Tate - Rambus Inc., Mountain View, CA

BiographiesWednesday, June 7

16

Tudor Brown

Tudor Brown has been dedicated to ARM developments since 1984,leading several CPU and system designs in that time. He hasmanaged the development team since 1991 and been CTO since1997. His early career included industrial control, Ethernet andgraphics controllers; bringing together analog electronics andcomputer engineering. Mr. Brown graduated in Electrical Sciencesfrom Cambridge University in 1979.

Sönke Mehrgardt

Dr. Sönke Mehrgardt was elected to the Management Board ofInfineon Technologies in April 1999, and is Chief TechnologyOfficer and Executive Vice President. He was previously Presidentof Signal Processing and Control and President of ConsumerElectronics ICs in the Siemens Semiconductor Group. After tenyears at ITT-Semiconductor, Dr. Mehrgardt joined Siemens in1993. He holds an MA in physics and a PhD in natural sciencesfrom the University of Goettingen, and was Assistant Professor atthe university for nine years.

Richard Newton

A. Richard Newton is Department Chair and Professor of ElectricalEngineering and Computer Sciences at the University of Californiaat Berkeley, and Director of the multi-university MARCO/DARPAGigascale Silicon Research Center. He has helped to foundseveral design technology companies, including Cadence DesignSystems, Synopsys, and Simplex Solutions, and is also a venturepartner with the high-technology Mayfield venture partnership.

Walden C. Rhines

Walden C. Rhines is President and CEO of Mentor Graphics. Hejoined Mentor in 1993 from Texas Instruments, where he wasExecutive Vice President and managed all parts of itssemiconductor and computer systems businesses. He is ViceChairman of the Electronic Design Automation Consortium and onthe board of SEMI/SEMATECH. Dr. Rhines received a BSE fromthe University of Michigan, an MS and PhD from StanfordUniversity, an MBA from Southern Methodist University and anHonorary Doctor of Technology degree from Nottingham TrentUniversity.

Henry Samueli

Henry Samueli co-founded Broadcom Corporation in 1991. AsCo-Chairman and Chief Technical Officer of the company, he isresponsible for all research and development activities. Dr.

Samueli also co-founded PairGain Technologies in 1988 andserved as its Chief Scientist. He was previously Professor ofElectrical Engineering at UCLA and supervised advancedresearch programs in broadband communications circuits, andheld engineering management positions at TRW. Dr. Samuelireceived BS, MS, and PhD degrees in electrical engineering fromUCLA.

Geoff Tate

Geoff Tate has been Chief Executive Officer of Rambus Inc. sinceMay 1990; and is a member of the Rambus Board of Directors.From 1979 to 1990, he held various executive positions atAdvanced Micro Devices, including Senior Vice President of theMicroprocessor and Logic Group. He received a Bachelor inComputer Science from University of Alberta and an MBA fromHarvard University.

technicalprogram

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COMBINED GLOBAL ROUTING,BUFFERING AND WIRESIZINGCHAIR: Patrick Groeneveld - Magma Design Automation,

Inc., Cupertino, CAORGANIZERS: Lou Scheffer, Patrick GroeneveldThis session deals with routing long wires duringtop-level routing on the chip. To optimize delay,buffers must be inserted. A problem is that thesebuffers cannot be placed as arbitrary locations, butonly in specific areas. The papers provide varioussolutions to this problem. The last paper deals withcombined routing and wiresizing.

22.1 A Fast Algorithm for Context-Aware BufferInsertionAshok Jagannathan, Sung-Woo Hur, John Lillis - Univ. ofIllinois, Chicago, IL22.2 Maze Routing with Buffer Insertion andWiresizingMinghorng Lai, D.F. Wong - Univ. of Texas, Austin, TX22.3 Routing Tree Construction under FixedBuffer LocationsJason Cong, Xin Yuan - Univ. of California, Los Angeles, CA22.4 A Current Driven Routing and VerificationMethodology for Analog ApplicationsThorsten Adler - Infineon Technologies AG, Munich, GermanyLars Hedrich, Hiltrud Brocke, Erich Barke - Univ. of Hanover,Hanover, Germany


NEW TECHNIQUES IN POWERESTIMATION ANDPERFORMANCE IMPROVEMENTCHAIR: Timothy Kam - Intel Corp., Hillsboro, ORORGANIZERS: Luciano Lavagno, Timothy KamThe first three papers present new techniques inpower estimation. The fourth paper proposespipelined FSMs. The last paper discusses analysisand optimization techniques to improveperformance of system design.

21.1 The Design and Use of Simplepower: A Cycle-Accurate Energy Estimation ToolWu Ye, Vijaykrishnan Narayanan, Mahmut Kandemir, MaryJane Irwin - Penn State Univ., University Park, PA21.2 An Instruction-Level Functionality-BasedEnergy Estimation Model for 32-bitsMicroprocessorsCarlo Brandolese, William Fornaciari, Fabio Salice, DonatellaSciuto - Politecnico di Milano, Milano, Italy21.3S Dynamic Power Management of ComplexSystems Using Generalized Stochastic Petri NetsQinru Qiu, Qing Wu, Massoud Pedram - Univ. of SouthernCalifornia, Los Angeles, CA21.4S Wave-Steering One-Hot Encoded FSMsLuca Macchiarulo, Malgorzata Marek-Sadowska - Univ. ofCalifornia, Santa Barbara, CA21.5 Performance Analysis and Optimization ofLatency Insensitive SystemsLuca P. Carloni, Alberto L. Sangiovanni-Vincentelli - Univ. ofCalifornia, Berkeley, CA


Wednesday, June 7

18

SSeessssiioonn 2233Room: ROOM: 406AB

ADVANCES IN SYSTEMMODELING ANDSYNTHESISCHAIR: Rajesh K. Gupta - Univ. of California,

Irvine, CAORGANIZERS: Randolph E. Harr,

Donatella SciutoThe session presents different approaches to system levelmodeling, synthesis, and optimization. The first deals witha new base model of representation for system designs,while the second considers system-level modeling fromthe embedded OS perspective. The next two papersintroduce different aspects of the Espirit/OMI Cosy Project.The fifth paper shows a task scheduling algorithm basedon Peri Nets, while the last one considers partitioned cacheto improve the performance of embedded applications.

23.1 ACodesign Virtual Machine forHierarchical, Balanced Hardware/Software System ModelingJoann Paul, Simon Peffers, Donald E. Thomas -Carnegie Mellon Univ., Pittsburgh, PA23.2 An Operating System Approach toSystem Level DesignDirk Desmet, Diederik Verkest, Hugo De Man - IMEC,Leuven, Belgium23.3S YAPI: Application Modeling forSignal Processing SystemsErwin de Kock, Gerben Essink, Wim Smits, Pieter van derWolf, Jean-Yves Brunel, Wido Kruijtzer - Philips Research Labs.,Eindhoven, The NetherlandsPaul Lieverse - Delft Univ., Delft, The NetherlandsKees A. Vissers - Univ. of California, Berkeley, CA23.4S Cosy Communication IP’sJean-Yves Brunel, Wido Kruijtzer, Arjan Kenter -Philips Research Labs., Eindhoven, The NetherlandsFrederic Petrot - Univ. Pierre et Marie CurieLaurent Pasquier - Philips Research Labs., Paris, FranceErwin de Kock, Wim Swits - Philips Research Labs.,Eindhoven, The Netherlands23.5S Synthesis and Optimization ofCoordination Controllers for DistributedEmbedded SystemsPai H. Chou - Univ. of California, Irvine, CAGaetano Borriello - Univ. of Washington, Seattle, WA23.6S Application-Specific MemoryManagement for Embedded Systems UsingSoftware-Controlled CachesDerek Chiou, Prabhat Jain, Srinivas Devadas, LarryRudolph - Massachusetts Institute of Technology,Cambridge, MA


DESIGNING SYSTEMSON A CHIPCHAIR: Randolph E. Harr - Synopsys, Inc.,

Mountain View, CAORGANIZERS: Kurt Keutzer,

Asawaree KalavadeThis session begins with a tutorialoverview of tools and methodologies beingput in place at IBM to support a core-based approach to the design of systems-on-a-chip. Topics covered will includeinterconnect and communication, coreimplementation, interface synthesis, andverification. The remaining two papers willgo into detail on methodologies for design verification and manufacture test respectively.

24.1 EMBEDDED TUTORIAL:Designing Systems-on-chip Using CoresReinaldo Bergamaschi - IBM Corp., YorktownHeights, NYWilliam Lee - IBM Microelectronics, ResearchTriangle Park, NC24.2 Verification of ConfigurableProcessor CoresMarines Puig-Medina, Gulbin Ezer, PavlosKonas - Tensilica, Santa Clara, CA24.3 Design of System-on-a-Chip TestAccess Architectures under Place-and-Route and Power ConstraintsKrishnendu Chakrabarty - Duke Univ.,Durham, NC


PANEL: THE FUTURE OFSYSTEM DESIGNLANGUAGES CHAIR: Richard Goering - EE Times, Felton,

CAORGANIZERS: Nanette Collins,

Clifford E.Cummings, Richard Goering

Verilog HDL was a breakthrough for thehardware design community in 1986.Over the years, the methodology basedon the Verilog HDL has been extendedwith utilities and enhancements. With0.25- and 0.18- processes enabling asystem to be packed onto a singleintegrated circuit, design problems havesurfaced that no one could havepredicted 13 years ago. As a result,several new design language proposalshave been introduced since the lastDesign Automation Conference, allclaiming to aid system-on-chip (SOC)design. Several claim to improve thedesigner’s ability to efficiently create,implement, and verify SOC designs fromarchitectural specification throughfunctional implementation. The panel,comprised of experienced designersand representatives of organizationssubmitting design language proposals,will debate the various proposals andwill try to identify what future trend willaccelerate system design.

PANELISTS:Clifford E. Cummings - Sunburst Design,Beaverton, ORSimon Davidmann - Co-Design Automation,San Jose, CAJoachim Kunkel - Synopsys, Inc., MountainView, CAOz Levia - Improv, Santa Clara, CAJohn Sanguinetti - CynApps, Santa Clara,CASteven E. Schulz - Texas Instruments, Dallas,TX

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FLOORPLANNING &PLACEMENTCHAIR: Louis Scheffer - Cadence Design Systems, Inc.,

San Jose, CAORGANIZERS: Patrick Groeneveld, Lou SchefferTwo critical tasks in chip design are the constructionof an appropriate floorplan and the detailedplacement of each component. This session startswith a new data structure for floorplanning, followedby a new technique for enforcing symmetryconstraints and a new aspect ratio optimization. Thelast two papers implement detailed placement bypartitioning, while trying to control both timing androuting congestion.

27.1 B*-Trees: A New Representation for Non-Slicing FloorplansYun-Chih Chang, Yao-Wen Chang, Guang-Ming Wu, Su-WeiWu - National Chiao Tung Univ., Hsinchu, Taiwan, ROC27.2S Block Placement with Symmetry ConstraintsBased on the O-Tree Non-Slicing RepresentationYingxin Pang - Univ. of California at San Diego, La Jolla, CAFlorin Balasa, Koen Lampaert - Conexant Systems, Inc., Newport Beach, CAChung-Kuan Cheng - Univ. of California at San Diego, La Jolla, CA27.3S Floorplan Sizing by Linear ProgrammingApproximationPinhong Chen, Ernest S. Kuh - Univ. of California, Berkeley, CA27.4S Timing-Driven Placement Based onPartitioning with Dynamic Cut-Net ControlShihg-Liang Ou, Massoud Pedram - Univ. of SouthernCalifornia, Los Angeles, CA27.5S Can Recursive Bisection Alone ProduceRoutable Placements?Andrew E. Caldwell, Andrew B. Kahng, Igor L. Markov - Univ.of California, Los Angeles, CA


MIXED SIGNAL DESIGN ANDANALYSISCHAIR: Mojy C. Chian - Conexant Systems Inc., Newport

Beach, CAORGANIZERS: Ingrid Verbauwhede, David BlaauwWith the explosion of the telecommunication market,there is an over increasing trend to integrate morefunctionality on one single chip. The papers in thissession demonstrate enabling technologies insupport of this trend. The first paper presents anefficient simulation techniques for digital telecomtransceivers. The second paper demonstrates acell-based techniques for substrate and powersupply noise analysis. The third paper reports on thedesign methodology and trade-offs for theimplementation of a 14-bit D/A Converter.

26.1 A Methodology for Efficient High-LevelDataflow Simulation of Mixed-Signal Front-Ends ofDigital Telecom TransceiversGerd Vandersteen, Piet Wambacq - IMEC, Leuven, BelgiumYves Rolain - VUB, Brussels, BelgiumPetr Dobrovolny, Stephane Donnay, Marc Engels, Ivo Bolsens -IMEC, Leuven, Belgium26.2 High-Level Simulation of Substrate NoiseGeneration Including Power Supply NoiseCouplingMarc van Heijningen, Mustafa Badaroglu, Stephane Donnay,Marc Engels, Ivo Bolsens - IMEC, Leuven, Belgium26.3 DESIGN CONTEST: Systematic Design of a 14-bit 150-MS/S CMOS Current-Steering D/AConverterGeert Van der Plas, Jan Vandenbussche, Walter Daems, AnneVan Den Bosch, Georges Gielen, Michiel Steyaert, Willy Sansen -Katholieke Univ., Leuven, Belgium





Wednesday, June 7

20


SYSTEM LEVELSCHEDULINGCHAIR: Erwin de Kock - Philips Research

Labs., Eindhoven, The NetherlandsORGANIZERS: Kees Vissers, John GlossnerAn important part of system software isthe task-scheduling approach. In thissession the subject of finding prioritiesunder real-time constraints is addressed,in the context of a real-time operatingsystem. Furthermore a novel techniquefor addressing the scheduling problemsat this level will be presented. Also anapproach is presented that indicateswhere reductions should be made inexecution times of tasks.

28.1 Task Scheduling with RTConstraintsMarco di Natale - Universita’ Degli Studi diPisa, Pisa, ItalyAlberto L. Sangiovanni - Vincentelli - Univ. ofCalifornia, Berkeley, CAFelice Balarin - Cadence Berkeley Labs., Berkeley, CA28.2 Task Generation and Compile-Time Scheduling for Mixed Data-Control Embedded SoftwareJordi Cortadella - Univ. Politecnica de Catalunya,Barcelona, SpainAlex Kondratyev - Theseus Logic, Sunnyvale, CALuciano Lavagno - Univ. di Udine, Udine, ItalyMarc Massot - Univ. de Girona, Girona, SpainSandra Moral - Univ. Politecnica de Cataluny,Barcelona, SpainClaudio Passerone - Politecnico di Torino, Torino, ItalyYosinori Watanabe - Cadence Berkeley Labs.,Berkeley, CAAlberto L. Sangiovanni-Vincentelli - Univ. ofCalifornia, Berkeley, CA28.3 Schedulability-DrivenPerformance Analysis of Multiple ModeEmbedded Real-Time SystemsYoungsoo Shin - Univ. of Tokyo, Tokyo, JapanDaehong Kim, Kiyoung Choi - Seoul NationalUniv., Seoul, Korea


ARCHITECTURES FOREMBEDDED SYSTEMSCHAIR: Kees A. Vissers - Univ. of California,

Berkeley, CAORGANIZERS: Donatella Scuito,

Rajesh GuptaSelection of an appropriate architectureis an important design decision forembedded systems. Papers in thissession address architectural choicesand organization of embedded systemsusing reconfigurable hardware. The lastpaper proposes a new technique fordesign of communication functions forembedded systems on a chip.

29.1 System Design of ActiveBasestations Based on DynamicallyReconfigurable HardwareAthanassios Boulis, Mani B. Srivastava - Univ.of California, Los Angeles, CA29.2 Hardware-Software Co-Design ofEmbedded ReconfigurableArchitecturesYanbing Li - Synopsys, Inc., Mountain View, CATim Callahan - Univ. of California, Berkeley, CAErvan Darnell - Silicon Spice, Mountain View, CARandolph E. Harr, Uday Kurkure, Jon Stockwood -Synopsys, Inc., Mountain View, CA

29.3Communication ArchitectureTuners: A Methodology for the Designof High Performance CommunicationArchitectures for System-on-ChipsKanishka Lahiri - Univ. of California at SanDiego, La Jolla, CAAnand Raghunathan, Lakshminarayana Ganesh -NEC USA, C&C Research Labs, Princeton, NJSujit Dey - Univ. of California at San Diego, La Jolla, CA


PANEL: EMBEDDEDSYSTEMS EDUCATIONCHAIR: Sharad Malik - Princeton Univ.,

Princeton, NJ ORGANIZERS: Sharad Malik,

Jan Rabaey,Asawaree Kalavade

The design and design automation ofembedded systems is rapidly emerging asa research area in its own right. It drawsfrom several traditional areas of studysuch as system specification, modelingand analysis; computer architecture andmicroarchitecture, as well as compilersand operating systems. However, theembedded domain adds some interestingtwists in terms of tighter problemconstraints that demand a fresh look ateven these traditional areas. In addition,there are several emerging EDA areassuch as design reuse and integration ofsystems on a chip that are critical to thestudy of embedded systems. All theseaspects are not typically covered bycomputer engineering and EDA curricula.This panel addresses the challengesassociated with the educational issues inembedded systems design and designautomation. The panelists will examineissues in including embedded systems inuniversity curricula, as well as in setting upresearch programs that are crucial for theeducation of graduate students.The panel of distinguished members haveall grappled with these issues and will sharetheir experiences in setting up variousprograms, as well as point out changes weshould be looking at for the future.

PANELISTS:D.K. Arvind - Univ. of Edinburgh, Edinburgh,UKEdward Lee - Univ. of California, Berkeley, CAPhil Koopman - Carnegie Mellon Univ.,Pittsburgh, PAAlberto L. Sangiovanni-Vincentelli - Univ. ofCalifornia, Berkeley, CAWayne Wolf - Princeton Univ., Princeton, NJ

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HIGH LEVEL SYNTHESIS FORDSPs: DATA INTENSIVEAPPLICATIONSCHAIR: Nikil D. Dutt - Univ. of California, Irvine, CAORGANIZERS: Rajesh K. Gupta,

Kazutoshi WakabayashiPapers in this session address synthesis andoptimization techniques for DSP and memoryintensive applications. The first and the last papersaddress memory organization to minimize latencyand bandwidth effects. The second paper proposesan improvement over latency bounding techniquesfor DFGs. The third paper in this session looks atinterface generation from data flow graphs.

32.1 Optimal Two Level Partitioning and LoopScheduling for Hiding Memory Latency for DSPApplicationsZhong Wang, Michael Kirkpatrick, Edwin Hsing-Mean Sha -Univ. of Notre Dame, Notre Dame, IN32.2 On Lower Bounds for Scheduling Problemsin High-Level SynthesisM. Narasimhan, J. Ramanujam - Louisiana State Univ., Baton Rouge, LA32.3S Efficient Building Block Based RTL-HDLCode Generation from Synchronous Data-FlowGraphsJens Horstmannshoff, Heinrich Meyr- Integrated SignalProcessing System, RWTH Aachen, Germany32.4S System-Level Data Format ExplorationforDynamically Allocated Data StructuresPeeter Ellervee - KTH, Kista, SwedenMiguel Miranda, Francky Catthoor - IMEC, Leuven, BelgiumAhmed Hemani - KTH, Kista, Sweden


INTERCONNECT ANALYSISCHAIR: Eric Bracken - Ansoft Corp., Pittsburgh, PAORGANIZERS: Joel Phillips, Alan MantoothThis session features efficient methods for modelinginterconnnect. The first two papers discuss newmodel reduction approaches, the third, closed-formmodels for coupling noise, and the fourth, compactdiscretizations for capacitance extraction.

31.1 Passive Model Order Reduction AlgorithmBased on Chebyshev Expansion of ImpulseResponse of Interconnect NetworksJanet Meiling Wang - Univ. of California, Berkeley, CA31.2 Passive Model Order Reduction of MultiportDistributed InterconnectsEmad Gad, Anestis Dounavis, Michel Nakhla, RamachandraAchar - Carleton Univ., Ottawa, ON, Canada31.3S Predicting Coupled Noise in RC Circuits byMatching 1, 2, and 3 MomentsBernard N. Sheehan - Mentor Graphics Corp., St. Paul, MN31.4S Singularity-Treated Quadrature-EvaluatedMethod of Moments Solver for 3-D Capacitance ExtractionJinsong Zhao - Cadence Design Systems, Inc., San Jose, CA


* Please be advised that the two Keynotes and some of the Technical Sessions will be video taped duringthe conference.

Thursday, June

22


EMBEDDED TUTORIAL:MOSFET MODELING ANDCIRCUIT DESIGN: RE-ESTABLISHING ALOST CONNECTIONCHAIR: Brian Mulvaney - Motorola, Inc.,

Austin, TXORGANIZER: Daniel Foty Amid the blizzard of design-automationtechnologies, the analytical MOSFET models(and their associated model parameter sets)receive scant attention from the designcommunity. However, these models andparameter sets are fundamental to the designprocess, since they represent the critical"communication link" between a design groupand its wafer foundry.The first part of this tutorial will examine thepresent "infrastructure" of MOS modeling forcircuit simulation, with particular emphasis onhow history has played a role at least as largeas that of engineering. The viewpoint will bethat of a circuit design "consumer" of MOSmodels who must make the best possible useof a badly flawed infrastructure. In recentyears, the entire structure of MOS models hasbeen evolving into continually morecomplicated and empirical forms, opening up a"reality gap" between a model's mathematicalstructure and circuit design usage.The second part of this tutorial willdemonstrate the connection betweenMOSFET modeling and a modern approach todesigning analog and digital integrated circuits.A methodology is presented is which permitsMOSFET sizing for optimal bandwidth, optimaldc matching, balanced compromises inbandwidth and dc matching, and othercombinations of circuit performance. Themethodology permits operation anywhere inthe continuum of MOSFET operation throughweak, moderate, and strong inversion. Themethodology is particularly compatible with theEKV MOSFET model, as will be shown.

PRESENTERS:David Binkley - Concorde Microsystems,Knoxville, TNDaniel Foty - Gilgamesh Associates, Fletcher,VT


RECONFIGURABLECOMPUTING SYSTEMSCHAIR: Telle Whitney - Malleable

Technologies, San Jose, CAORGANIZERS: Telle Whitney,

Ingrid VerbauwhedeReconfigurable computing systemsprovide a platform for a vast array ofattractive applications. The sessionopens with a novel FPGA designenvironment. The second paperproposes a metric for FPGA placementand routing. The session closes with acase study of a reconfigurable system.

34.1 Using General-PurposeProgramming Languages for FPGA DesignBrad Hutchings, Brent Nelson - Brigham YoungUniv., Provo, UT34.2 An Architecture-Driven Metric forSimultaneous Placement and GlobalRouting for FPGAsYao-Wen Chang, Yu-Tsang Chang - NationalChiao Tung Univ., Hsinchu, Taiwan ROC34.3 Morphosys: Case Study of aReconfigurable Computing SystemTargeting Multimedia ApplicationsHartej Singh, Guangming Lu, Ming-Hau Lee,Fadi J. Kurdahi, Nader Bagherzadeh - Univ. ofCalifornia, Irvine, CAEliseu Filho - Federal Univ. of Rio de Janei, Rio deJaneiro, BrazilRafael Maestre - Univ. Complutense, Madrid, Spain


PANEL: SURVIVALSTRATEGIES FORMIXED-SIGNALSYSTEMS-ON-CHIPCHAIR: Stephan Ohr, EE Times,

New York, NYORGANIZERS: Rob A. Rutenbar,

Georges GielenMore and more large ASICs requireanalog subsystems to interface to thereal world — to wireless and wirednetworks, to sensors and transducers inembedded applications, to electricallycomplex high-speed interconnect. This isa major problem, since these analogsubsystems break almost everyassumption we know and love aboutdigital systems. With respect to today'slogic-centric CAD flows, analog blocks fitpoorly and abstract badly. What ishappening to help mixed-signal SoCdesigners in this difficult area? And whatcan we hope for here? Analogsynthesis? Mixed-signal IP? Practicalreuse methodologies? Or will wecontinue to design analog the old-fashioned way – one transistor, onepolygon at a time? Our panelists offer amix of widely differing viewpoints on thisimportant question.

PANELISTS:Henry Chang - Cadence Design Systems,Inc., San Jose, CAGeorges Gielen - Katholieke Univ. Leuven,Leuven BelgiumRudolf Koch - Infineon Technologies AG,Munich, GermanyRoy McGuffin - Antrim Design Systems,Scotts Valley, CAK. C. Murphy - Pivotal Technologies,Pasadena, CARob A. Rutenbar - Carnegie Mellon Univ.,Pittsburgh, PA

technicalprogram

Thursday, June

23

10:30to

12:00

chnical program




CORRECTNESS ISSUES IN HIGHLEVEL SYNTHESISCHAIR: Kwang-Ting (Tim) Cheng - Univ. of California, Santa

Barbara, CAORGANIZERS: Kazutoshi Wakabayashi,

Rajesh K. GuptaWith the diffusion of high-level tools into practicaldesigns, designers continue to face problems suchas how to ensure that a high-level synthesis toolgenerates a correct structure after it applies varioustransformations, and to ensure the testability of thesynthesized design. This session explores answersto these questions.

37.1 Optimizing Sequential Verification byRetiming TransformationsGianpiero Cabodi, Stefano Quer - Politecnico di Torino,Torino, ItalyFabio Somenzi - Univ. of Colorado, Boulder, CO37.2 Efficient Methods for Embedded SystemDesign Space ExplorationHarry Hsieh - Univ. of California, Berkeley, CAFelice Balarin - Cadence Berkeley Labs., Berkeley, CALuciano Lavagno - Cadence Design Systems, Inc., Berkeley, CAAlberto L. Sangiovanni-Vincentelli - Univ. of California, Berkeley, CA37.3 Synthesis-for-Testability of Controller-Datapath Pairs that Use Gated ClocksMehrdad Nourani - Univ. of Texas, Richardson, TXJoan E. Carletta - Univ. of Akron, Akron, OHChristos A. Papachristou - Case Western Reserve Univ.,Cleveland, OH


INTELLECTUAL PROPERTYPROTECTION & RE-USECHAIR: Kenji Yoshida - Toshiba Corp.,

Kawasaki, JapanORGANIZERS: Anantha Chandrakasan, Mojy ChianThis session addresses issues in IP protection andreuse methodologies for the modern SoCenvironments. The first two papers discuss forensicengineering and finger printing techniques based ongraph theory approaches. The final two paperspresent HW/SW IP protection and reusemethodologies for web-based designs.

36.1 Forensic Engineering Techniques for VLSICAD ToolsDavid T. Liu, Jennifer L. Wong, Darko Kirovski, Miodrag Potkonjak - Univ. of California, Los Angeles, CA36.2 Fingerprinting Intellectual Property UsingConstraint-AdditionGang Qu, Miodrag Potkonjak - Univ. of California, Los Angeles, CA36.3S Hardware/Software IP ProtectionMarcello Dalpasso - Univ. of Padova, Padova, ItalyAlessandro Bogliolo - Univ. of Ferrara, Ferrara, ItalyLuca Benini - Univ. of Bologna, Bologna, Italy36.4S A Web-CAD Methodology for IP-CoreAnalysis and SimulationAlessandro Fin, Franco Fummi - Univ. di Verona, Verona, Italy


Thursday, June

24


SOC TESTMETHODOLOGIES ANDDEFECT MODELLINGCHAIR: Anand Raghunathan - NEC USA,

C&C Research Labs., Princeton, NJORGANIZERS: Anand Ragunathan,

Kenji YoshidaThe first two papers present HW andSW based self test techniques, targetingrespectively crosstalk and stuck-at faultsin System-on-Chip design. The lastpaper explains the application of fuzzylogic to model defects using a resistivefault model.

38.1 Self-Test Methodology for At-Speed Test of Crosstalk in Chip InterconnectsXiaoliang Bai, Sujit Dey - Univ. of California atSan Diego, La Jolla, CAJanusz Rajski - Mentor Graphics Corp.,Wilsonville, OR38.2 Embedded Hardware andSoftware Self-Testing Methodologiesfor Processor CoresLi Chen, Sujit Dey, Pablo Sanchez, Krishna Sekar,Ying Chen - Univ. of California at San Diego,La Jolla, CA38.3 Modeling and Simulation of RealDefects Using Fuzzy LogicAmir Attarha, Mehrdad Nourani - Univ. of Texas,Richardson, TXCaro Lucas - The Univ. of Tehran, Tehran, Iran


EMBEDDED TUTORIAL:BRIDGING THE GAPBETWEEN FULL CUSTOMAND ASIC DESIGNCHAIR: Bryan D. Ackland - Bell Labs. - Lucent

Technologies, Holmdel, NJORGANIZER: Kurt KeutzerCustom designs manufactured in .25micron processes have routinely exceededspeeds of 600 MHz. where ASIC designsin the same processes may only achieve150 MHz. The first aim of this embeddedtutorial is to identify precisely what factorsare responsible for the gap between ASICand custom performance. Initial studiesindicate that key factors are: preferentialprocessing, use of dynamic logic families,better circuit design, elimination ofguardbanding, and generally betterattention to design at the RTL, gate, andtransistor levels. Each of the participantswill evaluate these aspects and quantifythe contribution of each aspect. Keutzer’stalk will focus on determining the extent towhich new tools and methodologies canclose the performance gap between ASICand custom. Dally’s talk will focus onlooking at new custom design techniques,that promise to continue to keep customdesign performance well ahead of thatattainable by ASIC techniques. Finally thetwo presentations will be critiqued andreviewed by a small panel of designers andCAD tool developers.39.1 Closing the Gap between ASICand Custom: An ASIC PerspectiveKurt Keutzer - Univ. of California, Berkeley, CA39.2 Closing the Gap between ASICand Custom: A Custom PerspectiveWilliam J. Daly - Stanford Univ., Stanford, CA39.3 Comments on Closing the Gapbetween ASIC and CustomMichael Keating - Synopsys, Inc., Mountain View, CAUdi Kra - Silicon Value, Jerusalem, IsraelEarl Killian - Tensilica, Santa Clara, CAMartin Lefebvre - Cadabra Technologies, Santa Clara, CA


PANEL: CASE STUDIES:CHIP DESIGN ON THEBLEEDING EDGECHAIR: John M. Cohn - IBM Corp., Essex

Junction, VTORGANIZER: Rob A. RutenbarOften, the most interestingtools, methodologies, and insightscome from designs that push hard on the"leading edge" of technology -- what thesurvivors commonly call the "bleedingedge" of design. In this session, wecollect three such on-the-edge designs,each done in a different style, eachaimed at a very different market, eachwith its own unique set of challenges andsolutions. The session offers casestudies from an enormous FPGA, amaximally high-end PC graphics engine,and a huge system-on-a-chip for acellular handset. Design leads fromeach design team will share sometechnical strategies, some successstories, and some horror stories in a setof introductory talks. A short panelsession at the end will allow theaudience to ask questions of all thespeakers.

PANELISTS:Luis Aldaz - Philips Semiconductors, SanJose, CAChris Malachowsky - NVIDIA, Santa Clara, CASteve Young - Xilinx, Inc., San Jose, CA

technicalprogram

Thursday, June

25

2:00to

4:00

chnical program




DECISION PROCEDURES FORCAD PROBLEMSCHAIR: Eugene Goldberg - Cadence Design Systems, Inc.,

Berkeley, CAORGANIZERS: Limor Fix, Kurt KeutzerBoolean functions manipulation and booleansatisfiability are fundamental underlying technologyin many EDA applications. A tutorial on SATalgorithms will be presented and new variable orderand partition algorithms for BDDs will be described.

42.1 EMBEDDED TUTORIAL: BooleanSatisfiability Models and Algorithms for EDAJoao P. Marques Silva - Technical Univ. of Lisbon, Lisboa, PortugalKarem Sakallah - Univ. of Michigan, Ann Arbor, MI42.2 Analysis of Composition Complexity, andHow to Obtain Smaller Canonical GraphsJawahar Jain, Dinos Moundanos - Fujitsu Labs. of America,Sunnyvale, CAKartik Mohanram - Univ. of Texas, Austin, TXYuan Lu - Carnegie Mellon Univ., Pittsburgh, PA42.3 Efficient Variable Ordering UsingAbstraction Based Sampling TechniquesYuan Lu - Carnegie Mellon Univ., Pittsburgh, PAJawahar Jain - Fujitsu Labs. of America, Inc., Sunnyvale, CAEdmund Clarke - Carnegie Mellon Univ., Pittsburgh, PAMasahiro Fujita - Fujitsu Labs. of America, Inc., Sunnyvale, CA


LAYOUT OPTIMIZATIONCHAIR: Ralph H.J.M. Otten - Delft Univ. of Tech., Delft, The

NetherlandsORGANIZERS: Telle Whitney, Miodrag PotkonjakLayout needs to be optimized to a wide variety ofobjectives these days. This session presents asample of three widely different aspects: from devicesizing, module generation to density equalizing. Thislast topic, needed to enable effective chemical-mechanical polishing, is a new and challengingissue in layout design.

41.1 Minflotransit: Min-Cost Flow BasedTransistor Sizing ToolVijay Sundararajan, Sachin S. Sapatnekar, Keshab K. Parhi -Univ. of Minnesota, Minneapolis, MN41.2 Convex Delay Models for Transistor SizingMahesh Ketkar, Kishore Kasamsetty, Sachin S. Sapatnekar -Univ. of Minnesota, Minneapolis, MN41.3 A Macro-Driven Circuit Design Methodologyfor Custom High Performance DatapathsMahadevamurty Nemani, Vivek Tiwari - Intel Corp., Santa Clara, CA41.4S Model-Based Dummy Feature Placement forOxide Chemical-Mechanical PolishingManufacturabilityRuiqi Tian - Univ. of Texas, Austin, TX, Motorola Inc., Austin, TXD. F. Wong - Univ. of Texas, Austin, TXRobert Boone - Motorola Inc., Austin, TX41.5S Practical Iterated Methods for LayoutDensity ControlYu Chen, Andrew B. Kahng - Univ. of California, Los Angeles, CAAlexander Zelikovsky - Georgia State Univ., Atlanta, GA


Thursday, June

26


NEW FRAMEWORKSFOR THE EDA FIELDCHAIR: Olivier R. Coudert - Monterey Design

Systems Inc., Sunnyvale, CAORGANIZERS: Sharad Malik,

Srinivas DevadasAs design technology and the EDA field as awhole mature, new frameworks forroadmapping, measuring, and reusing theleading edge of progress must be put in place.This session presents four types of suchframeworks. First, a framework for an extensible,open-source living technology roadmap ispresented. Next is a framework for composingmodular components for system simulation.Third is a framework for instrumenting andmeasuring (then improving) the design processitself. The session closes with a panel of threeperspectives on how the web will be enabling toR&D processes throughout EDA.

43.1 GTX: The Marco GSRCTechnology Extrapolation SystemAndrew Caldwell, Andrew B. Kahng, FarinazKoushanfar, Hua Lu, Igor L. Markov, Michael R.Oliver, D. Stroobandt - Univ. of California, Los Angeles, CA43.2S A System Simulation FrameworkPeter van den Hamer, Wim van der Linden,Peter Bingley, Nico Schellingerhout - PhilipsResearch Labs., Eindhoven, The Netherlands43.3S Metrics: A System Architecturefor Design Process OptimizationAndrew B. Kahng, Stefanus Mantik - Univ. ofCalifornia, Los Angeles, CA

PANEL: WEB-BASEDFRAMEWORKS TOENABLE CAD R&DPANELISTS:Igor L. Markov - Univ. of California, Los Angeles, CAChristoph Meinel - Univ. of Trier, Trier, GermanyEllen Sentovich - Cadence Berkeley Labs., Berkeley, CA


HIGH PERFORMANCEMICROPROCESSOR DESIGNCHAIR: David Blaauw - Motorola, Inc., Austin, TXORGANIZERS: Anantha Chandrakasan, Ralph

H.J.M. OttenThis session presents design methodologies and verificationtechniques for Gigahertz microprocessors. The methodologiesaddress a range of problems from low-level timing verificationand clock distribution to Cache coherence protocols andmultiprocessor design verification. The use of “timing closure”by design is high lighted. The various approaches are verifiedon large commercial processors. The session also includes thedesign of high performance using GaAs technology.44.1 Timing Closure by Design, a HighFrequency Microprocessor DesignMethodologyStephen Posluszny, Naoaki Aoki, Dave Boerstler, PaulaCoulman, Sang Dhong - IBM Corp., Austin, TXBrian Flachs - Motorola, Inc., Austin, TXPeter Hofstee, Nobuo Kojima, Ohsang Kwon - IBM Corp.,Austin, TXKyung Tek Lee - Sun Microsystems, CADave Meltzer - IBM Corp., Yorktown, NYKevin Nowka - IBM Corp., Austin, TXJaehong Park - Samsung, KoreaJim Peter - IBM Corp., Austin, TXJoel Silberman - IBM Corp., Yorktown, NYOsamu Takahashi, Paul Villarubia - IBM Corp., Austin, TX44.2 Multiprocessing Design V erificationMethodology for Motorola MPC74xx PowerPCMicroprocessorJen-Tien Yen, Qichao Richard Yin - Motorola Inc.,Austin, TX44.3 A Methodology for Formal Design ofHardware Control with Application to CacheCoherence ProtocolsCindy Eisner - IBM Haifa Research Lab., Haifa, IsraelRuss Hoover, Wayne Nation, Kyle L. Nelson - IBM Corp.,Rochester, MNIrit Shitsevalov - IBM Haifa Research Lab., Haifa, IsraelKen Valk - IBM Corp., Rochester, MN44.4 DESIGNCONTEST: CGAASPowerPCFXUAlan Drake, Todd Basso - Univ. of Michigan, Ann Arbor, MISpencer M. Gold - Sun Microsystems, Chelmsford, MAKeith L. Kraver - Univ. of Michigan, Ann Arbor, MIPhirose N. Parakh - Monterey Design Systems, Sunnyvale, CAClaude R. Gauthier - Sun Microsystems, Palo Alto, CAP. Sean Stetson - Texas Instruments, Dallas, TXRichard B. Brown - Univ. of Michigan, Ann Arbor, MI


PANEL: WHEN BADTHINGS HAPPEN TOGOOD CHIPSCHAIR: Nagaraj NS - Texas Instruments,

Dallas, TXORGANIZERS: Nagaraj NS,

Shishpal Rawat

Design of reliable chips with high yield is anextremely challenging task in UDSMtechnologies. Time to market pressures,which often limit the necessary verificationbefore tape-out, typically are manifested asramp-to-production problems on "good"designs either in the manufacturing process orin the field. Burn-in process, a reactivemeasure to ship reliable chips, is not effectivefor high volume designs. Another cause forconcern is hidden failures that go undetecteddue to incompleteness of test vectors.This session begins with a tutorial thatexamines a number of "bad things that canhappen to good chips" both duringmanufacturing and in the field. The conceptof "design marginality" which can significantlyaffect manufacturing yield, the proximity tothe "cliffs" in chip operation, and test escapesthat could cause failures in the field arediscussed. Then the panel, from differentperspectives on yield and reliabilitychallenges, will describe their own real-worldexperiences, and discuss how thesechallenges could be addressed in themanufacturing process, design, and EDA.

45.1 EMBEDDED TUTORIAL: Yieldand Reliability Challenges in Designing"Good" ChipsAndrzej Strojwas - Carnegie Mellon Univ.,Pittsburgh, PA

PANELISTS:Ray Hokinson - Compaq Computer Corp.,Shrewsbury, MASung-Mo Kang - Univ. of Illinois, Urbana, ILWonjae Kang - Intel Corp., Santa Clara, CASani Nassif - IBM Corp., Austin, TXDavid Overhauser - Simplex Solutions,Sunnyvale, CATak Young - Monterey Design, Sunnyvale, CA

technicalprogram

Thursday, June

27

4:30to

6:00

chnical program




ADVANCES IN HIGH LEVELSYNTHESISCHAIR: Kazutoshi Wakabayashi - NEC Corp., Kawasaki,

JapanORGANIZERS: Rajesh K. Gupta, Kazutoshi WakabayashiThis session focuses on architectural synthesis andoptimization issues. The first paper presents asimultaneous behavioral synthesis and physicaldesign flow for DFGs. The second paper proposes anew approach for describing multi-waysynchronization protocols using a graphicalformalism. The third paper discusses optimization ofcarry-save-adder representation by retiming.

47.1 Unifying Behavioral Synthesis and PhysicalDesignBill Dougherty, Donald E. Thomas - Carnegie Mellon Univ.,Pittsburgh, PA47.2 Hardware Implementation of CommunicationProtocols Modeled by Concurrent EFSMs withMulti-Way SynchronizationHisaaki Katagiri - Osaka Univ., Toyonaka, JapanKeiichi Yasumoto - Shiga University, Hikone, JapanAkira Kitajima - Osaka Univ., Osaka, JapanTeruo Higashino, Kenichi Taniguchi - Osaka Univ., Toyonaka, Japan47.3 The Use of Carry-Save Representation inJoint Module Selection and RetimingZhan Yu - Univ. of California, Los Angeles, CAKei-Yong Khoo - Synopsys, Inc., Mountain View, CAAlan N. Willson Jr. - Univ. of California, Los Angeles, CA


LARGE-SCALE PARASITICANALYSISCHAIR: Alan Mantooth - Univ. of Arkansas, Fayetteville, ARORGANIZER: Alan MantoothMethods and algorithms are presented in this sessionthat address large-scale parasitic analysis. The firstpaper describes a method for improving the speed ofextraction and matrix sparsification for substratecoupling. The second paper describes a new methodfor capacitance calculation that involves integratedequation formalation but that uses charge distributionsthat decouple charge variation from conductorgeometry. The last paper combines frequency andtime domain techniques to achieve performanceimprovements in simulation of thermal networks.

46.1 Fast Methods for Extraction andSparsification of Substrate CouplingJoseph D. Kanapka - Massachusetts Institute of Technology,Cambridge, MAJoel R. Phillips - Cadence Design Systems, Inc., San Jose, CAJacob K. White - Massachusetts Instittute of Technology, Cambridge, MA46.2 Large Scale Capacitance CalculationSharad Kapur, David E. Long - Bell Labs. - LucentTechnologies, Murray Hill, NJ46.3 Fast Temperature Calculation for TransientElectrothermal Simulation by MixedFrequency/Time Domain Thermal Model ReductionChing-Han Tsai, Sung-Mo (Steve) Kang - Univ. of Illinois,Urbana, IL


Thursday, June

28


FAULT SIMULATION ANDEXTRACTION OF LOW-LEVEL EFFECTSCHAIR: Thomas W. Williams - Synopsys, Inc.,

Boulder, COORGANIZERS: Kwang-Ting (Tim) Cheng,

Irith PomeranzThis session features fault simulationand extraction techniques for digital andanalog circuits taking into account low-level effects. The first paper presentsfault simulation and test developmenttechniques for analog circuitry. Thesecond paper describes an environmentfor mixed switch/RTL fault simulation.The third paper introduces acomprehensive fault representationmechanism and a fault simulationprocedure for it. The fourth paperpresents an efficient extraction methodfor bridging faults.

48.1 Closing the Gap Between Analogand Digital TestingKhaled Saab, Naim Ben Hamida, BozenaKaminska - Fluence Technology Inc., Beaverton, OR48.2 A Switch Level Fault SimulationEnvironmentVenkatram Krishnaswamy, Jeremy Casas,Thomas Tetzlaff - Intel Corp., Hillsboro, OR48.3S Universal Fault Simulation UsingTuple FaultsKumar Dwarakanath, R.D. Shawn Blanton -Carnegie Mellon Univ., Pittsburgh, PA48.4S An Efficient Algorithm to ExtractTwo-Node BridgesSujit Thomas Zachariah, Sreejit Chakravarty,Carl D. Roth - Intel Corp., Santa Clara, CA


LOW POWER DESIGNTECHNIQUES ANDESTIMATIONCHAIR: Tadahiro Kuroda - Toshiba Corp.,

Kawasaki, JapanORGANIZERS: David Blaauw,

Vivek TiwariThe first paper describes a controlgenerated clocking scheme to savepower in datapath registers and clockdrivers of sequential circuits. Thesecond paper discusses bus encodingto reduce dynamic and static power inI/O for memory systems.The third paperproposes a dynamic voltage scalingscheme and a method to modify existingapplication programs for real-time multi-media applications. The last paperpresents a functional-level powerestimation methodology for predictingpower dissipation of embedded softwareat compilation time.

49.1 Power Minimization UsingControl Generated ClocksSrikanth Rao Muroor, Soumitra Kumar Nandy -Indian Institute of Science, Bangalore, India49.2 Bus Encoding for Low-PowerHigh-Performance Memory SystemsNaehyuck Chang, Kwanho Kim, Heonshik Shin,Jinsung Cho - Seoul National Univ., Seoul, Korea49.3S Run-Time Voltage Hopping forLow-Power Real-Time SystemsSeongsoo Lee, Takayasu Sakurai - Univ. ofTokyo, Tokyo, Japan49.4S Function-Level Power EstimationMethodology for MicroprocessorsGang Qu - Univ. of California, Los Angeles, CANaoyuki Kawabe, Kimiyoshi Usami - ToshibaCorp., Kawasaki, JapanMiodrag Potkonjak - Univ. of California, LosAngeles, CA


PANEL: EMERGINGCOMPANIES: ACQUIRINGMINDS WANT TO KNOWCHAIR: Dan Schweikert -

Sun Microsystems, PaloAlto, CA

ORGANIZER: Mike MurrayThe EDA industry is entering its thirddecade with more software suppliers thanever before, automating smaller andsmaller pieces of the design flow. Thequestion invariably is whether anemerging EDA company, or anysemiconductor industry supplier for thatmatter, can remain independent and growlarge enough to rival the big industryplayers. In fact, executives managingnewcomer players know what it takes tobe a publicly traded company. Theyunderstand first and foremost abouttechnology and other ensuing challenges.Customer support is crucial to theequation. Executives managing theseemerging and much talked aboutcompanies are colorful and seasonedEDA and semiconductor veterans. Theyhave a healthy mix of senior-levelexperience, business acumen and vision-- much like the big players -- and theintimate knowledge of the work in thetrenches which appeals to real designers.They are pushing the envelope ofcompany strategy by introducing cleverand innovative ideas related to newbusiness models, pricing and technologiesthat are currently being implemented orare working. The panel will offer a livelyand spirited debate on the correct strategyfor success.

PANELISTS:Joe Costello - Barcelona Design Inc.,Mountain View, CASteve Carlson - Tharas Systems, SantaClara, CAMoshe Gavrielov - Verisity, Mountain View,CARajeev Madhavan - Magma DesignAutomation, Cupertino, CAJudy Owen - SiliconX, San Jose, CAY.C.(Buno) Pati - Numerical Technologies,Inc., San Jose, CA

technicalprogram

Tutorial 1 - Friday, June 9

29

tutorials

Tutorials will be held at the Los Angeles Convention Center in the Second Level meeting rooms.

8:00 AM - Tutorial Registration Opens (Second Level) 12:00 Noon - Lunch - Rm. 515AB8:30 AM - Continental Breakfast - Rm. 515AB 5:00 PM - Tutorials End9:00 AM - Tutorials Begin

THE QUEST FOR SYNTHESIS AND LAYOUT TIMING CLOSURE Rm. 403A

Organizers: Jason Cong - Univ. of California, Los Angeles, CAPatrick Groeneveld - Magma Design Automation, Inc., Cupertino, CA

Presenters:Jason Cong - University of California, Los Angeles, CAOlivier Coudert - Monterey Design Systems, Inc., Sunnyvale, CAAnthony Drumm - IBM Corp., Rochester, MNPatrick Groeneveld - Magma Design Automation, Cupertino, CA

Audience : Logic designers, layout designers and CAD engineers would benefit from understanding new algorithm andtool capabilities for achieving timing closure between synthesis and layout. This tutorial will also help design projectmanagers and academic researchers in understanding the state-of-art solutions for timing closure and future researchdirections.

Description : Getting timing closure between synthesis and layout has become the biggest challenge in deep submicronchip design. The increasing significance of interconnect delay is forcing a complete re-assessment of the traditionaldivision between the logical design and physical design steps. How can we bond logic synthesis with placement androuting such that the resulting chip will meet the original circuit timing specifications? This tutorial will provide the latestanswers to this question. An in-depth technical overview of all techniques for timing closure will be discussed: newsynthesis techniques, wire buffering for optimum speed, timing analysis and clocking strategies, signal integrity, etc. Also,the technical core of a number of new design systems will be presented, each operating in fundamentally different ways.The audience will be offered a strong insight in the fundamental technical problems and their solutions.

The first section will provide an in-depth review of the existing techniques that have been successfully used today indesigning high-performance chips. This covers the full "bag of tricks" for timing correction, including buffering andmanipulating wire load models. Timing analysis and clocking methodologies will also be reviewed. The second partpresents the new 'gain-based synthesis' method that is based on the theory of logical effort. This method essentiallyfixes the gate delays before physical design, rather than the gate sizes. The presentation will describe how delay canbe kept constant during placement and routing and, with that, how the timing closure problem can be solved. Variouspractical details of this method that emerged during commercial application will also be discussed. The third partintroduces a new design closure method. It is based on simultaneous optimization and model refinement. Theplacement, synthesis, timing, and routing engines suitable for this 'spiraling convergence' technique will be presented,together with the framework that enables their interaction. The fourth section presents the latest approaches to globalinterconnect planning and optimization at the chip-level. Buffer block planning and wire width planning can maximizethe speed of the long wires crossing the chip. New methods to automate this process will be presented, together withmore advanced methods for interconnect-centric designs, including floorplanning with interconnect planning, andcombining partitioning with retiming.


30

tutorials

STATIC TIMING ANALYSIS AND OPTIMIZATION FOR HIGH-PERFORMANCEDIGITAL DESIGN SUCCESS RM. 404

Organizers: Tim Burks - Magma Design Automation, Inc., Cupertino, CADavid Blaauw - Motorola, Inc., Austin, TX

Presenters:Tim Burks - Magma Design Automation, Inc., Cupertino, CAJacob Avidan - AmmoCore Technology Inc., San Jose, CAChandu Visweswariah - IBM Corp., Yorktown Heights, NYPeter Beerel - Univ. of Southern California, Los Angeles, CA

Audience : This tutorial is intended for anyone with an interest in static timing analysis techniques for verification andoptimization, including system and circuit designers, CAD engineers, design project managers, and researchers.

Description : Too important to entrust to tools, but too difficult to attempt without them... specifying and achievingtiming goals has become a central part of the design process. As timing-driven methodologies come online, it iscritical to pay close attention to timing from the beginning of the design flow. When combined with formal verification,static timing analysis methods can verify the correct operation of a design more thoroughly than billions of simulationcycles. However, many pitfalls and traps await the unwary user. Successful use of static timing analysis requires acombination of design discipline, well-understood modeling assumptions, and carefully chosen algorithms.

The first section of this tutorial will cover the basic models and algorithms of static timing analysis. Topics will includethe static analysis assumption, graph models of circuit timing, arrival and required time calculation, path-tracingalgorithms, multifrequency clocks, timing models for latches and dynamic logic, algorithms for handling false andmulticycle paths, and algorithms for fast incremental timing analysis. Special attention will be given to the problem ofverifying that a design has been properly constrained.

The second section will describe delay calculation methods in detail. Beginning with gate-level delay models, the modelsused in current tools will be described, including table lookup models, operating condition scaling, and the characterizationprocess. The Delay Calculation Language (DCL) standard will be presented and an overview of effective capacitance andwire delay calculation algorithms will be given. A discussion of limitations of gate-level models will lead to a presentation oftransistor-level modeling techniques including partitioning, fast timing simulation, generation of worst-case delays and delaycalculation for special circuits including domino and differential logic.

The third section will be devoted to optimizing circuits based on static timing analysis, implying optimal sizing of gatesand wires. Heuristic and formal methods will be compared and contrasted, with an emphasis on the latter. Thecomponents of a state-of-the-art static optimization tool include fast simulation, time-domain sensitivity analysis,innovative problem formulation with the help of a static timing analyzer and a nonlinear optimization package; each ofthese components will be discussed. Limitations and methodology implications will also be addressed.

Finally, several advanced timing analysis topics will be presented.Some simple techniques from asynchronous analysiswill be discussed that can be used to verify system-level performance and to derive the necessary conditions for correctoperation of dynamic circuits. The effects of noise and process variation on timing analysis will also be discussed.


31

tutorials

SYSTEM LEVEL DESIGN WITH EMBEDDED PLATFORMS Rm. 403B

Organizers: Kees Vissers - Philips Research Labs., Briarcliff Manor, NYBart Kienhuis - Univ. of California, Berkeley, CA

Presenters:Alberto L. Sangiovanni Vincentelli - Univ. of California, Berkeley, CABart Kienhuis - Univ. of California, Berkeley, CAJan Rabaey - Univ. of California, Berkeley, CAKees Vissers - Philips Research Labs., Briarcliff Manor, NYDiederik Verkest - IMEC, Leuven, Belgium

Audience : This tutorial is intended for system design professionals, EDA professionals and people involved inembedded systems.

Description : The increasing complexity of systems on silicon makes them more costly to manufacture and design.However, for these system to be successful in the market, the design time, and therefore time to market, should shrink.Over the years we have seen the trend in design from the transistor level to the gate level, then to the register transferlevel, and recently to the behavioral level in VHDL and Verilog. However, while Moore's Law holds, future designs willhave to start at even higher levels of abstraction in order to keep the design time sufficiently short.

In this tutorial we introduce a separation between architecture and functions or applications, followed by mapping theapplication onto the architectures of the embedded platforms. In the morning session, we discuss trends in embeddedsystems and give a definition of platforms. We elaborate on the impact of platform thinking on embedded systems andhighlight the importance of separation of computation and communication in embedded systems. We present the y-chartmethodology for designing systems using embedded platforms. In this methodology, sets of applications are mapped ontoarchitectures at several levels of abstraction. We show several models of computation that play an important role in the y-chart methodology. We explain these models, including models for control and data flow. We demonstrate that thecomputation and communication characteristics in the Picoradio research at UC Berkeley define the exploration space fornovel implementations. We also illustrate the need for and role of advanced system level tools.

In the afternoon session, we look at two industrial design cases for multimedia systems. In the first design case, we focuson the design and exploration of multimedia functions for a real-time high-performance platform that consists of a MIPScore, a VLIW core, and several coprocessors. We look at the modeling of video applications and at the modeling ofarchitectures. We show how we map Kahn Process Networks to VLIW cores and dedicated coprocessors, and wequantify and illustrate system trade-offs in terms of hardware, software and communication costs. The design of the datatransfer mechanism and data storage organization in these multimedia applications is extremely important and has alarge impact on system performance and total power consumption. Using compiler technology, we show the explorationof several memory organizations. We present quantitative results for a multimedia application.


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tutorials

SIGNAL INTEGRITY IN DEEP SUBMICRON DESIGNS Rm. 408AOrganizer: Chung-Kuan Cheng - Univ. of California, San Diego, CAPresenters:Tak Young - Monterey Design Systems Inc., Sunnyvale, CAShen Lin - Hewlett Packard Labs., Palo Alto, CASanjay Dhar - Mentor Graphics Corp., Wilsonville, OregonChung-Kuan Cheng - Univ. of California, San Diego, CA

Audience : The tutorial is intended for system and circuit designers who would benefit from understanding signalintegrity of interconnect dominated designs, for CAD engineers (both Research & Development and support), for designproject managers, and for academic researchers.

Description : In this tutorial, we present the design flow and analysis of signal integrity in deep submicron designs. Wefirst talk about the RLC parasitic extraction. We then study the capacitive and inductive effect with emphasis oninductance for high speed circuitry. Finally, we discuss industrial practices and cases studies.

We introduce the overall design flow and fundamental theories and concepts of RLC network analysis for interconnectdominated designs.

RLC Extraction: We describe the parasitic models and the extraction techniques of interconnect electronic parameters.An extraction flow with particular emphasis on cross-coupling capacitance screening and generation of net delays forfull chip delay analysis will be discussed.

On-Chip Inductance and Coupling Effects: We investigate the inductance and coupling effects for high speed designs.Impacts of RLC power/ground network modeling and delta i noise are discussed. Techniques to minimize inductanceeffects are explored. We also talk about our experience on test chip modeling and measurement.

Industrial Practices and Case Studies: We address the bottlenecks regarding the effects of coupling and the significantamount of parasitics. Case studies from different industrial designs will be used to demonstrate the importance ofinterconnect effect on timing and functional behavior.


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tutorials

DESIGN TECHNOLOGY FOR BUILDING WIRELESS SYSTEMS-ON-CHIPRm. 408BOrganizer: Rajesh Gupta - Univ. of California, Irvine, CAPresenters:Mani Srivastava - Univ. of California, Los Angeles, CACharles Chien - Rockwell Science Ctr., Thousand Oaks, CAGeorges Gielen - Katholieke Univ., Leuven, BelgiumRajesh K. Gupta - Univ. of California, Irvine, CA

Audience : This tutorial is targeted for practicing engineers interested in system and IC design tools for buildingwireless systems. CAD developers and researchers will develop an appreciation of the design tool requirements forwireless networked computing systems. Minimal familiarity with VLSI design, communications basics and computerprogramming is assumed.

Description : The progress in IC technology is making possible development of chips that incorporate all the elementsof a complete wireless radio system on a chip (SOC) as a means to obtain low system cost, ease of system insertionand miniaturization. Such an antenna-to-network chip would incorporate an RF front end, baseband digital signalprocessing, link layer coding functions for error, compression, and encryption, and medium access control and othernetwork protocols. An example of the drive toward wireless system on a chip is the race among 1000+ design housesaround the world to develop a single-chip device for "Bluetooth."

From an implementation point of view, this would require integration of analog circuits, high performance custom signalprocessing datapaths and cores, customized logic, embedded processor, and complex software environments on thesame chip or substrate. The design, simulation, implementation, and testing techniques required for such chips arecomplex, as are the metrics to evaluate the performance. The current effort in standardization of pre-designed core cellsis expected to play a major role in making it possible for designers to build complete and customized wireless SOCs.However, the diversity of cores required in such systems represents a special challenge in almost all aspects ofIC/System design.

In this tutorial we present the state of the art in designing such systems, focusing from a system perspective, on boththe CAD problems that arise from such chips as well as on the tools and design techniques. The presentation is roughlydivided into four parts. First part covers basics of wireless systems including RF, communication and networkingsubsystems; representation and modeling of wireless system components (RF, baseband DSP, protocol processing fornetwork interfaces) and optimization across heterogeneous processing domains. Second part addresses architecturaldesign techniques for integrated wireless systems, particularly tradeoffs in a resource, power and bandwidthconstrained environment. Third part addresses design tools, techniques and cores for wireless systems including toolsfor software synthesis and optimization. The last part addresses design tools and modeling for RF circuits. We addressthe technology, circuit, and architecture partition (e.g. where to draw the line between analog/RF and digital basebandprocessing) issues related to the integration of RF and baseband processing on the same chip.


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LOW-POWER SYSTEM DESIGN: APPLICATIONS, ARCHITECTURES, ANDDESIGN METHODOLOGIES Rm. 406

Organizer: Anand Raghunathan - NEC USA, C&C Research Labs., Princeton, NJPresenters:Anand Raghunathan - NEC USA, C&C Research Labs., Princeton, NJSujit Dey - Univ. of California, San Diego, CAArkady Horak - Motorola Inc., Austin, TXTrevor Mudge - Univ. of Michigan, Ann Arbor, MIKaushik Roy - Purdue Univ., West Lafayette, IN

Audience : This tutorial is intended for system designers who are involved in designing low-power and portablesystems, developers of system-level or low-power design methodologies and CAD tools, managers thereof, andresearchers interested in low-power system design.

Description : Advances in semiconductor technologies, and the aggressive time-to-market, performance, and costrequirements have led to a paradigm shift in electronic system design, with the evolution of system-level-integrationallowing an entire system to be integrated on a single chip. At the same time, the rapid growth in battery-driven systems,such as wireless communication devices and information appliances, has elevated power consumption to be a primaryfactor influencing system-level design decisions. This tutorial will highlight various critical aspects of low-power systemdesign: applications, system architectures, design methodologies and tools, and relevant technology trends.

The first part of the tutorial will present examples of low-power applications from the wireless communications domainand analyze the requirements imposed by application trends on system-level architectures and design methodologies.We will then present examples of low-power system architectures for such applications to illustrate current designpractice. Examples of IP cores currently available in the market will be used to illustrate the issues involved in selectingand designing with low-power system components. We will also present various low-power architectural techniques thatcould be employed in embedded processor cores, including memory organization, low-power instruction decoding, andcontrolled speculative execution.

The second part of the tutorial will focus on system-level design methodologies and tools for power analysis andreduction. Topics covered will include system-level power estimation and profiling, HW/SW partitioning and mapping forlow-power, low-power embedded software, dynamic voltage and performance management strategies, memory and I/Ooptimizations, power issues in bus architectures, system-level power management, and battery-friendly system design.

The third part will examine technology trends and their impact on low-power system design. We will discuss trends insupply and threshold voltages, the increasing importance of managing leakage power, and power issues involved inthe integration of heterogeneous technologies such as logic and DRAM, and multiple supply and threshold voltages ona single chip.

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tuesday, june 6 · increase the capacity of bdd-based model checking. the first paper investigates...

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