tsv technology for 2.5d & 3d ic solutions
TRANSCRIPT
TSV Technology for 2.5D & 3D IC Solutions
Muster Wang
Corporate RD
ASE Group
Nov. 9 , 2011
Presented by
2.5D & 3D SiPs to Meet Product Trends
- Function Integration & Form Factor
PKG-on-PKG
QFP
Stack CSP
FC + WB
FC BGA
3D TSV Stack
2.5D & 3D Integration
3D CoC Stack
2© 2011 ASE Group. All rights reserved.
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TSV Potential Applications
Vertical interconnect minim
um pitch
(µm)
Multi-level 3D IC (CPU + Cache + DRAM + Analog + RF + Sensor + I/O)
3D Stacked Memory (NAND, DRAM, …)
2007 2009 2012 >2014
Low Density 3D via Chip-level Bonding
Logic (Multicore Processor/ BB ASIC with Cache Memory)
Image Sensor
Digital Signal Processor
Via size 50~100µm
Via size~5-30µm
Via size=<5µm
CPU
Cache memory
Via size=<2µmCPU
Cache Memory
DRAM / NVM
Analog
RF Power
Sensor I/O
Sensor I/O
High Density 3D via Wafer-level Bonding
CMOS Image Sensor (Sensor + DSP + RAM)
1000
1
10
100
Vertical Device on CMOS
Sources : EMC-3D, IBM & ASE Data
Via Last TSV (Si interposer-2.5D)
ASIC
Si Interposer
Substrate
ASIC
Si Interposer
Substrate
© 2011 ASE Group. All rights reserved.
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Si Interposer Benefits
� Alleviate ELK/ ULK stress in large die
� Bridge organic substrate gap for dense & complex substrate
� Package advanced wafer node w/ tighter bump pitch
� Integrate multi-chip SiP platform
: Alternative SoC Solution (Allow IC designer to partition chips and re-organize in Si interposer platform)
: Provide platform for heterogeneous chip integration(IPD, MEMS, Sensor…)
Si - Si to minimize CTE impact on ELK
Match advanced wafer pitch
Fan-out to match existing substrate capability
Chip 1 Chip 2
Si Interposer
© 2011 ASE Group. All rights reserved.
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2.5D Si Interposer- IC scale vs Substrate scale
Packaging gap
Time
Size
sca
ling
IC scale
Substrate scale
Die size (pitch) ↓Die cost ↓Substrate cost ↑
Die size (pitch) ↓Die cost ↓Substrate cost ↓Si interposer cost ↑
© 2011 ASE Group. All rights reserved.
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FC Bump Pitch Roadmap
Time
Pitch (um)
2008 2009 2010 2011 2012
200
100
150
50
CtS
Substrate Applicable
CtC
Si Interposer Applicable
50um40um 40um
85um
150 um
120um125 um
135 um
Microbump Bump Pitch
Chip on Si-carrier to Resolve
1. Substrate Technology Gap & Cost
2. Cu-Low K Delam for N28 & above
3. Cost Competitiveness
C4 Bump Pitch
© 2011 ASE Group. All rights reserved.
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Si Interposer Enabling Chip Integration
Diplexer Balance Filter Balun
+
� Alternative SoC Solution (Allow IC designer to partition chips and
re-organize in Si interposer platform)
� Provide platform for heterogeneous chip integration
(IPD, MEMS, Sensor…)
© 2011 ASE Group. All rights reserved.
IPD MEMS
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2.5D Si Interposer Key Challenges
� Si Interposer Sourcing & Ownership
� Logistic & interface standardization
� Warpage control
� Cost
� Yield
� Known-Good Si Interposer
© 2011 ASE Group. All rights reserved.
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2.5D Si Interposer Challenge – Warpage Control
M1≠M2 ���� Warpage issue
Neutralsurface
Moment-2
Moment-1
© 2011 ASE Group. All rights reserved.
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Si Interposer Package Reliability
� Reliability
- 3 lots MSL3/260C + TCT3000 & HAST504 passed.
8x8 mm2 ASIC (65nm lowK)
12x12 mm2 Si Interposer
2000+ TSVs
35x35 FC BGA, 1/2/1 sub
© 2011 ASE Group. All rights reserved.
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Thank You
www.aseglobal.com
© 2011 ASE Group. All rights reserved.