transfer (tri-state) gate + inverter mcutri 2 4070 exclusive or/nor gate mcuexorn 3 4077 arithmetic...
TRANSCRIPT
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ULAs
High Speed CMOS Uncommitted Logic Arrays
FEATURES
• Offers advantages of custom design without the development
cost or time
• "PC board on a chip" approach allows simple, easy to design
technique by customer or General Instrument
• Single mask commitment pattern
• 5ns gate delay • Single supply voltage (3V to 6V)
• Low power dissipation due to silicon gate CMOS technology
• Available on-chip power-on reset option
• Full design package for customer designs available
• Short turnaround time, typically 6-8 weeks from layout to
prototypes
WHAT ARE GENERAL INSTRUMENT UlAs?
The General Instrument Uncommitted Logic Arrays consist of a
matrix of pre-processed basIc logic and peripheral cells which
require only a single layer of metal Interconnections to be made
into a custom designed Circuit
The design process consists of interconnecting, via the extensive
interconnection highway, standard cells selected from the com
prehensive cell library (Each standard cell being constructed
from one or more basic cells) This simple procedure, which
reqUires no special semi-conductor design experience, is Similar
to printed CirCUit board layout and may be undertaken either by
the customer or by General Instrument
ARRAY DESCRIPTION
The gate array consists of rows of basic logic cells with intercon
nection highways between each row On the edge of the chip,
surrounding the logic cells, are basic peripheral cells with an
Interconnection highway between the peripheral and the logic
cells The peripheral cells buffer signals Into and out of the chip
See Figure 1.
The customer's circuit is bUilt up uSing fully characterized stan
dard cells selected from the large, comprehensive cell library
Each standard cell IS constructed from one or more of the basIc
logic cells (or from one basIc peripheral cell In the case of the
standard peripheral cells)
THE GENERAL INSTRUMENT ARRAYS
No. of No. of Minimum
Type No. Gales i/O Pads Package Size
LA03 324 32 14
LA05 560 40 16
LA10 950 52 16
LA15 1440 64 22
LA20 2014 76 24
1 gate = 1 basIc logic cell
= 2 N-Channel + 2 P-Channel transistors conflgurable
as a dual Inverter, 2 Input NAND gate, transmission
gate etc
Note: Pin count includes 2 power pins.
The cell library Includes
Simple gates (AND, OR, NAND, NOR. exclusive OR etc)
Latches
Decoders
Shift Registers
ArithmetiC Elements
Input Buffers
Output Buffers
A complete list of standard cells appears at the end of this data
sheet and includes a cross-reference to standard 4000 series
CMOS Integrated CirCUitS
The interconnection between the standard cells IS done In the
interconnection highways, each of which can carry up to ten
tracks Extensive cross-under faCilities are provided in these
highways to allow tracks to cross each other In order to connect to
the standard cells
The metal interconnections inside standard cells are held on the
General Instrument graphics system and are automatically added
to the interconnections between the cells at the dlgltization stage
BASIC lOGIC CEll
The basIc logic cell consists of 4 MaS transistors (2 N-Channel
and 2 P-Channel) connected together as shown in Figure 2
The gate connections are in polysilicon, are continuous through
the cell and are available at the metal contacts both at the top and
the bottom of the cell
The two P-Channel transistors each have one common source
(drain) and one isolated source (drain) each of which may be
connected to the metal contacts at the top of the cell
Similarly the N-Channel transistors have their source and drain at
the bottom of the cell
The power supply lines are taken through every cell In metal
The Internal connections of the cell (which convert the four sepa
rate transistors of one (or more) basic logic cells Into a standard
cell) are made In metal. See Figure 3.
The interconnections between standard cells are made to the
metal c6ntacts at the top and bottom of the cells
BASIC PERIPHERAL CEll
The basic peripheral cell consists of an input section and an
output section See Figure 4
The input section has two MaS transistors (one N- and one
P-Channel) connected toform an inverter A resistor in series With
the gates plus two catching diodes gives Input static protectIOn A
2kO and a 15kO pull-up resistor are available which may be,
optionally, connected to the Input
The output section also has two MaS transistors (one N- and one
P-Channel) which may be connected to form either an open drain,
totem pole or trl-state output stage Two catching diodes are
provided to give output static protection
The peripheral cell also has a bonding pad which IS linked, inSide
the cell, to the Input and/or output sections and IS the pOint to
which the external bond wires to the chip are connected
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BASIC LOGIC
CELL
o
o
o
o
ULAs
1111111111111111
1111111111111111
10 10 10 10
CHIP BOUNDARY
o
o
o
Flg.1 BASIC GATE ARRAY LAYOUT
CELL BOUNDARY ,
• • • t/ , ' rim , ' , '
! ! : ! , , , ,
T T
,
T , ,
2KCl
CELL BOUNDARY
ULAs
---- -
(a)
(b)
(c)
MCU 2NAND
DECAL ALIGN M ENT _ ...... -Jr-"'1:-:'iL...L...JJ
MARK
DECAL ALIGNMENT
MARK
CL
CL
X
USED
CONTACT
INPUTS
D
MCUR2NIP
ULAs
DECAL BOUNDARY
OUTPUT
QR
OVERLAP INTO INTERCONNECTION HIGHWAY
Q
MCURDT
'-v-' UNUSED
ULAs
PROCEDURE I GENERAL INSTRUMENT DESIGNS ULA
CUSTOMER GENERAL INSTRUMENT
I I
PRODUCT SPECIFICATION I QUOTATION & APPRAISAL
LOGIC DIAGRAM I ARRAY SIZE DETERMINED
COMPUTER SIMULATION OR TIMING & STATUS DIAGRAMS
• CUSTOMER ACCEPTANCE DELIVERY DATE VERIFIED
& PURCHASE ORDER
TRANSLATION OF ULA CELLS ULA LOGIC DIAGRAM ADDITION OF TEST LOGIC ULA LOGIC SIMULATION (WORST CASE)
, CUSTOMER VERIFICATION ULA LAYOUT
DIGITIZE LAYOUT TO LOGIC CHECK ARTWORK CHECK, TEST PATTERN GENERATION, SIMULATE TEST WITH TEST PATTERN
MASK GENERATION
WAFER COMMITMENT] WAFER PROBE PROTOTYPE PACKAGE FINAL TEST
, CUSTOMER EVALUATION PRODUCTION DEVICE & ACCEPTANCE FABRICATION
t
Fig. 8 DESIGN INTERFACE
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ULAs
PROCEDURE II CUSTOMER DESIGNS IN ULA FORMAT
CUSTOMER GENERAL INSTRUMENT
PRODUCT SPECIFICATION
LOGIC DIAGRAM
COMPUTER SIMULATION OR
TIMING & STATUS DIAGRAMS
+ TRANSLATION TO ULA CELLS
ELECTRICAL CHARACTERISTICS
Maximum Ratings·
All inputs and outputs (with respect to GND) ............... -0 3V to 7V
Storage Temperature ••..•.•....•................•... -65°C to +150°C
Operating Temperature .•..•........•.......••......• -55°C to +125°C
Soldering Temperature of leads (10 seconds) ••........•..••..• +300° C
Standard Conditions (unless otherwise stated)·
Operating Voltage Range +3V to +6V
Operating Temperature Range 0° C to +70° C
-40° C to +65° C
ULAs
ULAs
EXAMPLE 2: OoTYPE FLIP-FLOP (MCUOT)
POSITIVE EDGE TRIGGERED FLIP-FLOP
D
CL
(DT)
BLOCK SCHEMATIC
Characteristics
Propagation Delay Time: Clock to 0 Clock to 0
Transition time
High to Low Level 0 0
Low to High Level 0 0
Clock Input Frequency
(0&0 Unloaded)
Data Set Up Time
Data Hold Time
Clock Rise or Fall Time
Input Capacitance. Node CL
D
Inherent Output Capacitance: Node Q
a
NOTES.
o
Min Typ
- 20
- 7
- 2.0
- 40
- 4.5
- 9
dc -30 -12 -- -- 35
- 35
- 85
- 135
LOGIC
,...-----{a
TRUTH TABLE
IN OUT
CL D Q Q
../ 0 0 1
../ 1 1 0
"- X Q Q NO CHANGE
Max Units Conditions
34 ns
12 ns
Note 1
26 ns/pF
54 ns/pF
58 ns/pF
117 ns/pF
17 MHz
- ns
- ns
1000 ns
5 pF
5 pF
11 pF Note 2
18 pF
1. If Q is loaded total propagation delay time to Q = propagation delay time to Q + additional transition time to Q.
2. If Q or 0 has to drive a switched load (eg. D input to MCUTRI) then outputs must be buffered with Inverter cell.
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ULAs
STANDARD CELL LIST
No. of Gate Nearest CMOS
Cell Description Cell Name Equivalents Equivalent
Gates
Inverter Fast MCUINVI 1 4069
Dual Inverter MCUINV2 1 4069
21P NAND Gate MCU2NAND 1 4011
21P NAND/AND Gate + Inverter MCU2AND 2 4018
31P NAND/Gate + Inverter MCU3NAND 2 4023
31P NAND/AND Gate MCU3AND 2 4073
41P NAND Gate MCU4NAND 2 4012
41 P AND/NAND Gate + Inverter MCU4AND 3 4082
21P NOR Gate MCU2NOR 1 4001
21 P NOR/OR Gate + Inverter MCU20R 2 4071
31 P NOR Gate -I- Inverter MCU3NOR 2 4025
31P NOR/OR Gate MCU30R 2 4075
41P NOR Gate MCU4NOR 2 4002
41 P NOR/OR Gate -I- Inverter MCU40R 3 4072
2 AND 2 NOR Gate MCU2ANNO 2 4085
2 AND NOR/OR Gate -I- Inverter MCU2ANOR 3 4019
Transfer (Tri-State) Gate + Inverter MCUTRI 2 4070
Exclusive OR/NOR Gate MCUEXORN 3 4077
Arithmetic
Half Adder + Inverter MCUHAD 4
Full Adder MCUFAD 7 4008
Registers & Latches
Set-Reset 0 Type Flip Flop MCUSRDT 8 4013
Reset 0 Type Flip Flop MCURDT 7 4013
Set 0 Type Flip Flop MCUSDT 7 4013
D Type Flip Flop MCUDT 6 4013
Set-Reset 0 Latch MCUSRDL 5
Reset D Latch MCURDL 4
Set 0 Latch MCUSDL 4
o Latch MCUDL 4 4042
NOR SIR Latch MCUNOSR 3 4043
NAND SIR Latch MCUNASR 3 4044
o Register (First Bit) MCUDREGF 5
o Register (Middle Bit) Dual MCUDREGM 5 4042
D Register (End Bit) MCUDREGE 3
Shift Register (First Bit) MCUSHRF 10
Shift Register (Middle Bit) MCUSHRM 5 4015
Shift Register (End Bit) MCUSHRE 5
Half Parallel Loading Shift Reg Clock Drivers MCUHPLSF 8
Half Parallel Loading Shift Reg First and Middle Bit MCUHPLSM 7 4021
Half Parallel Loading Shift Reg End Bit MCUHPLSE 7
Decoders
Expandable 7-Segment Decode Segment a MCU7SGA 7
Expandable 7-Segment Decode Segment b MCU7SGB 7
Expandable 7-Segment Decode Segment c MCU7SGC 5
Expandable 7-Segment Decode Segment d MCU7SGD 8 4055
Expandable 7-Segment Decode Segment e MCU7SGE 5
Expandable 7-Segment Decode Segment f MCU7SGF 8
Expandable 7-Segment Decode Segment g MCU7SGG 8
Service Elements
2 Row Interconnect MCU2INT 1
Peripheral
Input Buffer Inverting MCUNIP
Input Buffer Inverting with 15kO Pull Up Resistor MCURINIP
Input Buffer Inverting with 2kO Pull up Resistor MCUR2NIP
Output Buffer Inverting MCUNOP
Output Buffer Inverting Open Drain MCUODNOP
Tri-State Output Buffer plus Inverting Input Buffer MCU3IO
Dummy Pad MCUDUM
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