towards a reconfigurable nanocomputer platformphoenix/nsc1/presentation/beckett.pdfnanocomputer...
TRANSCRIPT
-
1
1
Towards a ReconfigurableNanocomputer Platform
Paul Beckett
School of Electrical and Computer EngineeringRMIT University
Melbourne, Australia
NSC-1 2
The Nanoscale “Cambrian Explosion”
• Disparity:– Wide range of
emerging non-Sitechnologies
• Diversity:– Many new device
options in CMOS,GaAs and othernon-Si
-
2
3
Example Nanoscale Devices
Quantum dot
Quantumdiffraction
FET
Quantuminterference
devices
surface super-lattices
RSFQ
Q-Well
GMR/CMR
MQCA
Hybrid-Hall effect
Molecularnano-
magnetics
MagneticRTD
Rotaxane
molecularx-bar
CAEN
Coulomb-coupledopticallypumped
nanodevices
DNA
CNT
C60 logic& memory
Nanotubearray logic
Large-bandgapdevices
(AlN, BN)
RTD/HFET
RTTlogic &memory
Multi-valuedlogic
nano-pipelining
SOI
Si-Ge
Dual-gate
VerticalFET
Ballisticnano-FET
MagneticMolecularNanotubeHetero-junction
Silicon
Disparity →→→→
4
The “Ideal” NanocomputerPlatform?
• Very large, scalable with rich, local connectivity• Built from simple devices that exhibit:
– High functionality (?)– Gain > 1– Static (at least) and preferably non-volatile operation– (Very) low power density– Room temperature operation
• Reliable and fault tolerant• Preferably no intrinsic reliance on any form of
global signal (e.g. a master clock)• Reconfigurable in operation, with little or no
performance penalty
-
3
5
Three Example Nanoscale Systems
1. Multi-valued SRAM Based Platform– RTD multi-valued RAM
– Dual-gate transistors
2. Phase Transition Device Based Platform– Resistive thin-films
3. A Nano-Magnetic Platform– Double spin-filter junction
6
• metal-insulator tunneltransistor (MITT)– gate voltage modulates the
tunnel barrier
• compatible with currentfabrication processes– can be buried in oxide layer
• Proposed dual-gateincreases functionality– Low-overhead reconfiguration
Multi-valued SRAM BasedPlatform
DrainSource
Top Gate
Back Gate TunnelInsulator
substrate
gate insulator
gate insulator
A
-0.6 -0.4 -0.2 0.0 0.20
0.2
0.4
0.6
0.8
1.0
-0.4V
-0.3V
-0.2V
-0.1V
0.0V
Second-Gate Voltage
B
C
VDD
RL
VG1 VG2
-
4
7
Multi-valued SRAM BasedPlatform
• 3-state memory (Wei & Lin)
• V1-3 matched by adjustingRTD barrier layer thicknesses
it Line
Word LineVDD3
VSS
IP
V1 V2 V3
ID
VD
IV
VDD3VSSVDD VSS VSS VDD
WordLine
Bit Line
Substrate 1
Substrate 2
RTDs RTDs
Out 1RL RL
insulator
Gnd
RL
• Ultimate dimensions50nm
• ~3 x 109 cells/cm2
8
Non-volatility – Chalcogenide Films
• Chalcogenide films act as fastnon-volatile programmableresistor
• Compatible with current(CMOS) logic fabrication
• Scales well to nanoscaledimensions (20-30nm)
• Vertical integration
Word Line
VA
VSS
Bit Line
PolycrystallineChalcogenide
np
n+substrate layer
bit line
ground plane
back gate
tunnel insulator
word line
Vdd plane
internal routing
top gate/input
schottky metal
gate insulator
gate insulator
TiW
SiO2
-
5
9
Double Spin-Filter Tunnel Junction
• Magnetoresistive tunnel device (Worledge &Geballe)– Potentially very high GMR
– Formed from two different layers that areinsulating but magnetic with unequal coercivities
nonmagneticelectrode
pinnedmagneticbarrier
nonmagneticelectrode
freemagneticbarrier
d d
J
Ef
J
Ef
pinnedbarrier
freebarrierAntiparallel
parallel
10
Vertical Double Spin-FilterJunction
• Resistance is variedbetween the inner pillarand the multiple outerconductors
• Requires ~20Ǻ films onvertical pillar– No obvious candidates
• Thickness control andlattice matching will beimportant
Substrate
a) Top View b) Side View“pinned” layer
free layerinner
conductor
outerconductors (x 4)
c) Square MeshConnections
-
6
11
Spin-Filter Based Platform
• RTD substrate addsnon-linearity to effectlogic
• VTT for isolation
• Junction densities inexcess of 2 x 1011/cm2
possible
Conductive substrate
RTD RTD
VDD
RTD
Vertical FETword line
BL BL BL
tunnel junction
verticalchannel
gatedielectric
12
Spatial Computing
• Memory Hierarchy– Tries to hide the cost of
moving code and data itemsfrom one place to another ina processor system
• 3D memory (Zhang)– Proposed as means memory
and processing physicallycloser together
Zhang, 2000
Inter-level Dielectric
IC substrate
memory layers
3D ROM
-
7
13
A 3D Reconfigurable ComputingPlatform
• Merged processor/memory into 3D structure
• Reduced memoryperformance gap
• Extreme memorybandwidth
• Processing-in-memory;processing-is-memory
memory/processor layers
base substrate
verticalinterconnect
3D Processor/memory
14
Reconfigurable NanoelectronicDevices?
PRO
• Maximizes utility ofsmall devices
• Reconfiguration over-heads kept small
• (Mostly) evolving fromexisting techniques
• Compatible with logicsynthesis systems
CON
• Can they be built?
• Is the added complexityjustified vs. (say)molecular approach?
• Will they efficientlysupport high-performancecomputer architectures
-
8
15
What’s Next?
• Simulation of nano-magnetic materials
• Characterization of typical junctions– e.g. tunneling conductance
• Simulation of GMR-based array platform
• Development of Spatial Computingtechniques suited to this platform
16
And in the long term?
• “Decimation followed by diversification”
(Gould)
• Test against the “environment”– ease of fabrication, cost, ease of use etc.
• Extinction for some, consolidation andgrowth for others
-
9
17
Towards a ReconfigurableTowards a ReconfigurableNanocomputerNanocomputer PlatformPlatform
Thank YouThank You
Paul BeckettPaul Beckett