total-dose radiation hardness assurance

552 IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 50, NO. 3, JUNE 2003

Total-Dose Radiation Hardness AssuranceD. M. Fleetwood, Fellow, IEEE,and H. A. Eisen, Senior Member, IEEE

Abstract—Total-dose radiation hardness assurance is reviewedfor MOS and bipolar devices and integrated circuits (ICs), with anemphasis on issues addressed by recent revisions to military andcommercial standard test methods. Hardness assurance typicallydepends upon sample tests of a subgroup of devices or circuits todetermine whether the full group meets its performance and func-tionality requirements to a desired confidence level. The dose ratesof many standard test methods match neither the very high doserates of some military environments nor the very low dose ratesof most space environments. So, one must ensure that hardness as-surance test plans address device response in the radiation environ-ment of interest. An increasing emphasis has been placed over thelast few decades on standardized test procedures to qualify devicesfor use in the natural space radiation environment. Challenging is-sues for defining test methods for space environments areMOStransistor threshold-voltage rebound and enhanced low-dose-ratesensitivity for linear bipolar devices and ICs. Effects of preirradi-ation elevated temperature stress on MOS radiation response arealso a significant concern. Trends are identified for future radia-tion hardness tests on advanced microelectronics technologies.

Index Terms—Bipolar radiation effects, hardness assurance,MOS radiation effects, test methods.

I. INTRODUCTION

T HE FUNDAMENTAL challenge of any hardness assur-ance program is to assure in a cost-effective and timely

fashion that devices and integrated circuits (ICs) will performas intended in systems and environments of interest. Becausetotal-dose irradiation is usually considered a destructive test, inthe sense that the tested device is no longer suitable for systemuse, nearly all hardness assurance testing depends on sampletesting of a group of devices or circuits. From this population,one must be able to infer with suitable confidence the radia-tion response of the untested portion of the sample that will beused in a particular system. This requires that the sample popu-lation be relatively homogeneous. Nominally identical devicesor ICs can show quite different radiation responses. So, there isa special problem for many commercial technologies for whichpackaging lots that are grouped by date code do not necessarilyall come from the same “diffusion” lot, or for processes withsignificant hardness variability. Moreover, total dose radiationenvironments range in dose rate from above 10rad(SiO )/sfor certain military environments to less than 10rad(SiO )/sfor natural space environments [1]. MOS and bipolar radiationresponse often depend strongly on dose rate, energy, and biasduring irradiation, and one rarely is able to test a device in the

Manuscript received January 13, 2003. This work was supported in part bythe Defense Threat Reduction Agency.

D. M. Fleetwood is with Vanderbilt University, Nashville, TN 37235 USA(e-mail: [email protected]).

H. A. Eisen is with ITT AE&S, Bethesda, MD 20814 USA (e-mail: [email protected]).

Digital Object Identifier 10.1109/TNS.2003.813130

laboratory in exactly the radiation environment that the part isrequired to withstand. So, correlation between laboratory to useenvironments is required. Standard radiation tests must be ca-pable of being performed with commonly available equipment,often by personnel who are not expert in the field. All these andother issues provide significant challenges to the economical as-sessment and assurance of the total-dose radiation hardness ofMOS and bipolar microelectronics.

Many reviews have been written on topics related to radiationhardness assurance in military and space radiation environments[2]–[10]; here, we will focus on issues that have driven the de-velopment and revision of standard test methods over the last20–25 years. In particular, we briefly review early test methodsthat focus on using Co-60 irradiation at a modest dose rate toprovide a reasonable surrogate for some tactical military envi-ronments [2], [3]. We show how these tests can be extended tocover the natural space environment for MOS devices and dis-cuss the special challenge of testing linear bipolar devices foruse in space. We also illustrate how scaling trends in micro-electronics technologies have changed the way hardness assur-ance is performed and how these trends will continue to affecthardness assurance in the future. A conclusion that seems in-escapable is that there will be increasingly more emphasis onmodeling and simulation and less emphasis on testing programs.Finally, an Appendix is provided that lists radiation hardness as-surance test methods.

II. HISTORICAL TRENDS

Over the last 25 years, microelectronics technologies havechanged dramatically. MOS gate lengths have dropped fromgreater than 10 to less than 0.1m, and gate dielectric layershave shrunk from 70 to less than 2 nm in leading edge com-mercial technologies. During this same time period, defense andspace system microelectronics needs also have become morediverse. For example, the natural space environment has be-come more of a concern to the radiation effects community, asopposed to the military systems that were the primary driversduring the Cold War era [2]–[12].

As ICs have become more complex and difficult to testin statistically significant numbers [13]–[15], the principlesthat underlie hardness assurance test methods have evolved inresponse. Originally, test standards were developed to applyto relatively inexpensive devices, available in relatively largenumbers, with a single predominant failure mode. Examplesof common failure modes that test methods were designedto detect are gate or field oxide threshold-voltage shifts inMOS devices and ICs, and gain degradation in linear bipolartransistors. These methods often are not as easy to apply tocomplex, expensive integrated circuits that are available onlyin limited numbers, and/or devices that exhibit multiple failure

0018-9499/03$17.00 © 2003 IEEE

FLEETWOOD AND EISEN: TOTAL-DOSE RADIATION HARDNESS ASSURANCE 553

modes. So, the standards community has had to adapt its testmethods accordingly.

A notable shift in hardness assurance philosophy is the changefromanexclusive“qualifiedpartslist(QPL)”approach[2],[10]toallowing (whenpossible)a “qualifiedmanufacturers list (QML)”approach[10],[16],[17].Theformerfocusesonrigorousandwell-definedteststhataremostlystatisticalindesign.Thelatterisamoreholistic approach that credits manufacturers who “design in” ra-diation hardness in a verified and controlled fashion and recog-nizestherelativedifficultyof“testingin”performance,reliability,and/or radiation hardness that was not first designed and deliber-ately built into a device or IC.

The QML approach to hardness assurance presumes thevariables that affect the radiation response of a particular processare under statistical process control [16], [17]. Hence, one maynot employ QML methods to attempt to evaluate the suitability ofdevicesandICsforuseinaparticularsystemif therequireddegreeof process and technology control is not present. So, one may notapply a QML approach to hardness assurance for commercialindustrial grade parts that may exhibit a degree of fortuitousradiation tolerance; one must use QPL test methods instead [10],[17], [19]. This is an example of how the variability in radiationresponse that is often observed in industrial-grade technologiesthat have not been purposefully radiation hardened can lead tohardness assurance and testing issues that are challenging to ad-dress in a cost-effective fashion [16]–[22]. However, sometimesthe savings in part costs and/or the increase in (at least initial)system functionality can justify the extra expense in testingand/or extra risk to a system [20]–[22]. In this regard, we shouldpoint out that a good hardness assurance plan is no substitute forconsidering radiation hardness assurance issues early in systemdesign. The best hardness assurance methodology in the worldcannot salvage a device that is fundamentally unsuited for the useenvironment. Early and ongoing communication between designandtestengineers isnecessary todevelopapractical,economical,and effective hardness assurance test plan.

III. SINGLE-PARAMETER HARDNESSASSURANCETESTS

Before the mid-1970s, most of the radiation hardness assur-ance literature was focused on testing bipolar devices in neutronenvironments [7]–[9], [23]. With the emergence of CMOS tech-nology, test methods were initially designed to screen primarilyfor theeffectsofnegativeMOSgateorparasitic field-oxidetran-sistor threshold-voltage shifts due to the buildup of trapped posi-tive charge in those regions. This testing is analogous in form toneutron tests intended to assess bipolar transistor gain degrada-tion [23], in the sense that each is a test in which one comparesthe degradation of a single parameter against an allowable rangeof responses.Thiscongruencein testingmethodologyallowedformany similarities in early statistics-based methods used for neu-tron and total-dose hardness assurance.

As an illustration of single point hardness assurance testingmethods, Gregory provides an early review of the failure mech-anisms in Al-gate MOS technologies [24], which is instructiveto consider briefly. Unlike the oxides of modern Si-gate de-vices, which are self-aligned and grown early in a processing se-quence, Al-gate oxides were grown toward the end of the device

process [25], [26]. No high-temperature processing was allowedafter the deposition of the Al-gate, owing to the relatively lowmelting point of Al. For these devices, the circuit failure mech-anisms, and the transistor threshold-voltage ( ) shifts thatcause them, are still quite similar to those for modern Si-gateCMOS [27], [28]:

• Failure to switchPositive or negative MOSNegative MOS

• Excessive leakageNegative MOS

• Speed reductionPositive MOS or negative MOS

• Loss of noise immunityPositive or negative MOSNegative MOS .

To understand why these effects occur, one must recognizethat oxide-trap charge is almost universally found to be net pos-itive in MOS gate oxides [29], which leads to negative thresholdvoltage shifts in both MOS and MOS transistors during ra-diation exposure. Interface trap charge is predominantly nega-tive for MOS transistors, leading to positive threshold voltageshifts during radiation exposure, and positive forMOS transis-tors, leading to negative threshold voltage shifts [30]. The timedependence of the buildup and/or annealing of oxide- and in-terface-trap charge differ greatly, which complicates the designof total dose MOS hardness assurance tests [1], [31]. However,for early Al-gate devices, with relatively thick oxides, it wasoften the case that the total-dose response was dominated bythe effects of net positive oxide-trap charge, causing theMOStransistor threshold voltage to go into depletion mode at aboutthe point of circuit failure [24]–[26]. Device-to-device leakagedue to parasitic oxides was often controlled by the use of highlydoped “guard bands,” especially in radiation hardened technolo-gies [27], [28].

In [24], Gregory compares two process lots, one with a rela-tively hardened process and another with a less radiation-hard-ened process, as illustrated in Fig. 1. The histograms reflect theunhardened process, and the approximately Gaussian distribu-tion shows the greatly improved hardened process. The smallershifts and the significant reduction in variability for the harderprocess both make hardness assurance testing much easier forthe harder process than the softer process [16], [18]–[22]. Ifone takes as a definition of failure in Fig. 1 the criterion thatthe MOS shifts less than 1 V, Fig. 2 shows a survivalconfidence for the radiation-hardened parts in this example of90% for a starting threshold voltage of 1.4 V. A confidence of

99.9% is achieved with a starting threshold voltage of 1.9 V[24]. Of course, increasing the startingMOS threshold voltagereduces the speed and initial noise margin of a CMOS IC, sothis leads to tradeoffs between one’s desires to maximize cir-cuit performance and radiation hardness. The dose rate of thetests performed in Figs. 1 and 2 is not given in [24]; however,typically, Co-60 irradiation1 is done at 50–300 rad(SiO )/s

1In this document, we typically discuss dose rates in rad(SiO)/s, which isthe most relevant parameter for MOS and bipolar technologies. Older sourcestend to use the more traditional rad(Si)/s. These are interchangeable for gammairradiation, but differ by a factor of�1.8 for 10-keV X-ray irradiation [58].


Fig. 1. Flatband voltage shifts forn-substrate capacitors processed inunhardened (histograms) or hardened (�Gaussian distribution) at SandiaNational Laboratories, using Al-gate CMOS processes. Devices were irradiatedwith Co-60 gamma rays at+10 V to 1.0 Mrad(SiO). The inset is a measure ofthe gaussianity of the distribution of threshold-voltage shifts for the hardenedprocess. (After [24], IEEE ©, used by permission.)

Fig. 2. Normalized averagenMOS transistor threshold voltage shift, asa function of the required standard deviation for the hardened technologyprocess distribution in Fig. 1, to achieve various survival probabilities afterexposure to 1.0 Mrad(SiO). The inset shows that a higher starting thresholdvoltage permits devices to survive larger threshold voltage shifts, and/or moredevice-to-device variation, without failure at the specified limits in the study.(After [24], IEEE ©, used by permission.)

[1], [31], [32]. The results of Figs. 1 and 2 likely are not easyto extrapolate to radiation environments that are much higher orlower [1], [32].

Much work using single-point definitions of failure along thelines of Fig. 1 has been performed, as described in many pub-lications [2], [4], [6], [10], [33]–[36]. There is a large body ofliterature on the statistics of acceptance and failure. These sta-tistics are based on the confidence that one has that a particularresult from a sample lot that is tested reflects the properties ofthe group of interest [4], [6], [10], [23], [33]. To improve thisconfidence level, Namenson and co-workers include informa-tion derived from parametric degradation during a step-stresstest in a more comprehensive analysis [37]–[42] in addition topass/fail statistics.

Although it is not often stated, attempts to perform hardnessassurance via nondestructive tests that correlate a preirradiationelectrical measurement with postirradiation response typicallyalso presume one has a single dominant failure mode, as

do most hardness assurance methods based on isochronalannealing techniques. An example of a nondestructive hardnessassurance technique is the correlation of preirradiationnoise to postirradiation oxide-trap charge [43]–[45]. Examplesof isochronal and/or isothermal annealing techniques areprovided in [46]–[51]. All these and other related techniquesrequire characterization testing to determine whether they arevalid for a particular process and cannot easily be appliedto devices having more than one predominant failure mode[32], [51]–[53]. Moreover, each demands a high level ofradiation-effects knowledge to implement successfully, whichmakes the tests difficult to apply in a standard fashion. So, whilethese are very useful vehicles for the study of fundamentalradiation effects, neither low-frequency noise nor isochronalannealing-based hardness assurance tests have found wide-spread use in the MOS device and IC hardness assurancecommunities.

IV. HARDNESSASSURANCESTANDARDS

The Appendix provides a comprehensive list of hardnessassurance test documents under present use. This includesU.S. military performance specifications, handbooks, and testmethods; Defense Threat Reduction Agency (DTRA) docu-ments; American Society for Testing and Materials (ASTM)guidelines and standards documents; as well as ElectronicsIndustry Alliance (EIA) and European Space Agency (ESA)test methods and guides. These documents are the results ofthe efforts of several committees from government, industry,and user groups who are stakeholders in establishing andmaintaining radiation hardness assurance standards. Alsoincluded in the Appendix are current points of contact to obtainthese documents. In the sections that follow, we discuss severalsignificant technical issues associated with total-dose hardnessassurance standards.

V. WAFER-LEVEL HARDNESSASSURANCE

There has been a lot of work in attempting to use sources thatare faster, more convenient, and/or more representative of somesystem use environments than Co-60 irradiation sources. Prob-ably the most attention has been paid to wafer-level irradiationusing a 10-keV X-ray source, which has been sold commerciallyby ARACOR [54]. Much work by a number of investigators wasperformed to correlate dose enhancement and electron-hole re-combination rates in Co-60 and 10-keV X-ray environments inthe 1980s and early 1990s [55]–[68]. This culminated in ASTMGuide F-1467 that captures well the similarities and differencesbetween 10-keV and Co-60 radiation response [69].

The 10-keV X-ray testing has been used chiefly as a processmonitor and/or test structure evaluation tool [16], [70], [71] andis typically not designated for lot acceptance in a procurementdocument. This is because 10-keV X-ray irradiation typically isdone at different dose rates than Co-60 irradiation and becausethe effects of electron-hole recombination and dose enhance-ment are often difficult to account for without detailed, com-parative testing [55]–[69]. The 10-keV X-ray irradiation canplay a critical role in an overall hardness assurance test plan buttypically must be correlated to Co-60 irradiation or a radiation


source more representative of the use environment [1], [69]. It isalso important to consider the effects of packaging and/or preir-radiation elevated temperature stress on MOS or bipolar radia-tion response, as we discuss below, since these effects can leadto changes in radiation response from that of devices on a waferimmediately after processing.

VI. MOS HARDNESSASSURANCE FORSPACE

In the mid-1980s, the phenomenon ofMOS transistorrebound was discovered during low-dose-rate irradiations andpostirradiation anneals [72], [73]. Rebound refers to positive

MOS transistor threshold voltage shifts, which are causedby excess interface-trap charge. Especially in older genera-tions of CMOS technologies, these shifts can sometimes belarge enough to cause IC failure [72], [73]. Because of thedifferences in buildup and annealing rates of MOS oxide-trapcharge (which causes negative threshold voltage shifts) andinterface-trap charge (which causes positive threshold voltageshifts in MOS transistors [1], [30], [31], [72], [73]), a singleradiation test cannot predict the radiation response of MOSdevices and circuits over a wide range of environments. Hence,tests that rely on radiation tests at a single dose rate with noprovision for making contact to real environments could leadto unsuitable parts being accepted for critical applicationsand good parts being rejected on the basis of tests that do notadequately reflect system needs.

The first standard test method that included tests for both mil-itary and space radiation environments was MIL-STD 883D,Test Method 1019.4 [31], [32], [52], [74]–[76]. Earlier versionsof this standard had narrowed the range of allowed dose ratesfrom 2–2500 to 100–300 rad(SiO)/s in the desire to ensuregreater uniformity of test results from manufacturer to manu-facturer and system to system [77], [78]. However, it was recog-nized that parts intended for use in space systems would be oper-ated at dose rates more than four orders of magnitude lower thanthose at which devices were tested. Because some device op-erating parameters improve with time (e.g., leakage, caused bynegative MOS transistor threshold voltage shifts) due to defectannealing processes (reduction in net oxide-trap charge), thisprevented some useful devices from being accepted for spaceapplication. Even more worrisome, interface traps tend to in-crease with increasing time, and their effects become more andmore dominant as they continue to grow and oxide-trap chargeis removed. This can lead to speed, timing, and noise marginerrors due to positiveMOS transistor threshold voltage shifts[72]–[76].

The above issues are illustrated clearly in Fig. 3. Here, weshow MOS transistor threshold-voltage shifts at various doserates for a mid-1980s generation radiation-hardened technologybuilt at Sandia National Laboratories [78]. At the higher rates,typical of standard dose-rate ranges prescribed in MIL-STD883C, Test Method 1019.3, the threshold voltage shifts are neg-ative, and devices tend to be limited by the buildup of net posi-tive oxide-trap charge. However, at the lowest dose rate in Fig. 3(which is still much higher than typical dose rates in space), cir-cuits are limited by the buildup of negative interface-trap charge.This same trend is also observed clearly in circuit failure levels

Fig. 3. Threshold voltage shifts versus dose and dose rate fornMOStransistors with 45 nm oxides irradiated with Cs-137 (0.1 rad(SiO)/s) orCo-60 (2–200 rad(SiO)/s) gamma rays at 10 V bias (after [31] and [78]).

for MOS ICs [72]. So, the standard range of dose rates used inMIL-STD 883C, Test Method 1019.3 were inadequate to enableaccurate prediction of the radiation response MOS devices withsignificant interface-trap densities in space [31].

MIL-STD 883D, Test Method 1019.4 addresses the aboveissues by including a “rebound test” to separately evaluate theeffects of interface traps on MOS device and IC performance[1], [31], [52]. Based on early work by Schwank and co-workers[73], rebound testing uses Co-60 irradiation, followed by a

100 C anneal, to provide an upper bound on the effects ofinterface traps on MOS response in a low-dose-rate radiationenvironment [31], [32], [52], [74]. The main test sequence forMIL-STD 883D, Test Method 1019.4 is illustrated in Fig. 4.The basic idea is that the initial Co-60 irradiation provides aworst case measure of the effects of the net positive oxide-trapcharge on MOS response in space. Then, the subsequentirradiation and elevated-temperature biased anneal provides aworst case measure of interface-trap effects on MOS responseat low dose rates. For a part to be considered suitable for bothtactical military and space radiation environments, it mustpass both tests in Fig. 4. In more recent versions of the teststandard, the Co-60 irradiation in the first block of Fig. 4can be performed at a lower dose rate and/or followed by anoptional room-temperature anneal, to gain some benefits ofroom temperature annealing [12], [77], [79] for parts that willonly be used in low-dose-rate radiation environments. Therange of alternative dose rates and the maximum time of anyroom-temperature anneal is determined by the actual dose rateof a particular system, as discussed in [74].

MIL-STD 883, Test Method 1019 provides an effective con-servative test for MOS devices intended for use in space, asillustrated in Fig. 5 [80] for a late 1980s Sandia technologythat exhibited significant rebound effects for high total doses atlow dose rates. In all cases shown here, the device degradationis worse following room-temperature irradiation and 1-week,100 C anneal than after low-dose-rate exposure [80], as re-quired to provide a conservative estimate of MOS device re-sponse in space [32]. That one may use a postirradiation annealto put an upper bound on MOS low-dose-rate response is due in


Fig. 4. Schematic diagram of main path for qualification of MOS devices andICs via MIL-STD 883D, Test Method, 1019.4. The three blocks that follow thefirst postirradiation electrical test comprise the “rebound test” in TM 1019 (after[31], [52], and [76]).

large part because “true” dose rate effects are typically not ob-served in MOS devices under worst case operating conditions[1].

While effective, the two-part irradiation and annealing testsequence in MIL-STD 883, Test Method 1019 consumes timeand resources that may no longer be justified for many moderntechnologies with ultrathin gate oxides. In very thin oxides, it isdifficult for enough interface traps to build up to cause devicefailure [81], [82]. This trend is shown in Fig. 6, in which theprojected maximumMOS transistor threshold voltage reboundis calculated theoretically, assuming one interface trap is createdfor every five electron-hole pairs created in the oxide [74].

Modern gate oxides can be more than ten times thinner thanthe 20 nm oxide considered in Fig. 6. Thus, it is clear that,except for very high total doses and/or exceedingly low noisemargins, rebound will become less and less a problem for mostmodern MOS microelectronics technologies. Indeed, gate oxidelayers are now so thin in many cases that negative thresholdvoltage shifts are also less and less a problem [81]–[83]. So,the chief concern for modern MOS devices with gate insula-tors thinner than 10 nm in space often is negative shiftsassociated with parasitic field, edge, and/or buried insulators[28], [67], [84], [85]. These can be assessed easily using thefirst part of MIL-STD 883D, Test Method 1019.4 in Fig. 4 (notincluding the rebound test), in conjunction with the single-pa-rameter statistical methods developed in early hardness assur-

Fig. 5. Read access time versus total dose for 16 k static random accessmemories built in Sandia’s 2-�m radiation-hardened process. Solid symbolsrepresent irradiation with Cs-137 gamma rays at 0.2 rad(SiO)/s; open circlesare device response after irradiation according to MIL-STD 883D, TestMethod, 1019.4 rebound test conditions specified in Fig. 4 (after [79].)

Fig. 6. Maximum positivenMOS transistor threshold voltage shift as afunction of dose and oxide thickness, assuming a charge yield of�80% andan interface-trap generation efficiency of 20% per electron-hole pair that isgenerated and escapes recombination (after [74]).

ance tests [2], [4], [6], [10], [33]–[36]. So, device scaling hasmade MOS hardness assurance testing easier to do for moderndevices in recent years. Older technologies with thicker gate ox-ides still require the full testing sequence in Fig. 4. Of course,if one does not know the oxide thickness of a particular deviceor IC being tested, it is difficult to take advantages of simpli-fications in testing sequence from which one could otherwisebenefit, showing the necessity of understanding at least somebasic processing details of devices intended for use in radiationenvironments.

VII. B IPOLAR HARDNESSASSURANCE FORSPACE

For moderate and high-dose-rate radiation environments, onecan almost always use similar hardness assurance tests to eval-uate the total-dose response of MOS and bipolar devices [32],[52], [86], [87]. However, this is not the case for low-dose-rateenvironments. The ionizing radiation response of modern linearbipolar devices and ICs is mostly a function of oxide and inter-face traps in the parasitic insulator that overlays the base-emitterjunction, as shown schematically for an npn transistor in Fig. 7[87], [88]. In 1991, Enlow and co-workers discovered a signifi-cant enhancement in gain degradation at low dose rates for linearbipolar devices that could not be bounded by testing using theirradiation-and-anneal methodology of MIL-STD 883D, Test


Fig. 7. Cross section of an npn bipolar transistor, representative of devicesused in modern BiCMOS technologies (after [88]).

Method 1019.4 [89]. Follow-on studies have identified othernpn and pnp transistors that show similar, or even larger, exam-ples of enhanced low-dose-rate sensitivity (ELDRS) [87]–[96]and also have confirmed the presence of ELDRS effects at alevel similar to that expected from ground tests in space [95].

Recent studies suggest that the differences between MOS andbipolar responses occur because, in contrast to MOS devicesthat typically do not show “true” dose-rate effects, linear bipolardevices frequently show effects at low dose rates that cannot besimulated effectively with higher rate irradiation and postirradi-ation anneal [87], [89], [97]–[99]. This is likely due to signifi-cant space charge effects that develop during high-dose-rate ir-radiation of bipolar devices and ICs that fundamentally alter therecombination, transport, and trapping of the charged species(holes, electrons, and protons) that lead to degraded bipolar radi-ation response [97]–[100]. In MOS devices, electric fields tendto be large and monotonic in direction (vertical, from gate tosubstrate) for worst case operating conditions in a radiation en-vironment. For bipolar devices, the fields are small and non-monotonic in direction. So, one can easily achieve conditionsin bipolar devices for which the electric fields are totally dif-ferent for high- and low-dose-rate irradiations [97], [101]. Theresulting enhanced low-dose-rate sensitivity is much more dif-ficult to account for with standard test methods than is reboundin MOS technologies [52], [87].

The magnitude of the ELDRS problem in several representa-tive devices can be seen in Fig. 8, for example. Here, it is shownthat the response of some devices at low dose rates is more thana factor of five times larger than the response of devices irra-diated at high dose rates. So, this is a very serious problem forradiation hardness assurance for many low-dose-rate radiationenvironments.

Significant progress has been made in the understanding ofELDRS mechanisms [96]–[117] and the factors that influencewhether a particular device exhibits ELDRS or not. The influ-ences of hydrogen [98]–[100] and/or mechanical stress due tochip passivation layers [117] appear to be especially significant.Revised versions of military and commercial test methods areavailable (most notably, ASTM Guide F-1892 [118], [119], andsoon a revised version of MIL-STD 883, Test Method 1019)to help users assess the suitability of bipolar devices for spaceapplications. At present, two primary strategies are availablefor hardness assurance testing of bipolar devices known or sus-pected of exhibiting ELDRS. The first is an actual low-dose-rate

Fig. 8. Relative damage enhancement, normalized to degradation at 50rad(SiO )/s, for several linear bipolar microcircuits. (After [92], IEEE © 1994,used by permission.)

test. This is based on the tendency, at least in most types of de-vices, for the radiation response to saturate in magnitude at alow enough dose rate (e.g.,10 mrad(SiO)/s), at least approxi-mately [118]–[120]. With suitable margin to account for the pos-sibility that device response at still lower rates in space may beworse yet, low-dose-rate irradiation is probably the best methodof choice for linear bipolar radiation hardness assurance [119],especially for fairly low-dose applications where testing can beperformed at a rate of 10 mrad(SiO)/s in reasonable amountof time. Unfortunately, at a dose rate of 10 mrad(SiO)/s, onecan deliver only 864 rad(SiO) to a device in a day. So underthese conditions 10 krad(SiO) irradiation takes 11.5 days, and100 krad(SiO) irradiation takes nearly four months to com-plete. Moreover, in tests involving prolonged irradiation expo-sures, there is also an increased risk that, if something goeswrong logistically with a test (e.g., there is a power outage, asignificant static glitch, etc.), this can have a major impact onsystem schedules. For a critical application where a device mustbe assured of working for the life of the system, this level of timeand expense may be warranted. However, there is a natural de-sire to try to find a shorter more cost-effective testing approach.

One approach to try to accelerate hardness assurance testingfor space applications that is effective for many (but not all)linear bipolar devices and ICs is elevated-temperature irradia-tion [97], [106], [111], [118], [119]. Irradiating either an MOSor a bipolar device at a temperature that is significantly higherthan the maximum temperature at which a system is expectedto operate (for the majority of its life) can accelerate the an-nealing of oxide-trap charge and the buildup of interface traps[97], [106], [121], [122]. With MOS devices, elevated temper-ature annealing also accomplishes these goals successfully, butthis is not typically the case for bipolar devices [89], [98], [104],[115], [119]. However, for many part types, degradation occursat a level during high-temperature irradiation that is comparableto that during low-dose-rate irradiation at room temperature, es-pecially if one uses appropriate safety factors in setting allowedparametric and functional failure levels during the high-temper-ature irradiations [106], [111], [118], [119], and/or performs the


Fig. 9. Excess base current, which is proportional to gain degradation, as afunction of irradiation temperature for 294 rad(SiO)/s irradiations of lateralpnp bipolar transistors, as compared to low dose rate response. (After [106].)

high-temperature irradiation at a dose rate of1–10 rad(SiO)/s[119], [123].

A comparison between room-temperature and high tem-perature irradiation is illustrated in Fig. 9 [106]. For thesedevices, irradiation at 150 C at 300 rad(SiO)/s pro-vides a fairly close approximation of device degradation at

1 mrad(SiO)/s (the striped band at the top of the figure).However, for other types of devices, such excellent agreementbetween high-temperature irradiation and low-rate response isnot always observed [108], [119], and there is definite risk ofinterface-trap annealing above 100C [31], [52]. The benefitsand risks of using high-temperature irradiation for linearbipolar hardness assurance have been discussed often in theliterature [97], [106], [111], [118], [119], [123]–[126], and aseries of preliminary recommendations are included in ASTMGuide F-1892 [118], [119]. At present, efforts to standardizeon a dose-rate and temperature for high-temperature irradiationof linear bipolar devices are focused on a temperature of

100 C and a dose rate of 1–10 rad(SiO)/s [118], [119],[125]. But, this guidance still should be regarded as somewhatpreliminary, and the safest course in space system design is totry one’s best to avoid using linear bipolar devices that exhibitELDRS whenever it is possible to do so and still meet systemrequirements [20], [21], [96], [127].

VIII. H IGH-DOSEHIGH-RATE ENVIRONMENTS

At present, military and commercial standards do not addressthe needs of some types of (primarily military) radiation envi-ronments in which a significant amount of dose is delivered ata rate much greater than1 krad(SiO)/s. While there is someguidance in the literature for how one might design a hardnessassurance test plan for these kinds of systems [1], [52], [80], itis usually expected that these systems will either perform teststo simulate the actual radiation environment or use modelingand simulation to develop surrogate tests that are easier and lessexpensive to perform. The 10-keV X-ray testing can play a sig-nificant role in this regard [1], [52], [80] because the dose rateavailable is higher than that of typical laboratory Co-60 radia-

Fig. 10. Input bias current as a function of preirradiation elevated temperaturestress (PETS) time for LM111 devices irradiated to 100 krad(SiO) at 0.1 or50 rad(SiO)/s with all pins grounded. One group of the devices irradiated at50 rad(SiO)/s also received an unbiased anneal at room temperature for a timeequal to that elapsed during the lower rate exposures (after [115]).

tion sources by up to ten times or more. However, it is presumedthat there are knowledgeable engineers and scientists designingand helping to evaluate the tests, as the lack of validated teststandards otherwise would lead to a higher risk to these sys-tems.

IX. PREIRRADIATION ELEVATED TEMPERATURESTRESS

Until fairly recently, there was at least the tacit assumptionthat the total dose hardness of a MOS or bipolar device wasfixed upon the last high-temperature (greater than850 C)step in device processing. However, recently there has beena lot of evidence that, for many part types, total dose radi-ation response can change during postprocessing heating totemperatures of 100–400 C, and/or aging after deviceprocessing [115], [116], [128]–[134]. Of special concern forhardness assurance test methods are accounting for the effectsof burn-in and packaging environments on radiation hardness[115], [117], [129]–[131], which can be quite significant.For example, Shaneyfelt and co-workers have found a stronginterdependence between ELDRS and preirradiation elevatedtemperature stress (PETS) effects. This is illustrated in Fig. 10,which shows a dramatic difference between the magnitudesof ELDRS effects exhibited by bipolar devices, depending onthe type of PETS the device had received [115]. Significantchanges in radiation hardness with burn-in are also reported forsome types of MOS devices and ICs as well, as illustrated inFig. 11. PETS effects appear to be quite sensitive to hydrogenand/or mechanical stress in the devices [115], [117], [128],[134], each of which can be affected by the way a device ispackaged and/or burned-in before system use.

The sensitivity of microelectronic radiation response to post-processing temperature and stress is a significant challenge tohardness assurance. For example, a device might show accept-able radiation response at the wafer level when one performs10-keV X-ray irradiation, but unacceptable response after thedevice is packaged, regardless of whether there are any other dif-ferences in radiation energy, dose rate, bias, etc. Changes in radi-


Fig. 11. Static power supply leakage for octal buffer/line drivers with orwithout preirradiation burn in at 150C for one week. Devices were irradiatedwith Co-60 gamma rays at 90 rad(SiO)/s at 5.5 V (after [129]).

ation response as a device ages in system use and/or storage is aclosely related concern. Presently, MIL-STD 883, Test Method1019 and ASTM Guide F-1892 require the irradiation of devicesin the packages in which they are to be fielded, after exposureto the same thermal treatments they will receive in their use his-tory, unless the devices are demonstrated not to be sensitive toPETS effects [115], [131], [132]. But, this continues to be anarea of active study, both from mechanisms and hardness assur-ance standpoints.

X. FUTURE TRENDS IN HARDNESSASSURANCE

As technologies change, new effects like ELDRS and PETSare almost certain to be found. A continuing trend is for de-vices to have smaller feature sizes and to be more complex indesign. This makes it virtually impossible to define a reasonableset of test vectors and/or bias conditions that ensure approxi-mately worst case response for the device or IC. Modeling andsimulation are increasingly necessary to do analysis of circuitresponse before and after irradiation to identify operating con-ditions under which a circuit may be expected to be most vul-nerable to radiation exposure [13]–[15], [28]. This clearly willbe an area of increasing study.

Most MOS radiation hardness assurance test techniquesare designed under the presumption that the gate dielectric isthermal SiO. It is already known that other dielectrics likeAl O , Si N , and HfO and Hf silicates can have differentradiation responses than thermal SiO[5], [135], [136]. So,assumptions made in relating irradiation and annealing tolow-dose-rate response for MOS devices, for example, likelywill have to be reevaluated when these kinds of insulatinglayers become more common in microelectronics.

Farther into the future, there is presently a lot of speculationthat non-Si based nanotechnologies and/or biologically inspireddevices may replace or augment the capabilities of Si-basedelectronics for some critical high-performance sensing andcomputing environments. Some of these technologies maybe very radiation tolerant; others may be extremely radiationsensitive. One can make the case that, for small enough device

dimensions, the concept of total dose response may becomeless useful. Instead, every radiation interaction may have tobe treated as a single event, as opposed to in a statistical,cumulative fashion, as one typically does in total dose testing.An example of this on a somewhat larger size scale is theeffects of “microdose” on highly scaled electronics, in whicha single cosmic ray can deposit enough local energy to causea hard error in a memory [137]. We expect similar and evenmore challenging effects to be observed in nanotechnologiesand biologically inspired computing elements. These and otheremerging areas are expected to be quite challenging from thestandpoint of basic mechanisms and hardness assurance, andthe sensitivity of some kinds of extremely small devices maylimit their use in high radiation environments like space [138].

XI. CONCLUSION

Total-dose radiation hardness assurance for many tacticalmilitary and low-dose-rate environments can be performed withhigh confidence for MOS devices using existing standard testmethods, as long as devices are tested in the packages used inthe system and have experienced an equivalent thermal history.For linear bipolar devices that exhibit ELDRS effects, therecan be significantly greater uncertainty in the ability of eitherlow-dose-rate testing or elevated-temperature irradiation to bean adequate hardness assurance test method. In either case,hardness assurance testing is simplified if considered as early aspossible in system design, as sometimes the success or failureof one’s hardness assurance test plan is determined almostentirely by the selection of the part types to be evaluated. In thefuture, continued scaling down of device feature sizes and theintroduction of new technologies into radiation environmentswill make radiation hardness assurance an ongoing challenge.There will be few short cuts to an understanding of basic deviceradiation response. This will increasingly include a heavierreliance on modeling and simulation to understand how toimprove device response and/or design improved hardnessassurance tests. Validation and verification testing will alwaysbe required at one level or another to check for variations indevice response as well as to continue to look for unexpectedfailure mechanisms.

APPENDIX

The following are radiation hardness assurance test methods,guidelines, and standards. Also included is present contact in-formation from which copies may be obtained. This list updatesthat provided in [2]; this list is updated at the Web site of theSpace Parts Working Group’s Hardness Assurance Committee:http://www.spwghac.org.

Military Performance Specifications

• 19 500, General Specification for Semiconductor Devices.• 38 510, General Specification for Microcircuits.• 38 534, Performance Specification for Hybrid Microcir-

cuits.• 38 535, General Specification for Integrated Circuits (Mi-

crocircuits) Manufacturing.


Military Handbooks

• 814, Ionizing Dose and Neutron Hardness AssuranceGuidelines for Microcircuits and Semiconductor Devices.

• 815, Dose Rate Hardness Assurance Guidelines.• 816, Guidelines for Developing Radiation Hardness As-

sured Device Specifications.• 817, System Development Radiation Hardness Assurance.• 339, Custom Large Scale Integrated Circuits, Develop-

ment and Acquisition for Space Vehicles.• 1547, Electronic Parts, Materials, and Processes for Space

and Launch Vehicles.• 1766, Nuclear Hardness and Survivability Program

Guidelines for ICBM Weapon Systems and Space Sys-tems.

Military Test Methods

In MIL-STD-750 (Test Methods for Semiconductor Devices)

• 1017, Neutron Irradiation Procedure.• 1019, Steady State Ionizing Radiation (Total Dose) Test

Procedure.• 1032, Package Induced Soft Error Test Procedure (Due To

Alpha Particles).• 1080, Single Event Burnout and Single Event Gate Rup-

ture.• 3478, Power MOSFET Electrical Dose Rate Test Method.• 5001, Wafer Lot Acceptance Testing.

In MIL-STD-883 (Test Methods and Procedures for Micro-electronics)

• 1017, Neutron Irradiation Procedure.• 1019, Steady State Ionizing Radiation (Total Dose) Test

Procedure.• 1020, Dose Rate Induced Latchup Test Procedure.• 1021, Dose Rate Upset Testing of Digital Microcircuits.• 1023, Dose Rate Response of Linear Microcircuits.• 5004, Screening Procedures.• 5005, Qualification and Quality Conformance Procedures.• 5010, Test Procedures for Complex Monolithic Microcir-

cuits.

Military standards, specifications, and handbooks can beviewed and ordered from the Web site of the DoD Docu-ment Automation and Production Services (DAPS), Bldg.4/D (DPM-DODSSP), 700 Robbins Ave., Philadelphia, PA19111-5094 USA. Their URL is http://www.dodssp.daps.mil.For assistance, one can phone 215-697-2179 or Fax—1462.Most can also be viewed and downloaded at DSCC’s web site,http://www.dscccols.com/Programs/MilSpec/default.asp.

DTRA Documents

• DNA-H-93-52, Program Management Handbook on Nu-clear Survivability.

• DNA-H-95-61, Transient Radiation Effects on Electronics(TREE) Handbook.

• DNA-H-93-140, Military Handbook for Hardness Assur-ance, Maintenance and Surveillance (HAMS).

DTRA documents can be obtained from the Defense Tech-nical Information Center (DTIC), phone 800-225-3842.

ASTM Standards

The following are test and measurement standards. They areunder the oversight of ASTM Subcommittee F1.11, Quality andHardness Assurance; Chairman, Allan Johnston, 818-354-6425.

• F448, Test Method for Measuring Steady-State PrimaryPhotocurrent.

• F526, Test Method for Measuring Dose for Use in LinearAcceleration Pulsed Radiation Effects Tests.

• F528, Test Method of Measurement of Common-EmitterD-C Current Gain of Junction Transistors.

• F615, Practice for Determining Safe Current Pulse Oper-ating Regions for Metallization on Semiconductor Com-ponents.

• F616, Test Method for Measuring MOSFET DrainLeakage Current.

• F617, Test Method for Measuring MOSFET LinearThreshold Voltage.

• F676, Test Method for Measuring Unsaturated TTL SinkCurrent.

• F744, Test Method for Measuring Dose Rate Thresholdfor Upset of Digital Integrated Circuits.

• F769, Test Method for Measuring Transistor and DiodeLeakage Currents.

• F773, Practice for Measuring Dose Rate Response ofLinear Integrated Circuit.

• F980, Guide for the Measurement of Rapid Annealing ofNeutron-Induced Displacement Damage in Silicon Semi-conductor Devices.

• F996, Test Method for Separating an Ionizing Radiation-Induced MOSFET Threshold Voltage Shift into Compo-nents Due to Oxide Trapped Holes and Interface StatesUsing the Subthreshold Current-Voltage Characteristics.

• F1190, Practice for the Neutron Irradiation of UnbiasedElectronic Components.

• F1192, Guide for the Measurement of Single Event Phe-nomena (SEP) Induced by Heavy Ion Irradiation of Semi-conductor Devices.

• F1262, Guide for Transient Radiation Upset ThresholdTesting of Digital Integrated Circuits.

• F1263, Test Method for Analysis of Overtest Data in Ra-diation Testing of Electronic Parts.

• F1467, Guide for Use of an X-Ray Tester (10 keV Pho-tons) in Ionizing Radiation Effects Testing of Semicon-ductor Devices and Microcircuits.

• F1892, Guide for Ionizing Radiation (Total Dose) EffectsTesting of Semiconductor Devices.

• F1893, Guide for the Measurement of Ionizing Dose-RateBurnout of Semiconductor Devices.

The following are radiation dosimetry standards. They areunder the oversight of ASTM Subcommittee E10.07; Chairman,Dave Vehar, 505-845-3414.

• E265, Test Method for Measuring Reaction Rates andFast-Neutron Fluences by Radioactivation of Sulfur-32.

• E496, Test Method for Measuring Neutron Fluence Rateand Average Energy from 3H(d,n)4He Neutron Genera-tors by Radioactivation Techniques.


• E665, Practice for Determining Absorbed Dose VersusDepth in Materials Exposed to the X-Ray Output of FlashX-Ray Machines.

• E666, Practice for Calculating Absorbed Dose fromGamma or X Radiation.

• E668, Practice for Application of ThermoluminescenceDosimetry Systems for Determining Absorbed Dose inRadiation-Hardness Testing of Electronics.

• E720, Guide for Selection of a Set of Neutron-ActivationFoils for Determining Neutron Spectra Used in Radiation-Hardness Testing of Electronics.

• E721, Method for Determining Neutron Energy Spectrawith Neutron-Activation Foils for Radiation HardnessTesting of Electronics.

• E722, Practice for Characterizing Neutron Energy FluenceSpectra in Terms of an Equivalent Monoenergetic NeutronFluence for Radiation-Hardness Testing of Electronics.

• E1026, Methods for Using the Fricke Dosimeter to Mea-sure Absorbed Dose in Water.

• E1249, Practice for Minimizing Dosimetry Errors in Ra-diation Hardness Testing of Silicon Electronic DevicesUsing Co-60 Sources.

• E1250, Test Method for Application of Ionization Cham-bers to Assess the Low Energy Gamma Component ofCobalt-60 Irradiators Used in Radiation-Hardness Testingof Silicon Electronic Devices.

• E1854, Practice for Assuring Test Consistency in Neutron-Induced Displacement Damage of Electronic Parts.

• E1855, Method for Use of 2N2222 Silicon Bipolar Tran-sistors as Neutron Spectrum Sensors and DisplacementDamage Monitors.

• E1894, Guide for Selecting Dosimetry Systems for Appli-cation in Pulsed X-Ray Sources.

The following are fiber optic test standards. They areunder the oversight of ASTM Subcommittee E13.09, OpticalFibers for Molecular Spectroscopy; Chairman, Tuan Bo-Dinh,423-574-6249.

• E1614, Guide for Procedure for Measuring Ionizing Radi-ation-Induced Attenuation in Silica-Based Optical Fibersand Cables for Use in Remote Fiber-Optic Spectroscopyand Broadband Systems.

• E1654, Guide for Measuring Ionizing Radiation-InducedSpectral Changes in Optical Fibers and Cables for Use inRemote Raman Fiber-Optic Spectroscopy.

ASTM standards can be purchased from ASTM, 100 BarrHarbor Dr., West Conshohocken, PA 19428-2959 USA. Phone610-832-9585. Portions of each standard can be viewed athttp://www.astm.org.

EIA Test Methods and Guides

• EIA/JESD-57, Procedures for the Measurement of Single-Event Effects in Semiconductor Devices from Heavy IonIrradiation.

• JESD-89, Measurement and Reporting of Alpha Particlesand Terrestrial Cosmic Ray-Induced Soft Errors in Semi-conductor Devices.

• EIA/JEP-133, Guideline for the Production and Acquisi-tion of Radiation-Hardness Assured Multichip Modulesand Hybrid Microcircuits.

• EIA/TIA-455-64 (FOTP-64), Procedure for MeasuringRadiation-Induced Attenuation in Optical Fibers andCables.

Some EIA/JEDEC standards can be obtained from GlobalEngineering Documents, 15 Inverness Way East, Engle-wood CO 80112-5704. Phone 800-854-7179. Otherwise seehttp://www.jedec.org or http://www.eia.org.

ESA Test Methods and Guides

• ESA/SCC Basic Specification no. 22900, Total DoseSteady-State Irradiation Test Method.

• ESA/SCC Basic Specification no. 25100, Single Event Ef-fects Test Method and Guidelines.

• ESA PSS-01-609, The Radiation Design Handbook.

ESA documents can be obtained from ESA/SCC Secretariat(TOS-QCS), ESTEC P.O. Box 299, 2200 AG Noordwijk, TheNetherlands.

ACKNOWLEDGMENT

The authors would like to thank L. Cohn of the DefenseThreat Reduction Agency for sustained support of hardnessassurance activities, as well as their professional colleaguesand the many members of the DoD, ASTM, EIA, and ESAcommittees who have devoted their time and efforts in supportof defining hardness assurance standards.

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