today modeling, design, and optimizationese370/fall2019/handouts/lec... · 2019. 10. 21. · pass...
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ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Lec 20: October 21, 2019 Pass Transistor Logic, Pt2
Penn ESE 370 Fall 2019 - Khanna
Today
! Pass Transistor Circuit " Cdiff>0 " Output levels " Cascading
" Series pass transistors? " Delay
! Start on Distributed RC " Analyzing delay for pass-tr designs
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Previously: Two XOR Gates
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Cascaded Pass Gates
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Delay A=1, B=0, Cdiff=0?
! What’s the equivalent RC circuit?
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2C0
2C0
Delay A=1, B=1, Cdiff=0?
! What’s the equivalent RC circuit? " What are we ignoring?
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2C0 2C0
2C0
2
Cdiff>0
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Contact/Diffusion Capacitance
! Cj – diffusion depletion ! Cjsw – sidewall capacitance ! LS – length of diffusion
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€
Cdiff = C jLSW +C jsw 2LS +W( )
LS
Cdiff ≈WCdiff 0 =W ⋅γC0
Cdiff 0 ≈ γC0Define:
Penn ESE 370 Fall 2019 - Khanna
First Order Model
! Switch " Loads all terminals capacitively
" Draw no steady-state current for a CMOS gate " Does not impact steady-state output voltage " Impacts Settling time/Delay
" Has finite drive strength " Could form voltage divider with resistive load " Impacts Settling time/Delay
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C0R0
Cdiff0
Cdiff0
First Order Delay
! R0 = Resistance of minimum size NMOS device ! C0 = gate capacitance of minimum size NMOS
device ! Cdiff0 = diffusion capacitance on minimum size
NMOS " Cdiff0 =γC0
! Rdrive = R0/W ! Cg = WC0
! Cdiff = WCdiff0
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Inverter Delay
! Delay driving another (min size) inverter? " Include Cdiff=γCg=WγC0
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W=1
Penn ESE 370 Fall 2019 - Khanna
Delay A=1, B=1, Cdiff=γC0? (W=1)
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2C0
3
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! What’s the equivalent RC circuit?
Penn ESE 370 Fall 2019 - Khanna
Delay A=1, B=1, Cdiff=γC0? (W=1)
2C0+3Cdiff0 2C0+2Cdiff0
2C0
Bonus
! What does this do?
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A
B
Penn ESE 370 Fall 2019 - Khanna
A B Y
0 0
0 1
1 0
1 1
Bonus
! What does this do?
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A
B
More examples in the text Penn ESE 370 Fall 2019 - Khanna
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
Cascading Pass Transistors
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Chain without Inverters
! What if we did this?
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/a
a
! Extract key path
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Chain without Inverters
Penn ESE 370 Fall 2019 - Khanna
/a
a
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Focus on Pass Transistor
! Vgs? ! Operation mode? ! Current flow?
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Preclass: t=0 (after Vin transition 1#0)
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Preclass: t=∞ (after Vin transition 1#0)
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Voltage of Chain
! What is voltage at output?
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How compare
! Compare
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DC Analysis – chain of 3 vs length of 3
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DC Analysis – chain of 6
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Conclude
! Can chain any number of pass transistors and only drop a single Vth
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…
Penn ESE 370 Fall 2019 - Khanna
Transient
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Transient: Zoomed Closeup
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Capacitance
! What is output capacitance per stage? " I.e. What is the capacitance at output y?
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/a
a
Delay Setup
! What does RC circuit look like?
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/a
a
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Pass TR Tree
! What if we did this?
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/c
/c
c /x
x
/z
z /a
a
/d
d
Path
! What’s different about this?
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/c
/c
c /x
x
/z
z /a
a
/d
d
Gate Cascade?
! What are the voltages?
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Conclude
! Cannot cascade degraded inputs into gates.
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Distributed RC (setup)
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What is response?
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What is response?
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What is response?
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SPICE Response
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1 2 3 4 5 6 7 8 9 10 (ns)
SPICE Response
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1 2 3 4 5 6 7 8 9 10 (ns)
Intuition
! Look at series of R’s on path " Must move Q=V(ΣC) across each R
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Elmore Delay: Distributed RC network
! The delay from source s to node i " N = number of nodes in circuit
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Elmore Delay: Distributed RC network
! The delay from source s to node i " N = number of nodes in circuit
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Rik = Rj∑ ⇒ (Rj ∈ [path(s→ i)∩ path(s→ k)])
Penn ESE 370 Fall 2019 - Khanna
τ Di = CkRikk=1
N
∑
Elmore Delay: Distributed RC network
! The delay from source s to node i " N = number of nodes in circuit
! Ex.
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Rik = Rj∑ ⇒ (Rj ∈ [path(s→ i)∩ path(s→ k)])
Penn ESE 370 Fall 2019 - Khanna
τ Di = CkRikk=1
N
∑
τ Di ?
Elmore Delay: Distributed RC network
! The delay from source s to node i " N = number of nodes in circuit
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τ Di = CkRikk=1
N
∑
τ Di =C1(R1)+C2 (R1)+C3(R1 + R3)+C4 (R1 + R3)+Ci (R1 + R3 + Ri )
Rik = Rj∑ ⇒ (Rj ∈ [path(s→ i)∩ path(s→ k)])
Elmore Delay: Practice
! The delay from source s to node i " N = number of nodes in circuit
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Rik = Rj∑ ⇒ (Rj ∈ [path(s→ i)∩ path(s→ k)])
Penn ESE 370 Fall 2019 - Khanna
τ Di = CkRikk=1
N
∑
Idea
! There are other circuit disciplines ! Can use pass transistors for logic
" Even chains of pass transistors " Mostly gives area win, sometimes gives delay win
" Will talk more about delay on Monday
! Do not cascade as easily as CMOS ! Additional diffusion capacitance leads to distributed
RC networks " More next lecture
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Logic Types
! CMOS Gates " Dual pull-down and pull-up networks, only one enabled at a time " Performance of gate is strong function of the fanin of gate
" Techniques to improve performance include sizing, input reordering, and buffering (staging)
! Ratioed Gates " Have active pull-down (-up) network connected to load device " Reduced gate complexity at expense of static power asymmetric transfer
function " Techniques to improve performance include sizing to improve noise margins and reduce
static power
! Pass Gates " Implement logic gate as switch network for reduced area and load
capacitance " Long cascades of switches result in quadratic increase in delay " Also suffer from reduced noise margins (VT drop)
" Use level-restoring buffers to improve noise margins
! Dynamic logic … coming up soon 48 Penn ESE 370 Fall 2019 – Khanna
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Admin
! Project " Due Friday " Use Piazza and office hours
" Extra Tania office hours T 2-4pm
" Should be working hard on project " Not enough to know what to do. You have to actually do it.
" Rewarding experience and worth the time once you get it " Design takes time
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