resistance capacitance
TRANSCRIPT
Dr. Ahmed H. Madian-VLSI 1
Very Large Scale Integration ((VLSI
Dr. Ahmed H. [email protected]
Lecture 3
Dr. Ahmed H. Madian-VLSI 2
Contents Wiring tracks Latch-up Circuit characterization & performance Resistance estimation Capacitance estimation Inductance estimation Delay estimation
Simple RC model Penfield-Rubenstein Model
Delay minimization techniques Transistor sizing Distributed drivers Large driver
Wiring techniques
Dr. Ahmed H. Madian-VLSI 3
Wiring Tracks A wiring track space required for a wire
4λ width, 4λ spacing from the neighbor=8 λ Transistor consumes one wiring track
4λ
4λ4λ
4λ
Dr. Ahmed H. Madian-VLSI 4
Area Estimation Estimate Area by Counting wiring tracks
Multiply by 8 (4Width + 4Spacing) to express in λ
40λ
32λ
Dr. Ahmed H. Madian-VLSI 5
Latch up Latch up is a condition that can occur in a circuit
fabricated in a bulk CMOS technology.
+N +N +P +P
VDDGND
N-well
P
N
P
N
VDD
Dr. Ahmed H. Madian-VLSI 6
P-substrate
Latch up Prevention This could be corrected by:
Include an N-well contact every time a pFET is connected to VDD
Include an p-substrate contact every time a NFET is connected to GND
+N +N +P +P
VDDGND
N-well
VDDGND
Dr. Ahmed H. Madian-VLSI 7
Circuit characterization &performance
Resistance estimation Capacitance estimation Inductance estimation Delay estimation
Dr. Ahmed H. Madian-VLSI 8
Resistance estimation Resistance of uniform slab
can be given as,
Where ρ = resistivity t= thickness
l= conductor length w=conductor widthor,
Rs is the sheet resistance Ω/ð
ohmsw
l
tR .
ρ=
ohmsw
lRR s .=
I
l
t
w
Dr. Ahmed H. Madian-VLSI 9
(.Resistance estimation (cont Resistance of certain layers
1K 5KN-well24Silicide 35Diffusion n80Diffusion p
15100Poly0.03metal
Rs (Ω/ð)Material
Dr. Ahmed H. Madian-VLSI 10
Resistance estimation For MOSFET channel resistance
Rchannel = RSheet (L/W)
where Rsheet = 1/µCOX(Vgs-Vt)
For P and n channels
Rsheet = 1000 ->30,000 Ω/ð
+N + NL
channel
L
W
Dr. Ahmed H. Madian-VLSI 11
(.Resistance estimation (cont Resistance of non rectangular regions
W1
W2
W2
W1
W2
W1
L
Ratio = 2L/(L+2W1)
L
WRatio =L/W Ratio =L/W
W2
W1
L
Ratio =W1/W2
W2 W2
W1
W1
Ratio =W2/W1
Dr. Ahmed H. Madian-VLSI 12
Inverter resistance estimation CMOS inverter (no static
current) Switching current
VDD
Vin
VGS
VOUT = VDSIL
IDS
MP
MN
Vin Vout
VDD
Rs,p (L/W)
Rs,n (L/W)
351025
1
,,max
,,
max
DDDD
nsps
DD
nsps
DD
total
DD
VV
RR
VI
WLforW
LR
W
LR
V
R
VI
=+
=+
=
==
+==
35.
2
maxDDV
VIlosspowerswitching DD ==
Dr. Ahmed H. Madian-VLSI 13
Circuit characterization &performance
Resistance estimation Capacitance estimation
Transistor capacitance Routing capacitance
Inductance estimation Delay estimation
Dr. Ahmed H. Madian-VLSI 14
Capacitance estimation
The dynamic response of MOS systems strongly depends on the parasitic capacitances associated with the MOS device. The total load capacitance on the output of a CMOS gate is the sum of: gate capacitance (of other inputs connected to out) diffusion capacitance (of drain/source regions) routing capacitances (output to other inputs)
gate
drain
source
substrate
CGD
CGS CSB
CDB
CGB
Dr. Ahmed H. Madian-VLSI 15
(.Capacitance estimation (cont
Gate capacitance Diffusion capacitance Routing capacitance
Cdiff >Cpoly>Cm1>Cm2
+nsubstrate
gate
insulatorCgate
C.diff
gate
+nsubstrate
Metal layer
Crouting
Dr. Ahmed H. Madian-VLSI 16
Capacitance estimation
In general, capacitance could be calculated using
d
A
d
AC ro ... εεε ==
oxro
areaunit Cd
C == εε ./ d
Dr. Ahmed H. Madian-VLSI 17
Gate Capacitance
Cg = Cgs + Cgd + Cgb
Dr. Ahmed H. Madian-VLSI 18
(.Capacitance estimation (cont Diffusion capacitance (source/drain)
SourceDiffusion
Area
DrainDiffusion
Area
b
a
Gateinsulator
CJP
Side wall capacitance
CJa
area capacitance
PCACC sidewallsdAreaddiffs .. ,,, +=
Where A = area and p = perimeters
Dr. Ahmed H. Madian-VLSI 19
Routing capacitance
single conductor capacitance multiple conductor capacitance
Dr. Ahmed H. Madian-VLSI 20
(.Capacitance estimation (cont
Metal 1
substrate
Fringing capacitance
+++
Π+−
=
2222
1ln
22
t
h
t
h
t
hh
tw
Ctotal ε
Routing capacitance: a) single conductor capacitance
w h
t
Half cylinders
Dr. Ahmed H. Madian-VLSI 21
(.Capacitance estimation (cont
Metal 2
Metal 1
substrate
C12C2
C1
C1C2
C12
Metal 2Metal 1Vin Vout
122
12.CC
CVV inout
+∆=∆
Routing capacitance: b) multiple conductor capacitance
Dr. Ahmed H. Madian-VLSI 22
Multilayer capacitance calculations
Example: given the layout shown in the figure calculate the total capacitance at source and gate given that:
Cmetal/Area = 0.025µF/µm2
Cpoly/Area = 0.045µF/µm2
CGate/A = 0.7 fF/µm2
Cd,a/A = 0.33fF/µm2
Cd,side/L = 2.6fF/µm
λ = 5.1µm
100λ
3λ CM
4λ
4λ
2λ
3λ
2λ
4λ4λ 2λ
CMP
CP1
Cgate
CP1
Dr. Ahmed H. Madian-VLSI 23
Solution100λ
3λ CM
4λ
4λ
2λ
3λ
2λ
4λ4λ 2λ
CMP
CP1
Cgate
CP1
Source capacitance
CS,diff = Cd,A . A + Cd,side walls . P
A = 4λ * 3λ = 12 λ2
P = 2*(4λ + 3λ)=14 λ
So, CS, diff = 0.33* 12 λ2+2.6* 14 λ=63.51fF
Cs
S D
G
CG
CD
Dr. Ahmed H. Madian-VLSI 24
(.Solution (cont100λ
3λ CM
4λ
4λ
2λ
3λ
2λ
4λ4λ 2λ
CMP
CP1
Cgate
CP1
Gate capacitance
CG,total = CM + CMP+CP1+CG+CP2
CM = 0.025 * 100λ*3 λ=7.5λ2
CMP = 0.045 * 4λ* 4 λ = 0.72λ2
CP1 = 0.045 * 2λ* 2λ = 0.18λ2
CP2 = 0.045 * 2λ* 2λ = 0.18λ2
CG = 0.7 * 2λ* 3λ = 4.2λ2
CM CMP CP1 Cgate CP1